1 From 0311903940046649e20bd23bca837169eb4525dc Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Wed, 16 Nov 2022 22:48:41 +0100
4 Subject: [PATCH] arm64: dts: qcom: ipq8074: correct PCIe QMP PHY output clock
7 Current PCIe QMP PHY output name were changed in ("arm64: dts: qcom: Fix
8 IPQ8074 PCIe PHY nodes") however it did not account for the fact that GCC
9 driver is relying on the old names to match them as they are being used as
10 the parent for the gcc_pcie0_pipe_clk and gcc_pcie1_pipe_clk.
12 This broke parenting as GCC could not find the parent clock, so fix it by
13 changing to the names that driver is expecting.
15 Fixes: 942bcd33ed45 ("arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes")
16 Signed-off-by: Robert Marko <robimarko@gmail.com>
18 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
19 1 file changed, 2 insertions(+), 2 deletions(-)
21 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
22 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
25 clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
26 clock-names = "pipe0";
27 - clock-output-names = "pcie_0_pipe_clk";
28 + clock-output-names = "pcie20_phy0_pipe_clk";
34 clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
35 clock-names = "pipe0";
36 - clock-output-names = "pcie_1_pipe_clk";
37 + clock-output-names = "pcie20_phy1_pipe_clk";