target/linux/ipq807x/patches-5.15/0128-cpufreq-qcom-nvmem-add-support-for-IPQ8074.patch

   1 From 813f2b5ad002e691b92154037f154b4444eedd54 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Sat, 31 Dec 2022 13:03:41 +0100
   4 Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ8074
   5
   6 IPQ8074 comes in 2 families:
   7 * IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz
   8 * IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz
   9
  10 So, in order to be able to share one OPP table lets add support for IPQ8074
  11 family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074.
  12
  13 IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device
  14 will get created by NVMEM CPUFreq driver.
  15
  16 Signed-off-by: Robert Marko <robimarko@gmail.com>
  17 ---
  18  drivers/cpufreq/cpufreq-dt-platdev.c |  1 +
  19  drivers/cpufreq/qcom-cpufreq-nvmem.c | 39 ++++++++++++++++++++++++++++
  20  2 files changed, 40 insertions(+)
  21
  22 --- a/drivers/cpufreq/cpufreq-dt-platdev.c
  23 +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
  24 @@ -157,6 +157,7 @@ static const struct of_device_id blockli
  25         { .compatible = "ti,omap3", },
  26
  27         { .compatible = "qcom,ipq8064", },
  28 +       { .compatible = "qcom,ipq8074", },
  29         { .compatible = "qcom,apq8064", },
  30         { .compatible = "qcom,msm8974", },
  31         { .compatible = "qcom,msm8960", },
  32 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
  33 +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
  34 @@ -32,6 +32,9 @@
  35
  36  #include <dt-bindings/arm/qcom,ids.h>
  37
  38 +#define IPQ8074_HAWKEYE_VERSION                BIT(0)
  39 +#define IPQ8074_ACORN_VERSION          BIT(1)
  40 +
  41  struct qcom_cpufreq_drv;
  42
  43  struct qcom_cpufreq_match_data {
  44 @@ -218,6 +221,37 @@ len_error:
  45         return ret;
  46  }
  47
  48 +static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
  49 +                                            struct nvmem_cell *speedbin_nvmem,
  50 +                                            char **pvs_name,
  51 +                                            struct qcom_cpufreq_drv *drv)
  52 +{
  53 +       int msm_id;
  54 +       *pvs_name = NULL;
  55 +
  56 +       msm_id = qcom_cpufreq_get_msm_id();
  57 +       if (msm_id < 0)
  58 +               return msm_id;
  59 +
  60 +       switch (msm_id) {
  61 +       case QCOM_ID_IPQ8070A:
  62 +       case QCOM_ID_IPQ8071A:
  63 +               drv->versions = IPQ8074_ACORN_VERSION;
  64 +               break;
  65 +       case QCOM_ID_IPQ8072A:
  66 +       case QCOM_ID_IPQ8074A:
  67 +       case QCOM_ID_IPQ8076A:
  68 +       case QCOM_ID_IPQ8078A:
  69 +               drv->versions = IPQ8074_HAWKEYE_VERSION;
  70 +               break;
  71 +       default:
  72 +               BUG();
  73 +               break;
  74 +       }
  75 +
  76 +       return 0;
  77 +}
  78 +
  79  static const struct qcom_cpufreq_match_data match_data_kryo = {
  80         .get_version = qcom_cpufreq_kryo_name_version,
  81  };
  82 @@ -232,6 +266,10 @@ static const struct qcom_cpufreq_match_d
  83         .genpd_names = qcs404_genpd_names,
  84  };
  85
  86 +static const struct qcom_cpufreq_match_data match_data_ipq8074 = {
  87 +       .get_version = qcom_cpufreq_ipq8074_name_version,
  88 +};
  89 +
  90  static int qcom_cpufreq_probe(struct platform_device *pdev)
  91  {
  92         struct qcom_cpufreq_drv *drv;
  93 @@ -431,6 +469,7 @@ static const struct of_device_id qcom_cp
  94         { .compatible = "qcom,msm8996", .data = &match_data_kryo },
  95         { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
  96         { .compatible = "qcom,ipq8064", .data = &match_data_krait },
  97 +       { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
  98         { .compatible = "qcom,apq8064", .data = &match_data_krait },
  99         { .compatible = "qcom,msm8974", .data = &match_data_krait },
 100         { .compatible = "qcom,msm8960", .data = &match_data_krait },