1 From 6c98adf98236b8644b8f5e1aa7af9f1a88ea2766 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Mon, 11 Apr 2022 14:38:08 +0200
4 Subject: [PATCH] power: Add Qualcomm APM
6 Add Qualcomm APM driver, which allows scaling cache and memory fabrics.
8 Signed-off-by: Robert Marko <robimarko@gmail.com>
10 drivers/power/Kconfig | 1 +
11 drivers/power/Makefile | 1 +
12 drivers/power/qcom/Kconfig | 7 +
13 drivers/power/qcom/Makefile | 1 +
14 drivers/power/qcom/apm.c | 944 +++++++++++++++++++++++++++++++++
15 include/linux/power/qcom/apm.h | 48 ++
16 6 files changed, 1002 insertions(+)
17 create mode 100644 drivers/power/qcom/Kconfig
18 create mode 100644 drivers/power/qcom/Makefile
19 create mode 100644 drivers/power/qcom/apm.c
20 create mode 100644 include/linux/power/qcom/apm.h
22 --- a/drivers/power/Kconfig
23 +++ b/drivers/power/Kconfig
25 # SPDX-License-Identifier: GPL-2.0-only
26 source "drivers/power/reset/Kconfig"
27 source "drivers/power/supply/Kconfig"
28 +source "drivers/power/qcom/Kconfig"
29 --- a/drivers/power/Makefile
30 +++ b/drivers/power/Makefile
32 # SPDX-License-Identifier: GPL-2.0-only
33 obj-$(CONFIG_POWER_RESET) += reset/
34 obj-$(CONFIG_POWER_SUPPLY) += supply/
35 +obj-$(CONFIG_QCOM_APM) += qcom/
37 +++ b/drivers/power/qcom/Kconfig
40 + bool "Qualcomm Technologies Inc platform specific APM driver"
42 + Platform specific driver to manage the power source of
43 + memory arrays. Interfaces with regulator drivers to ensure
44 + SRAM Vmin requirements are met across different performance
47 +++ b/drivers/power/qcom/Makefile
49 +obj-$(CONFIG_QCOM_APM) += apm.o
51 +++ b/drivers/power/qcom/apm.c
54 + * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
56 + * This program is free software; you can redistribute it and/or modify
57 + * it under the terms of the GNU General Public License version 2 and
58 + * only version 2 as published by the Free Software Foundation.
60 + * This program is distributed in the hope that it will be useful,
61 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
62 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
63 + * GNU General Public License for more details.
66 +#define pr_fmt(fmt) "%s: " fmt, __func__
68 +#include <linux/debugfs.h>
69 +#include <linux/delay.h>
70 +#include <linux/of_device.h>
71 +#include <linux/init.h>
72 +#include <linux/io.h>
73 +#include <linux/kernel.h>
74 +#include <linux/list.h>
75 +#include <linux/module.h>
76 +#include <linux/of.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/slab.h>
79 +#include <linux/string.h>
80 +#include <linux/power/qcom/apm.h>
84 + * =============================================================
86 + * | ==========================|============= |
87 + * ___|___ ___|___ ___|___ ___|___ ___|___ ___|___
88 + * | | | | | | | | | | | |
89 + * | APCC | | MX HS | | MX HS | | APCC | | MX HS | | APCC |
90 + * | HS | | | | | | HS | | | | HS |
91 + * |_______| |_______| |_______| |_______| |_______| |_______|
92 + * |_________| |_________| |__________|
94 + * ______|_____ ______|_____ _______|_____
97 + * | CPU MEM | | L2 MEM | | L3 MEM |
98 + * | Arrays | | Arrays | | Arrays |
100 + * |____________| |____________| |_____________|
104 +/* Register value definitions */
105 +#define APCS_GFMUXA_SEL_VAL 0x13
106 +#define APCS_GFMUXA_DESEL_VAL 0x03
107 +#define MSM_APM_MX_MODE_VAL 0x00
108 +#define MSM_APM_APCC_MODE_VAL 0x10
109 +#define MSM_APM_MX_DONE_VAL 0x00
110 +#define MSM_APM_APCC_DONE_VAL 0x03
111 +#define MSM_APM_OVERRIDE_SEL_VAL 0xb0
112 +#define MSM_APM_SEC_CLK_SEL_VAL 0x30
113 +#define SPM_EVENT_SET_VAL 0x01
114 +#define SPM_EVENT_CLEAR_VAL 0x00
116 +/* Register bit mask definitions */
117 +#define MSM_APM_CTL_STS_MASK 0x0f
119 +/* Register offset definitions */
120 +#define APCC_APM_MODE 0x00000098
121 +#define APCC_APM_CTL_STS 0x000000a8
122 +#define APCS_SPARE 0x00000068
123 +#define APCS_VERSION 0x00000fd0
125 +#define HMSS_VERSION_1P2 0x10020000
127 +#define MSM_APM_SWITCH_TIMEOUT_US 10
128 +#define SPM_WAKEUP_DELAY_US 2
129 +#define SPM_EVENT_NUM 6
131 +#define MSM_APM_DRIVER_NAME "qcom,msm-apm"
139 +struct msm_apm_ctrl_dev {
140 + struct list_head list;
141 + struct device *dev;
142 + enum msm_apm_supply supply;
144 + void __iomem *reg_base;
145 + void __iomem *apcs_csr_base;
146 + void __iomem **apcs_spm_events_addr;
147 + void __iomem *apc0_pll_ctl_addr;
148 + void __iomem *apc1_pll_ctl_addr;
150 + struct dentry *debugfs;
154 +#if defined(CONFIG_DEBUG_FS)
155 +static struct dentry *apm_debugfs_base;
158 +static DEFINE_MUTEX(apm_ctrl_list_mutex);
159 +static LIST_HEAD(apm_ctrl_list);
162 + * Get the resources associated with the APM controller from device tree
163 + * and remap all I/O addresses that are relevant to this HW revision.
165 +static int msm_apm_ctrl_devm_ioremap(struct platform_device *pdev,
166 + struct msm_apm_ctrl_dev *ctrl)
168 + struct device *dev = &pdev->dev;
169 + struct resource *res;
170 + static const char *res_name[SPM_EVENT_NUM] = {
180 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
182 + dev_err(dev, "Missing PM APCC Global register physical address");
185 + ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
186 + if (!ctrl->reg_base) {
187 + dev_err(dev, "Failed to map PM APCC Global registers\n");
191 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "apcs-csr");
193 + dev_err(dev, "Missing APCS CSR physical base address");
196 + ctrl->apcs_csr_base = devm_ioremap(dev, res->start, resource_size(res));
197 + if (!ctrl->apcs_csr_base) {
198 + dev_err(dev, "Failed to map APCS CSR registers\n");
202 + ctrl->version = readl_relaxed(ctrl->apcs_csr_base + APCS_VERSION);
204 + if (ctrl->version >= HMSS_VERSION_1P2)
207 + ctrl->apcs_spm_events_addr = devm_kzalloc(&pdev->dev,
209 + * sizeof(void __iomem *),
211 + if (!ctrl->apcs_spm_events_addr) {
212 + dev_err(dev, "Failed to allocate memory for APCS SPM event registers\n");
216 + for (i = 0; i < SPM_EVENT_NUM; i++) {
217 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
220 + dev_err(dev, "Missing address for %s\n", res_name[i]);
225 + ctrl->apcs_spm_events_addr[i] = devm_ioremap(dev, res->start,
226 + resource_size(res));
227 + if (!ctrl->apcs_spm_events_addr[i]) {
228 + dev_err(dev, "Failed to map %s\n", res_name[i]);
233 + dev_dbg(dev, "%s event phys: %pa virt:0x%p\n", res_name[i],
234 + &res->start, ctrl->apcs_spm_events_addr[i]);
237 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
240 + dev_err(dev, "Missing APC0 PLL CTL physical address\n");
245 + ctrl->apc0_pll_ctl_addr = devm_ioremap(dev,
247 + resource_size(res));
248 + if (!ctrl->apc0_pll_ctl_addr) {
249 + dev_err(dev, "Failed to map APC0 PLL CTL register\n");
254 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
257 + dev_err(dev, "Missing APC1 PLL CTL physical address\n");
262 + ctrl->apc1_pll_ctl_addr = devm_ioremap(dev,
264 + resource_size(res));
265 + if (!ctrl->apc1_pll_ctl_addr) {
266 + dev_err(dev, "Failed to map APC1 PLL CTL register\n");
274 + devm_kfree(dev, ctrl->apcs_spm_events_addr);
278 +/* 8953 register offset definition */
279 +#define MSM8953_APM_DLY_CNTR 0x2ac
281 +/* Register field shift definitions */
282 +#define APM_CTL_SEL_SWITCH_DLY_SHIFT 0
283 +#define APM_CTL_RESUME_CLK_DLY_SHIFT 8
284 +#define APM_CTL_HALT_CLK_DLY_SHIFT 16
285 +#define APM_CTL_POST_HALT_DLY_SHIFT 24
287 +/* Register field mask definitions */
288 +#define APM_CTL_SEL_SWITCH_DLY_MASK GENMASK(7, 0)
289 +#define APM_CTL_RESUME_CLK_DLY_MASK GENMASK(15, 8)
290 +#define APM_CTL_HALT_CLK_DLY_MASK GENMASK(23, 16)
291 +#define APM_CTL_POST_HALT_DLY_MASK GENMASK(31, 24)
294 + * Get the resources associated with the msm8953 APM controller from
295 + * device tree, remap all I/O addresses, and program the initial
296 + * register configuration required for the 8953 APM controller device.
298 +static int msm8953_apm_ctrl_init(struct platform_device *pdev,
299 + struct msm_apm_ctrl_dev *ctrl)
301 + struct device *dev = &pdev->dev;
302 + struct resource *res;
303 + u32 delay_counter, val = 0, regval = 0;
306 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pm-apcc-glb");
308 + dev_err(dev, "Missing PM APCC Global register physical address\n");
311 + ctrl->reg_base = devm_ioremap(dev, res->start, resource_size(res));
312 + if (!ctrl->reg_base) {
313 + dev_err(dev, "Failed to map PM APCC Global registers\n");
318 + * Initial APM register configuration required before starting
319 + * APM HW controller.
321 + regval = readl_relaxed(ctrl->reg_base + MSM8953_APM_DLY_CNTR);
324 + if (of_find_property(dev->of_node, "qcom,apm-post-halt-delay", NULL)) {
325 + rc = of_property_read_u32(dev->of_node,
326 + "qcom,apm-post-halt-delay", &delay_counter);
328 + dev_err(dev, "apm-post-halt-delay read failed, rc = %d",
333 + val &= ~APM_CTL_POST_HALT_DLY_MASK;
334 + val |= (delay_counter << APM_CTL_POST_HALT_DLY_SHIFT)
335 + & APM_CTL_POST_HALT_DLY_MASK;
338 + if (of_find_property(dev->of_node, "qcom,apm-halt-clk-delay", NULL)) {
339 + rc = of_property_read_u32(dev->of_node,
340 + "qcom,apm-halt-clk-delay", &delay_counter);
342 + dev_err(dev, "apm-halt-clk-delay read failed, rc = %d",
347 + val &= ~APM_CTL_HALT_CLK_DLY_MASK;
348 + val |= (delay_counter << APM_CTL_HALT_CLK_DLY_SHIFT)
349 + & APM_CTL_HALT_CLK_DLY_MASK;
352 + if (of_find_property(dev->of_node, "qcom,apm-resume-clk-delay", NULL)) {
353 + rc = of_property_read_u32(dev->of_node,
354 + "qcom,apm-resume-clk-delay", &delay_counter);
356 + dev_err(dev, "apm-resume-clk-delay read failed, rc = %d",
361 + val &= ~APM_CTL_RESUME_CLK_DLY_MASK;
362 + val |= (delay_counter << APM_CTL_RESUME_CLK_DLY_SHIFT)
363 + & APM_CTL_RESUME_CLK_DLY_MASK;
366 + if (of_find_property(dev->of_node, "qcom,apm-sel-switch-delay", NULL)) {
367 + rc = of_property_read_u32(dev->of_node,
368 + "qcom,apm-sel-switch-delay", &delay_counter);
370 + dev_err(dev, "apm-sel-switch-delay read failed, rc = %d",
375 + val &= ~APM_CTL_SEL_SWITCH_DLY_MASK;
376 + val |= (delay_counter << APM_CTL_SEL_SWITCH_DLY_SHIFT)
377 + & APM_CTL_SEL_SWITCH_DLY_MASK;
380 + if (val != regval) {
381 + writel_relaxed(val, ctrl->reg_base + MSM8953_APM_DLY_CNTR);
382 + /* make sure write completes before return */
389 +static int msm8996_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
391 + int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
394 + unsigned long flags;
396 + spin_lock_irqsave(&ctrl_dev->lock, flags);
398 + /* Perform revision-specific programming steps */
399 + if (ctrl_dev->version < HMSS_VERSION_1P2) {
400 + /* Clear SPM events */
401 + for (i = 0; i < SPM_EVENT_NUM; i++)
402 + writel_relaxed(SPM_EVENT_CLEAR_VAL,
403 + ctrl_dev->apcs_spm_events_addr[i]);
405 + udelay(SPM_WAKEUP_DELAY_US);
407 + /* Switch APC/CBF to GPLL0 clock */
408 + writel_relaxed(APCS_GFMUXA_SEL_VAL,
409 + ctrl_dev->apcs_csr_base + APCS_SPARE);
411 + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
412 + ctrl_dev->apc0_pll_ctl_addr);
414 + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
415 + ctrl_dev->apc1_pll_ctl_addr);
417 + /* Ensure writes complete before proceeding */
421 + /* Switch arrays to MX supply and wait for its completion */
422 + writel_relaxed(MSM_APM_MX_MODE_VAL, ctrl_dev->reg_base +
425 + /* Ensure write above completes before delaying */
428 + while (timeout > 0) {
429 + regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
430 + if ((regval & MSM_APM_CTL_STS_MASK) ==
431 + MSM_APM_MX_DONE_VAL)
438 + if (timeout == 0) {
440 + dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
444 + /* Perform revision-specific programming steps */
445 + if (ctrl_dev->version < HMSS_VERSION_1P2) {
446 + /* Switch APC/CBF clocks to original source */
447 + writel_relaxed(APCS_GFMUXA_DESEL_VAL,
448 + ctrl_dev->apcs_csr_base + APCS_SPARE);
450 + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
451 + ctrl_dev->apc0_pll_ctl_addr);
453 + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
454 + ctrl_dev->apc1_pll_ctl_addr);
456 + /* Complete clock source switch before SPM event sequence */
459 + /* Set SPM events */
460 + for (i = 0; i < SPM_EVENT_NUM; i++)
461 + writel_relaxed(SPM_EVENT_SET_VAL,
462 + ctrl_dev->apcs_spm_events_addr[i]);
466 + ctrl_dev->supply = MSM_APM_SUPPLY_MX;
467 + dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
470 + spin_unlock_irqrestore(&ctrl_dev->lock, flags);
475 +static int msm8996_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
477 + int i, timeout = MSM_APM_SWITCH_TIMEOUT_US;
480 + unsigned long flags;
482 + spin_lock_irqsave(&ctrl_dev->lock, flags);
484 + /* Perform revision-specific programming steps */
485 + if (ctrl_dev->version < HMSS_VERSION_1P2) {
486 + /* Clear SPM events */
487 + for (i = 0; i < SPM_EVENT_NUM; i++)
488 + writel_relaxed(SPM_EVENT_CLEAR_VAL,
489 + ctrl_dev->apcs_spm_events_addr[i]);
491 + udelay(SPM_WAKEUP_DELAY_US);
493 + /* Switch APC/CBF to GPLL0 clock */
494 + writel_relaxed(APCS_GFMUXA_SEL_VAL,
495 + ctrl_dev->apcs_csr_base + APCS_SPARE);
497 + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
498 + ctrl_dev->apc0_pll_ctl_addr);
500 + writel_relaxed(MSM_APM_OVERRIDE_SEL_VAL,
501 + ctrl_dev->apc1_pll_ctl_addr);
503 + /* Ensure previous writes complete before proceeding */
507 + /* Switch arrays to APCC supply and wait for its completion */
508 + writel_relaxed(MSM_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
511 + /* Ensure write above completes before delaying */
514 + while (timeout > 0) {
515 + regval = readl_relaxed(ctrl_dev->reg_base + APCC_APM_CTL_STS);
516 + if ((regval & MSM_APM_CTL_STS_MASK) ==
517 + MSM_APM_APCC_DONE_VAL)
524 + if (timeout == 0) {
526 + dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
530 + /* Perform revision-specific programming steps */
531 + if (ctrl_dev->version < HMSS_VERSION_1P2) {
532 + /* Set SPM events */
533 + for (i = 0; i < SPM_EVENT_NUM; i++)
534 + writel_relaxed(SPM_EVENT_SET_VAL,
535 + ctrl_dev->apcs_spm_events_addr[i]);
537 + /* Complete SPM event sequence before clock source switch */
540 + /* Switch APC/CBF clocks to original source */
541 + writel_relaxed(APCS_GFMUXA_DESEL_VAL,
542 + ctrl_dev->apcs_csr_base + APCS_SPARE);
544 + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
545 + ctrl_dev->apc0_pll_ctl_addr);
547 + writel_relaxed(MSM_APM_SEC_CLK_SEL_VAL,
548 + ctrl_dev->apc1_pll_ctl_addr);
552 + ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
553 + dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
556 + spin_unlock_irqrestore(&ctrl_dev->lock, flags);
561 +/* 8953 register value definitions */
562 +#define MSM8953_APM_MX_MODE_VAL 0x00
563 +#define MSM8953_APM_APCC_MODE_VAL 0x02
564 +#define MSM8953_APM_MX_DONE_VAL 0x00
565 +#define MSM8953_APM_APCC_DONE_VAL 0x03
567 +/* 8953 register offset definitions */
568 +#define MSM8953_APCC_APM_MODE 0x000002a8
569 +#define MSM8953_APCC_APM_CTL_STS 0x000002b0
571 +/* 8953 constants */
572 +#define MSM8953_APM_SWITCH_TIMEOUT_US 500
574 +/* Register bit mask definitions */
575 +#define MSM8953_APM_CTL_STS_MASK 0x1f
577 +static int msm8953_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
579 + int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
582 + unsigned long flags;
584 + spin_lock_irqsave(&ctrl_dev->lock, flags);
586 + /* Switch arrays to MX supply and wait for its completion */
587 + writel_relaxed(MSM8953_APM_MX_MODE_VAL, ctrl_dev->reg_base +
588 + MSM8953_APCC_APM_MODE);
590 + /* Ensure write above completes before delaying */
593 + while (timeout > 0) {
594 + regval = readl_relaxed(ctrl_dev->reg_base +
595 + MSM8953_APCC_APM_CTL_STS);
596 + if ((regval & MSM8953_APM_CTL_STS_MASK) ==
597 + MSM8953_APM_MX_DONE_VAL)
604 + if (timeout == 0) {
606 + dev_err(ctrl_dev->dev, "APCC to MX APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
609 + ctrl_dev->supply = MSM_APM_SUPPLY_MX;
610 + dev_dbg(ctrl_dev->dev, "APM supply switched to MX\n");
613 + spin_unlock_irqrestore(&ctrl_dev->lock, flags);
618 +static int msm8953_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
620 + int timeout = MSM8953_APM_SWITCH_TIMEOUT_US;
623 + unsigned long flags;
625 + spin_lock_irqsave(&ctrl_dev->lock, flags);
627 + /* Switch arrays to APCC supply and wait for its completion */
628 + writel_relaxed(MSM8953_APM_APCC_MODE_VAL, ctrl_dev->reg_base +
629 + MSM8953_APCC_APM_MODE);
631 + /* Ensure write above completes before delaying */
634 + while (timeout > 0) {
635 + regval = readl_relaxed(ctrl_dev->reg_base +
636 + MSM8953_APCC_APM_CTL_STS);
637 + if ((regval & MSM8953_APM_CTL_STS_MASK) ==
638 + MSM8953_APM_APCC_DONE_VAL)
645 + if (timeout == 0) {
647 + dev_err(ctrl_dev->dev, "MX to APCC APM switch timed out. APCC_APM_CTL_STS=0x%x\n",
650 + ctrl_dev->supply = MSM_APM_SUPPLY_APCC;
651 + dev_dbg(ctrl_dev->dev, "APM supply switched to APCC\n");
654 + spin_unlock_irqrestore(&ctrl_dev->lock, flags);
659 +static int msm_apm_switch_to_mx(struct msm_apm_ctrl_dev *ctrl_dev)
663 + switch (ctrl_dev->msm_id) {
665 + ret = msm8996_apm_switch_to_mx(ctrl_dev);
669 + ret = msm8953_apm_switch_to_mx(ctrl_dev);
676 +static int msm_apm_switch_to_apcc(struct msm_apm_ctrl_dev *ctrl_dev)
680 + switch (ctrl_dev->msm_id) {
682 + ret = msm8996_apm_switch_to_apcc(ctrl_dev);
686 + ret = msm8953_apm_switch_to_apcc(ctrl_dev);
694 + * msm_apm_get_supply() - Returns the supply that is currently
695 + * powering the memory arrays
696 + * @ctrl_dev: Pointer to an MSM APM controller device
698 + * Returns the supply currently selected by the APM.
700 +int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)
702 + return ctrl_dev->supply;
704 +EXPORT_SYMBOL(msm_apm_get_supply);
707 + * msm_apm_set_supply() - Perform the necessary steps to switch the voltage
708 + * source of the memory arrays to a given supply
709 + * @ctrl_dev: Pointer to an MSM APM controller device
710 + * @supply: Power rail to use as supply for the memory
713 + * Returns 0 on success, -ETIMEDOUT on APM switch timeout, or -EPERM if
714 + * the supply is not supported.
716 +int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
717 + enum msm_apm_supply supply)
722 + case MSM_APM_SUPPLY_APCC:
723 + ret = msm_apm_switch_to_apcc(ctrl_dev);
725 + case MSM_APM_SUPPLY_MX:
726 + ret = msm_apm_switch_to_mx(ctrl_dev);
735 +EXPORT_SYMBOL(msm_apm_set_supply);
738 + * msm_apm_ctrl_dev_get() - get a handle to the MSM APM controller linked to
739 + * the device in device tree
740 + * @dev: Pointer to the device
742 + * The device must specify "qcom,apm-ctrl" property in its device tree
743 + * node which points to an MSM APM controller device node.
745 + * Returns an MSM APM controller handle if successful or ERR_PTR on any error.
746 + * If the APM controller device hasn't probed yet, ERR_PTR(-EPROBE_DEFER) is
749 +struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
751 + struct msm_apm_ctrl_dev *ctrl_dev = NULL;
752 + struct msm_apm_ctrl_dev *dev_found = ERR_PTR(-EPROBE_DEFER);
753 + struct device_node *ctrl_node;
755 + if (!dev || !dev->of_node) {
756 + pr_err("Invalid device node\n");
757 + return ERR_PTR(-EINVAL);
760 + ctrl_node = of_parse_phandle(dev->of_node, "qcom,apm-ctrl", 0);
762 + pr_err("Could not find qcom,apm-ctrl property in %s\n",
763 + dev->of_node->full_name);
764 + return ERR_PTR(-ENXIO);
767 + mutex_lock(&apm_ctrl_list_mutex);
768 + list_for_each_entry(ctrl_dev, &apm_ctrl_list, list) {
769 + if (ctrl_dev->dev && ctrl_dev->dev->of_node == ctrl_node) {
770 + dev_found = ctrl_dev;
774 + mutex_unlock(&apm_ctrl_list_mutex);
776 + of_node_put(ctrl_node);
779 +EXPORT_SYMBOL(msm_apm_ctrl_dev_get);
781 +#if defined(CONFIG_DEBUG_FS)
783 +static int apm_supply_dbg_open(struct inode *inode, struct file *filep)
785 + filep->private_data = inode->i_private;
790 +static ssize_t apm_supply_dbg_read(struct file *filep, char __user *ubuf,
791 + size_t count, loff_t *ppos)
793 + struct msm_apm_ctrl_dev *ctrl_dev = filep->private_data;
798 + pr_err("invalid apm ctrl handle\n");
802 + if (ctrl_dev->supply == MSM_APM_SUPPLY_APCC)
803 + len = snprintf(buf, sizeof(buf), "APCC\n");
804 + else if (ctrl_dev->supply == MSM_APM_SUPPLY_MX)
805 + len = snprintf(buf, sizeof(buf), "MX\n");
807 + len = snprintf(buf, sizeof(buf), "ERR\n");
809 + return simple_read_from_buffer(ubuf, count, ppos, buf, len);
812 +static const struct file_operations apm_supply_fops = {
813 + .open = apm_supply_dbg_open,
814 + .read = apm_supply_dbg_read,
817 +static void apm_debugfs_base_init(void)
819 + apm_debugfs_base = debugfs_create_dir("msm-apm", NULL);
821 + if (IS_ERR_OR_NULL(apm_debugfs_base))
822 + pr_err("msm-apm debugfs base directory creation failed\n");
825 +static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
827 + struct dentry *temp;
829 + if (IS_ERR_OR_NULL(apm_debugfs_base)) {
830 + pr_err("Base directory missing, cannot create apm debugfs nodes\n");
834 + ctrl_dev->debugfs = debugfs_create_dir(dev_name(ctrl_dev->dev),
836 + if (IS_ERR_OR_NULL(ctrl_dev->debugfs)) {
837 + pr_err("%s debugfs directory creation failed\n",
838 + dev_name(ctrl_dev->dev));
842 + temp = debugfs_create_file("supply", S_IRUGO, ctrl_dev->debugfs,
843 + ctrl_dev, &apm_supply_fops);
844 + if (IS_ERR_OR_NULL(temp)) {
845 + pr_err("supply mode creation failed\n");
850 +static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
852 + if (!IS_ERR_OR_NULL(ctrl_dev->debugfs))
853 + debugfs_remove_recursive(ctrl_dev->debugfs);
856 +static void apm_debugfs_base_remove(void)
858 + debugfs_remove_recursive(apm_debugfs_base);
862 +static void apm_debugfs_base_init(void)
865 +static void apm_debugfs_init(struct msm_apm_ctrl_dev *ctrl_dev)
868 +static void apm_debugfs_deinit(struct msm_apm_ctrl_dev *ctrl_dev)
871 +static void apm_debugfs_base_remove(void)
876 +static struct of_device_id msm_apm_match_table[] = {
878 + .compatible = "qcom,msm-apm",
879 + .data = (void *)(uintptr_t)MSM8996_ID,
882 + .compatible = "qcom,msm8953-apm",
883 + .data = (void *)(uintptr_t)MSM8953_ID,
886 + .compatible = "qcom,ipq807x-apm",
887 + .data = (void *)(uintptr_t)IPQ807x_ID,
892 +static int msm_apm_probe(struct platform_device *pdev)
894 + struct device *dev = &pdev->dev;
895 + struct msm_apm_ctrl_dev *ctrl;
896 + const struct of_device_id *match;
899 + dev_dbg(dev, "probing MSM Array Power Mux driver\n");
901 + if (!dev->of_node) {
902 + dev_err(dev, "Device tree node is missing\n");
906 + match = of_match_device(msm_apm_match_table, dev);
910 + ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
912 + dev_err(dev, "MSM APM controller memory allocation failed\n");
916 + INIT_LIST_HEAD(&ctrl->list);
917 + spin_lock_init(&ctrl->lock);
919 + ctrl->msm_id = (uintptr_t)match->data;
920 + platform_set_drvdata(pdev, ctrl);
922 + switch (ctrl->msm_id) {
924 + ret = msm_apm_ctrl_devm_ioremap(pdev, ctrl);
926 + dev_err(dev, "Failed to add APM controller device\n");
932 + ret = msm8953_apm_ctrl_init(pdev, ctrl);
934 + dev_err(dev, "Failed to initialize APM controller device: ret=%d\n",
940 + dev_err(dev, "unable to add APM controller device for msm_id:%d\n",
945 + apm_debugfs_init(ctrl);
946 + mutex_lock(&apm_ctrl_list_mutex);
947 + list_add_tail(&ctrl->list, &apm_ctrl_list);
948 + mutex_unlock(&apm_ctrl_list_mutex);
950 + dev_dbg(dev, "MSM Array Power Mux driver probe successful");
955 +static int msm_apm_remove(struct platform_device *pdev)
957 + struct msm_apm_ctrl_dev *ctrl_dev;
959 + ctrl_dev = platform_get_drvdata(pdev);
961 + mutex_lock(&apm_ctrl_list_mutex);
962 + list_del(&ctrl_dev->list);
963 + mutex_unlock(&apm_ctrl_list_mutex);
964 + apm_debugfs_deinit(ctrl_dev);
970 +static struct platform_driver msm_apm_driver = {
972 + .name = MSM_APM_DRIVER_NAME,
973 + .of_match_table = msm_apm_match_table,
974 + .owner = THIS_MODULE,
976 + .probe = msm_apm_probe,
977 + .remove = msm_apm_remove,
980 +static int __init msm_apm_init(void)
982 + apm_debugfs_base_init();
983 + return platform_driver_register(&msm_apm_driver);
986 +static void __exit msm_apm_exit(void)
988 + platform_driver_unregister(&msm_apm_driver);
989 + apm_debugfs_base_remove();
992 +arch_initcall(msm_apm_init);
993 +module_exit(msm_apm_exit);
995 +MODULE_DESCRIPTION("MSM Array Power Mux driver");
996 +MODULE_LICENSE("GPL v2");
998 +++ b/include/linux/power/qcom/apm.h
1001 + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
1003 + * This program is free software; you can redistribute it and/or modify
1004 + * it under the terms of the GNU General Public License version 2 and
1005 + * only version 2 as published by the Free Software Foundation.
1007 + * This program is distributed in the hope that it will be useful,
1008 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1009 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1010 + * GNU General Public License for more details.
1013 +#ifndef __LINUX_POWER_QCOM_APM_H__
1014 +#define __LINUX_POWER_QCOM_APM_H__
1016 +#include <linux/device.h>
1017 +#include <linux/err.h>
1020 + * enum msm_apm_supply - supported power rails to supply memory arrays
1021 + * %MSM_APM_SUPPLY_APCC: to enable selection of VDD_APCC rail as supply
1022 + * %MSM_APM_SUPPLY_MX: to enable selection of VDD_MX rail as supply
1024 +enum msm_apm_supply {
1025 + MSM_APM_SUPPLY_APCC,
1026 + MSM_APM_SUPPLY_MX,
1029 +/* Handle used to identify an APM controller device */
1030 +struct msm_apm_ctrl_dev;
1032 +#ifdef CONFIG_QCOM_APM
1033 +struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev);
1034 +int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
1035 + enum msm_apm_supply supply);
1036 +int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev);
1039 +static inline struct msm_apm_ctrl_dev *msm_apm_ctrl_dev_get(struct device *dev)
1040 +{ return ERR_PTR(-EPERM); }
1041 +static inline int msm_apm_set_supply(struct msm_apm_ctrl_dev *ctrl_dev,
1042 + enum msm_apm_supply supply)
1044 +static inline int msm_apm_get_supply(struct msm_apm_ctrl_dev *ctrl_dev)