1 From ccc5b088058bccdf454bd296867c47e56c415cde Mon Sep 17 00:00:00 2001
2 From: Chukun Pan <amadeus@jmu.edu.cn>
3 Date: Fri, 1 Oct 2021 22:54:21 +0800
4 Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
6 Add node to support the QUP5 I2C controller inside of IPQ8074.
7 It is exactly the same as QUP2 controllers.
8 Some routers like ZTE MF269 use this bus.
10 Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
11 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
12 Link: https://lore.kernel.org/r/20211001145421.18302-1-amadeus@jmu.edu.cn
14 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++
15 1 file changed, 15 insertions(+)
17 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
18 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
23 + blsp1_i2c5: i2c@78b9000 {
24 + compatible = "qcom,i2c-qup-v2.2.1";
25 + #address-cells = <1>;
27 + reg = <0x78b9000 0x600>;
28 + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
29 + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
30 + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
31 + clock-names = "iface", "core";
32 + clock-frequency = <400000>;
33 + dmas = <&blsp_dma 21>, <&blsp_dma 20>;
34 + dma-names = "rx", "tx";
35 + status = "disabled";
38 blsp1_i2c6: i2c@78ba000 {
39 compatible = "qcom,i2c-qup-v2.2.1";