target/linux/ixp4xx/patches-6.1/0008-ARM-dts-usr8200-Fix-phy-registers.patch

   1 From a1ab45966e5a21841af58742adf27725e523d303 Mon Sep 17 00:00:00 2001
   2 From: Linus Walleij <linus.walleij@linaro.org>
   3 Date: Sat, 14 Oct 2023 19:53:24 +0200
   4 Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
   5
   6 The MV88E6060 switch has internal PHY registers at MDIO
   7 addresses 0x00..0x04. Tie each port to the corresponding
   8 PHY.
   9
  10 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  11 ---
  12  .../dts/intel-ixp42x-usrobotics-usr8200.dts   | 22 +++++++++++++++++++
  13  1 file changed, 22 insertions(+)
  14
  15 --- a/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
  16 +++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
  17 @@ -165,6 +165,24 @@
  18                                 #address-cells = <1>;
  19                                 #size-cells = <0>;
  20
  21 +                               /*
  22 +                                * PHY 0..4 are internal to the MV88E6060 switch but appear
  23 +                                * as independent devices.
  24 +                                */
  25 +                               phy0: ethernet-phy@0 {
  26 +                                       reg = <0>;
  27 +                               };
  28 +                               phy1: ethernet-phy@1 {
  29 +                                       reg = <1>;
  30 +                               };
  31 +                               phy2: ethernet-phy@2 {
  32 +                                       reg = <2>;
  33 +                               };
  34 +                               phy3: ethernet-phy@3 {
  35 +                                       reg = <3>;
  36 +                               };
  37 +
  38 +                               /* Altima AMI101L used by the WAN port */
  39                                 phy9: ethernet-phy@9 {
  40                                         reg = <9>;
  41                                 };
  42 @@ -181,21 +199,25 @@
  43                                                 port@0 {
  44                                                         reg = <0>;
  45                                                         label = "lan1";
  46 +                                                       phy-handle = <&phy0>;
  47                                                 };
  48
  49                                                 port@1 {
  50                                                         reg = <1>;
  51                                                         label = "lan2";
  52 +                                                       phy-handle = <&phy1>;
  53                                                 };
  54
  55                                                 port@2 {
  56                                                         reg = <2>;
  57                                                         label = "lan3";
  58 +                                                       phy-handle = <&phy2>;
  59                                                 };
  60
  61                                                 port@3 {
  62                                                         reg = <3>;
  63                                                         label = "lan4";
  64 +                                                       phy-handle = <&phy3>;
  65                                                 };
  66
  67                                                 port@5 {