target/linux/kirkwood/patches-3.10/0006-pci-PCIe-driver-for-Marvell-Armada-370-XP-systems.patch

   1 From b18ed8465d6c2e3b7057d5bb2fc3da5cb15e3fb1 Mon Sep 17 00:00:00 2001
   2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   3 Date: Fri, 18 Jan 2013 17:42:58 +0100
   4 Subject: [PATCH 06/29] pci: PCIe driver for Marvell Armada 370/XP systems
   5
   6 This driver implements the support for the PCIe interfaces on the
   7 Marvell Armada 370/XP ARM SoCs. In the future, it might be extended to
   8 cover earlier families of Marvell SoCs, such as Dove, Orion and
   9 Kirkwood.
  10
  11 The driver implements the hw_pci operations needed by the core ARM PCI
  12 code to setup PCI devices and get their corresponding IRQs, and the
  13 pci_ops operations that are used by the PCI core to read/write the
  14 configuration space of PCI devices.
  15
  16 Since the PCIe interfaces of Marvell SoCs are completely separate and
  17 not linked together in a bus, this driver sets up an emulated PCI host
  18 bridge, with one PCI-to-PCI bridge as child for each hardware PCIe
  19 interface.
  20
  21 In addition, this driver enumerates the different PCIe slots, and for
  22 those having a device plugged in, it sets up the necessary address
  23 decoding windows, using the mvebu-mbus driver.
  24
  25 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  26 Acked-by: Bjorn Helgaas <bhelgaas@google.com>
  27 ---
  28  .../devicetree/bindings/pci/mvebu-pci.txt          | 220 ++++++
  29  drivers/pci/Kconfig                                |   2 +
  30  drivers/pci/Makefile                               |   3 +
  31  drivers/pci/host/Kconfig                           |   8 +
  32  drivers/pci/host/Makefile                          |   1 +
  33  drivers/pci/host/pci-mvebu.c                       | 879 +++++++++++++++++++++
  34  6 files changed, 1113 insertions(+)
  35  create mode 100644 Documentation/devicetree/bindings/pci/mvebu-pci.txt
  36  create mode 100644 drivers/pci/host/Kconfig
  37  create mode 100644 drivers/pci/host/Makefile
  38  create mode 100644 drivers/pci/host/pci-mvebu.c
  39
  40 diff --git a/Documentation/devicetree/bindings/pci/mvebu-pci.txt b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
  41 new file mode 100644
  42 index 0000000..eb69d92
  43 --- /dev/null
  44 +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
  45 @@ -0,0 +1,220 @@
  46 +* Marvell EBU PCIe interfaces
  47 +
  48 +Mandatory properties:
  49 +- compatible: one of the following values:
  50 +    marvell,armada-370-pcie
  51 +    marvell,armada-xp-pcie
  52 +- #address-cells, set to <3>
  53 +- #size-cells, set to <2>
  54 +- #interrupt-cells, set to <1>
  55 +- bus-range: PCI bus numbers covered
  56 +- device_type, set to "pci"
  57 +- ranges: ranges for the PCI memory and I/O regions, as well as the
  58 +  MMIO registers to control the PCIe interfaces.
  59 +
  60 +In addition, the Device Tree node must have sub-nodes describing each
  61 +PCIe interface, having the following mandatory properties:
  62 +- reg: used only for interrupt mapping, so only the first four bytes
  63 +  are used to refer to the correct bus number and device number.
  64 +- assigned-addresses: reference to the MMIO registers used to control
  65 +  this PCIe interface.
  66 +- clocks: the clock associated to this PCIe interface
  67 +- marvell,pcie-port: the physical PCIe port number
  68 +- status: either "disabled" or "okay"
  69 +- device_type, set to "pci"
  70 +- #address-cells, set to <3>
  71 +- #size-cells, set to <2>
  72 +- #interrupt-cells, set to <1>
  73 +- ranges, empty property.
  74 +- interrupt-map-mask and interrupt-map, standard PCI properties to
  75 +  define the mapping of the PCIe interface to interrupt numbers.
  76 +
  77 +and the following optional properties:
  78 +- marvell,pcie-lane: the physical PCIe lane number, for ports having
  79 +  multiple lanes. If this property is not found, we assume that the
  80 +  value is 0.
  81 +
  82 +Example:
  83 +
  84 +pcie-controller {
  85 +       compatible = "marvell,armada-xp-pcie";
  86 +       status = "disabled";
  87 +       device_type = "pci";
  88 +
  89 +       #address-cells = <3>;
  90 +       #size-cells = <2>;
  91 +
  92 +       bus-range = <0x00 0xff>;
  93 +
  94 +       ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
  95 +                 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
  96 +                 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
  97 +                 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
  98 +                 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
  99 +                 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
 100 +                 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
 101 +                 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
 102 +                 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
 103 +                 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
 104 +                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 105 +                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
 106 +
 107 +       pcie@1,0 {
 108 +               device_type = "pci";
 109 +               assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
 110 +               reg = <0x0800 0 0 0 0>;
 111 +               #address-cells = <3>;
 112 +               #size-cells = <2>;
 113 +               #interrupt-cells = <1>;
 114 +               ranges;
 115 +               interrupt-map-mask = <0 0 0 0>;
 116 +               interrupt-map = <0 0 0 0 &mpic 58>;
 117 +               marvell,pcie-port = <0>;
 118 +               marvell,pcie-lane = <0>;
 119 +               clocks = <&gateclk 5>;
 120 +               status = "disabled";
 121 +       };
 122 +
 123 +       pcie@2,0 {
 124 +               device_type = "pci";
 125 +               assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
 126 +               reg = <0x1000 0 0 0 0>;
 127 +               #address-cells = <3>;
 128 +               #size-cells = <2>;
 129 +               #interrupt-cells = <1>;
 130 +               ranges;
 131 +               interrupt-map-mask = <0 0 0 0>;
 132 +               interrupt-map = <0 0 0 0 &mpic 59>;
 133 +               marvell,pcie-port = <0>;
 134 +               marvell,pcie-lane = <1>;
 135 +               clocks = <&gateclk 6>;
 136 +               status = "disabled";
 137 +       };
 138 +
 139 +       pcie@3,0 {
 140 +               device_type = "pci";
 141 +               assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
 142 +               reg = <0x1800 0 0 0 0>;
 143 +               #address-cells = <3>;
 144 +               #size-cells = <2>;
 145 +               #interrupt-cells = <1>;
 146 +               ranges;
 147 +               interrupt-map-mask = <0 0 0 0>;
 148 +               interrupt-map = <0 0 0 0 &mpic 60>;
 149 +               marvell,pcie-port = <0>;
 150 +               marvell,pcie-lane = <2>;
 151 +               clocks = <&gateclk 7>;
 152 +               status = "disabled";
 153 +       };
 154 +
 155 +       pcie@4,0 {
 156 +               device_type = "pci";
 157 +               assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
 158 +               reg = <0x2000 0 0 0 0>;
 159 +               #address-cells = <3>;
 160 +               #size-cells = <2>;
 161 +               #interrupt-cells = <1>;
 162 +               ranges;
 163 +               interrupt-map-mask = <0 0 0 0>;
 164 +               interrupt-map = <0 0 0 0 &mpic 61>;
 165 +               marvell,pcie-port = <0>;
 166 +               marvell,pcie-lane = <3>;
 167 +               clocks = <&gateclk 8>;
 168 +               status = "disabled";
 169 +       };
 170 +
 171 +       pcie@5,0 {
 172 +               device_type = "pci";
 173 +               assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
 174 +               reg = <0x2800 0 0 0 0>;
 175 +               #address-cells = <3>;
 176 +               #size-cells = <2>;
 177 +               #interrupt-cells = <1>;
 178 +               ranges;
 179 +               interrupt-map-mask = <0 0 0 0>;
 180 +               interrupt-map = <0 0 0 0 &mpic 62>;
 181 +               marvell,pcie-port = <1>;
 182 +               marvell,pcie-lane = <0>;
 183 +               clocks = <&gateclk 9>;
 184 +               status = "disabled";
 185 +       };
 186 +
 187 +       pcie@6,0 {
 188 +               device_type = "pci";
 189 +               assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
 190 +               reg = <0x3000 0 0 0 0>;
 191 +               #address-cells = <3>;
 192 +               #size-cells = <2>;
 193 +               #interrupt-cells = <1>;
 194 +               ranges;
 195 +               interrupt-map-mask = <0 0 0 0>;
 196 +               interrupt-map = <0 0 0 0 &mpic 63>;
 197 +               marvell,pcie-port = <1>;
 198 +               marvell,pcie-lane = <1>;
 199 +               clocks = <&gateclk 10>;
 200 +               status = "disabled";
 201 +       };
 202 +
 203 +       pcie@7,0 {
 204 +               device_type = "pci";
 205 +               assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
 206 +               reg = <0x3800 0 0 0 0>;
 207 +               #address-cells = <3>;
 208 +               #size-cells = <2>;
 209 +               #interrupt-cells = <1>;
 210 +               ranges;
 211 +               interrupt-map-mask = <0 0 0 0>;
 212 +               interrupt-map = <0 0 0 0 &mpic 64>;
 213 +               marvell,pcie-port = <1>;
 214 +               marvell,pcie-lane = <2>;
 215 +               clocks = <&gateclk 11>;
 216 +               status = "disabled";
 217 +       };
 218 +
 219 +       pcie@8,0 {
 220 +               device_type = "pci";
 221 +               assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
 222 +               reg = <0x4000 0 0 0 0>;
 223 +               #address-cells = <3>;
 224 +               #size-cells = <2>;
 225 +               #interrupt-cells = <1>;
 226 +               ranges;
 227 +               interrupt-map-mask = <0 0 0 0>;
 228 +               interrupt-map = <0 0 0 0 &mpic 65>;
 229 +               marvell,pcie-port = <1>;
 230 +               marvell,pcie-lane = <3>;
 231 +               clocks = <&gateclk 12>;
 232 +               status = "disabled";
 233 +       };
 234 +       pcie@9,0 {
 235 +               device_type = "pci";
 236 +               assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
 237 +               reg = <0x4800 0 0 0 0>;
 238 +               #address-cells = <3>;
 239 +               #size-cells = <2>;
 240 +               #interrupt-cells = <1>;
 241 +               ranges;
 242 +               interrupt-map-mask = <0 0 0 0>;
 243 +               interrupt-map = <0 0 0 0 &mpic 99>;
 244 +               marvell,pcie-port = <2>;
 245 +               marvell,pcie-lane = <0>;
 246 +               clocks = <&gateclk 26>;
 247 +               status = "disabled";
 248 +       };
 249 +
 250 +       pcie@10,0 {
 251 +               device_type = "pci";
 252 +               assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
 253 +               reg = <0x5000 0 0 0 0>;
 254 +               #address-cells = <3>;
 255 +               #size-cells = <2>;
 256 +               #interrupt-cells = <1>;
 257 +               ranges;
 258 +               interrupt-map-mask = <0 0 0 0>;
 259 +               interrupt-map = <0 0 0 0 &mpic 103>;
 260 +               marvell,pcie-port = <3>;
 261 +               marvell,pcie-lane = <0>;
 262 +               clocks = <&gateclk 27>;
 263 +               status = "disabled";
 264 +       };
 265 +};
 266 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
 267 index 6d51aa6..ac45398 100644
 268 --- a/drivers/pci/Kconfig
 269 +++ b/drivers/pci/Kconfig
 270 @@ -119,3 +119,5 @@ config PCI_IOAPIC
 271  config PCI_LABEL
 272         def_bool y if (DMI || ACPI)
 273         select NLS
 274 +
 275 +source "drivers/pci/host/Kconfig"
 276 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
 277 index 0c3efcf..6ebf5bf 100644
 278 --- a/drivers/pci/Makefile
 279 +++ b/drivers/pci/Makefile
 280 @@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 281  obj-$(CONFIG_OF) += of.o
 282
 283  ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
 284 +
 285 +# PCI host controller drivers
 286 +obj-y += host/
 287 diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
 288 new file mode 100644
 289 index 0000000..6918fbc
 290 --- /dev/null
 291 +++ b/drivers/pci/host/Kconfig
 292 @@ -0,0 +1,8 @@
 293 +menu "PCI host controller drivers"
 294 +       depends on PCI
 295 +
 296 +config PCI_MVEBU
 297 +       bool "Marvell EBU PCIe controller"
 298 +       depends on ARCH_MVEBU
 299 +
 300 +endmenu
 301 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
 302 new file mode 100644
 303 index 0000000..5ea2d8b
 304 --- /dev/null
 305 +++ b/drivers/pci/host/Makefile
 306 @@ -0,0 +1 @@
 307 +obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
 308 diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
 309 new file mode 100644
 310 index 0000000..b0ee63b
 311 --- /dev/null
 312 +++ b/drivers/pci/host/pci-mvebu.c
 313 @@ -0,0 +1,879 @@
 314 +/*
 315 + * PCIe driver for Marvell Armada 370 and Armada XP SoCs
 316 + *
 317 + * This file is licensed under the terms of the GNU General Public
 318 + * License version 2.  This program is licensed "as is" without any
 319 + * warranty of any kind, whether express or implied.
 320 + */
 321 +
 322 +#include <linux/kernel.h>
 323 +#include <linux/pci.h>
 324 +#include <linux/clk.h>
 325 +#include <linux/module.h>
 326 +#include <linux/mbus.h>
 327 +#include <linux/slab.h>
 328 +#include <linux/platform_device.h>
 329 +#include <linux/of_address.h>
 330 +#include <linux/of_pci.h>
 331 +#include <linux/of_irq.h>
 332 +#include <linux/of_platform.h>
 333 +
 334 +/*
 335 + * PCIe unit register offsets.
 336 + */
 337 +#define PCIE_DEV_ID_OFF                0x0000
 338 +#define PCIE_CMD_OFF           0x0004
 339 +#define PCIE_DEV_REV_OFF       0x0008
 340 +#define PCIE_BAR_LO_OFF(n)     (0x0010 + ((n) << 3))
 341 +#define PCIE_BAR_HI_OFF(n)     (0x0014 + ((n) << 3))
 342 +#define PCIE_HEADER_LOG_4_OFF  0x0128
 343 +#define PCIE_BAR_CTRL_OFF(n)   (0x1804 + (((n) - 1) * 4))
 344 +#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
 345 +#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
 346 +#define PCIE_WIN04_REMAP_OFF(n)        (0x182c + ((n) << 4))
 347 +#define PCIE_WIN5_CTRL_OFF     0x1880
 348 +#define PCIE_WIN5_BASE_OFF     0x1884
 349 +#define PCIE_WIN5_REMAP_OFF    0x188c
 350 +#define PCIE_CONF_ADDR_OFF     0x18f8
 351 +#define  PCIE_CONF_ADDR_EN             0x80000000
 352 +#define  PCIE_CONF_REG(r)              ((((r) & 0xf00) << 16) | ((r) & 0xfc))
 353 +#define  PCIE_CONF_BUS(b)              (((b) & 0xff) << 16)
 354 +#define  PCIE_CONF_DEV(d)              (((d) & 0x1f) << 11)
 355 +#define  PCIE_CONF_FUNC(f)             (((f) & 0x7) << 8)
 356 +#define  PCIE_CONF_ADDR(bus, devfn, where) \
 357 +       (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))    | \
 358 +        PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
 359 +        PCIE_CONF_ADDR_EN)
 360 +#define PCIE_CONF_DATA_OFF     0x18fc
 361 +#define PCIE_MASK_OFF          0x1910
 362 +#define  PCIE_MASK_ENABLE_INTS          0x0f000000
 363 +#define PCIE_CTRL_OFF          0x1a00
 364 +#define  PCIE_CTRL_X1_MODE             0x0001
 365 +#define PCIE_STAT_OFF          0x1a04
 366 +#define  PCIE_STAT_BUS                  0xff00
 367 +#define  PCIE_STAT_LINK_DOWN           BIT(0)
 368 +#define PCIE_DEBUG_CTRL         0x1a60
 369 +#define  PCIE_DEBUG_SOFT_RESET         BIT(20)
 370 +
 371 +/*
 372 + * This product ID is registered by Marvell, and used when the Marvell
 373 + * SoC is not the root complex, but an endpoint on the PCIe bus. It is
 374 + * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
 375 + * bridge.
 376 + */
 377 +#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
 378 +
 379 +/* PCI configuration space of a PCI-to-PCI bridge */
 380 +struct mvebu_sw_pci_bridge {
 381 +       u16 vendor;
 382 +       u16 device;
 383 +       u16 command;
 384 +       u16 status;
 385 +       u16 class;
 386 +       u8 interface;
 387 +       u8 revision;
 388 +       u8 bist;
 389 +       u8 header_type;
 390 +       u8 latency_timer;
 391 +       u8 cache_line_size;
 392 +       u32 bar[2];
 393 +       u8 primary_bus;
 394 +       u8 secondary_bus;
 395 +       u8 subordinate_bus;
 396 +       u8 secondary_latency_timer;
 397 +       u8 iobase;
 398 +       u8 iolimit;
 399 +       u16 secondary_status;
 400 +       u16 membase;
 401 +       u16 memlimit;
 402 +       u16 prefmembase;
 403 +       u16 prefmemlimit;
 404 +       u32 prefbaseupper;
 405 +       u32 preflimitupper;
 406 +       u16 iobaseupper;
 407 +       u16 iolimitupper;
 408 +       u8 cappointer;
 409 +       u8 reserved1;
 410 +       u16 reserved2;
 411 +       u32 romaddr;
 412 +       u8 intline;
 413 +       u8 intpin;
 414 +       u16 bridgectrl;
 415 +};
 416 +
 417 +struct mvebu_pcie_port;
 418 +
 419 +/* Structure representing all PCIe interfaces */
 420 +struct mvebu_pcie {
 421 +       struct platform_device *pdev;
 422 +       struct mvebu_pcie_port *ports;
 423 +       struct resource io;
 424 +       struct resource realio;
 425 +       struct resource mem;
 426 +       struct resource busn;
 427 +       int nports;
 428 +};
 429 +
 430 +/* Structure representing one PCIe interface */
 431 +struct mvebu_pcie_port {
 432 +       char *name;
 433 +       void __iomem *base;
 434 +       spinlock_t conf_lock;
 435 +       int haslink;
 436 +       u32 port;
 437 +       u32 lane;
 438 +       int devfn;
 439 +       struct clk *clk;
 440 +       struct mvebu_sw_pci_bridge bridge;
 441 +       struct device_node *dn;
 442 +       struct mvebu_pcie *pcie;
 443 +       phys_addr_t memwin_base;
 444 +       size_t memwin_size;
 445 +       phys_addr_t iowin_base;
 446 +       size_t iowin_size;
 447 +};
 448 +
 449 +static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
 450 +{
 451 +       return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
 452 +}
 453 +
 454 +static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
 455 +{
 456 +       u32 stat;
 457 +
 458 +       stat = readl(port->base + PCIE_STAT_OFF);
 459 +       stat &= ~PCIE_STAT_BUS;
 460 +       stat |= nr << 8;
 461 +       writel(stat, port->base + PCIE_STAT_OFF);
 462 +}
 463 +
 464 +/*
 465 + * Setup PCIE BARs and Address Decode Wins:
 466 + * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
 467 + * WIN[0-3] -> DRAM bank[0-3]
 468 + */
 469 +static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
 470 +{
 471 +       const struct mbus_dram_target_info *dram;
 472 +       u32 size;
 473 +       int i;
 474 +
 475 +       dram = mv_mbus_dram_info();
 476 +
 477 +       /* First, disable and clear BARs and windows. */
 478 +       for (i = 1; i < 3; i++) {
 479 +               writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
 480 +               writel(0, port->base + PCIE_BAR_LO_OFF(i));
 481 +               writel(0, port->base + PCIE_BAR_HI_OFF(i));
 482 +       }
 483 +
 484 +       for (i = 0; i < 5; i++) {
 485 +               writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
 486 +               writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
 487 +               writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
 488 +       }
 489 +
 490 +       writel(0, port->base + PCIE_WIN5_CTRL_OFF);
 491 +       writel(0, port->base + PCIE_WIN5_BASE_OFF);
 492 +       writel(0, port->base + PCIE_WIN5_REMAP_OFF);
 493 +
 494 +       /* Setup windows for DDR banks.  Count total DDR size on the fly. */
 495 +       size = 0;
 496 +       for (i = 0; i < dram->num_cs; i++) {
 497 +               const struct mbus_dram_window *cs = dram->cs + i;
 498 +
 499 +               writel(cs->base & 0xffff0000,
 500 +                      port->base + PCIE_WIN04_BASE_OFF(i));
 501 +               writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
 502 +               writel(((cs->size - 1) & 0xffff0000) |
 503 +                       (cs->mbus_attr << 8) |
 504 +                       (dram->mbus_dram_target_id << 4) | 1,
 505 +                      port->base + PCIE_WIN04_CTRL_OFF(i));
 506 +
 507 +               size += cs->size;
 508 +       }
 509 +
 510 +       /* Round up 'size' to the nearest power of two. */
 511 +       if ((size & (size - 1)) != 0)
 512 +               size = 1 << fls(size);
 513 +
 514 +       /* Setup BAR[1] to all DRAM banks. */
 515 +       writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
 516 +       writel(0, port->base + PCIE_BAR_HI_OFF(1));
 517 +       writel(((size - 1) & 0xffff0000) | 1,
 518 +              port->base + PCIE_BAR_CTRL_OFF(1));
 519 +}
 520 +
 521 +static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
 522 +{
 523 +       u16 cmd;
 524 +       u32 mask;
 525 +
 526 +       /* Point PCIe unit MBUS decode windows to DRAM space. */
 527 +       mvebu_pcie_setup_wins(port);
 528 +
 529 +       /* Master + slave enable. */
 530 +       cmd = readw(port->base + PCIE_CMD_OFF);
 531 +       cmd |= PCI_COMMAND_IO;
 532 +       cmd |= PCI_COMMAND_MEMORY;
 533 +       cmd |= PCI_COMMAND_MASTER;
 534 +       writew(cmd, port->base + PCIE_CMD_OFF);
 535 +
 536 +       /* Enable interrupt lines A-D. */
 537 +       mask = readl(port->base + PCIE_MASK_OFF);
 538 +       mask |= PCIE_MASK_ENABLE_INTS;
 539 +       writel(mask, port->base + PCIE_MASK_OFF);
 540 +}
 541 +
 542 +static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
 543 +                                struct pci_bus *bus,
 544 +                                u32 devfn, int where, int size, u32 *val)
 545 +{
 546 +       writel(PCIE_CONF_ADDR(bus->number, devfn, where),
 547 +              port->base + PCIE_CONF_ADDR_OFF);
 548 +
 549 +       *val = readl(port->base + PCIE_CONF_DATA_OFF);
 550 +
 551 +       if (size == 1)
 552 +               *val = (*val >> (8 * (where & 3))) & 0xff;
 553 +       else if (size == 2)
 554 +               *val = (*val >> (8 * (where & 3))) & 0xffff;
 555 +
 556 +       return PCIBIOS_SUCCESSFUL;
 557 +}
 558 +
 559 +static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
 560 +                                struct pci_bus *bus,
 561 +                                u32 devfn, int where, int size, u32 val)
 562 +{
 563 +       int ret = PCIBIOS_SUCCESSFUL;
 564 +
 565 +       writel(PCIE_CONF_ADDR(bus->number, devfn, where),
 566 +              port->base + PCIE_CONF_ADDR_OFF);
 567 +
 568 +       if (size == 4)
 569 +               writel(val, port->base + PCIE_CONF_DATA_OFF);
 570 +       else if (size == 2)
 571 +               writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
 572 +       else if (size == 1)
 573 +               writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
 574 +       else
 575 +               ret = PCIBIOS_BAD_REGISTER_NUMBER;
 576 +
 577 +       return ret;
 578 +}
 579 +
 580 +static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
 581 +{
 582 +       phys_addr_t iobase;
 583 +
 584 +       /* Are the new iobase/iolimit values invalid? */
 585 +       if (port->bridge.iolimit < port->bridge.iobase ||
 586 +           port->bridge.iolimitupper < port->bridge.iobaseupper) {
 587 +
 588 +               /* If a window was configured, remove it */
 589 +               if (port->iowin_base) {
 590 +                       mvebu_mbus_del_window(port->iowin_base,
 591 +                                             port->iowin_size);
 592 +                       port->iowin_base = 0;
 593 +                       port->iowin_size = 0;
 594 +               }
 595 +
 596 +               return;
 597 +       }
 598 +
 599 +       /*
 600 +        * We read the PCI-to-PCI bridge emulated registers, and
 601 +        * calculate the base address and size of the address decoding
 602 +        * window to setup, according to the PCI-to-PCI bridge
 603 +        * specifications. iobase is the bus address, port->iowin_base
 604 +        * is the CPU address.
 605 +        */
 606 +       iobase = ((port->bridge.iobase & 0xF0) << 8) |
 607 +               (port->bridge.iobaseupper << 16);
 608 +       port->iowin_base = port->pcie->io.start + iobase;
 609 +       port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
 610 +                           (port->bridge.iolimitupper << 16)) -
 611 +                           iobase);
 612 +
 613 +       mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
 614 +                                         port->iowin_size,
 615 +                                         iobase,
 616 +                                         MVEBU_MBUS_PCI_IO);
 617 +
 618 +       pci_ioremap_io(iobase, port->iowin_base);
 619 +}
 620 +
 621 +static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
 622 +{
 623 +       /* Are the new membase/memlimit values invalid? */
 624 +       if (port->bridge.memlimit < port->bridge.membase) {
 625 +
 626 +               /* If a window was configured, remove it */
 627 +               if (port->memwin_base) {
 628 +                       mvebu_mbus_del_window(port->memwin_base,
 629 +                                             port->memwin_size);
 630 +                       port->memwin_base = 0;
 631 +                       port->memwin_size = 0;
 632 +               }
 633 +
 634 +               return;
 635 +       }
 636 +
 637 +       /*
 638 +        * We read the PCI-to-PCI bridge emulated registers, and
 639 +        * calculate the base address and size of the address decoding
 640 +        * window to setup, according to the PCI-to-PCI bridge
 641 +        * specifications.
 642 +        */
 643 +       port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);
 644 +       port->memwin_size  =
 645 +               (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
 646 +               port->memwin_base;
 647 +
 648 +       mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
 649 +                                         port->memwin_size,
 650 +                                         MVEBU_MBUS_NO_REMAP,
 651 +                                         MVEBU_MBUS_PCI_MEM);
 652 +}
 653 +
 654 +/*
 655 + * Initialize the configuration space of the PCI-to-PCI bridge
 656 + * associated with the given PCIe interface.
 657 + */
 658 +static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
 659 +{
 660 +       struct mvebu_sw_pci_bridge *bridge = &port->bridge;
 661 +
 662 +       memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
 663 +
 664 +       bridge->status = PCI_STATUS_CAP_LIST;
 665 +       bridge->class = PCI_CLASS_BRIDGE_PCI;
 666 +       bridge->vendor = PCI_VENDOR_ID_MARVELL;
 667 +       bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
 668 +       bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
 669 +       bridge->cache_line_size = 0x10;
 670 +
 671 +       /* We support 32 bits I/O addressing */
 672 +       bridge->iobase = PCI_IO_RANGE_TYPE_32;
 673 +       bridge->iolimit = PCI_IO_RANGE_TYPE_32;
 674 +}
 675 +
 676 +/*
 677 + * Read the configuration space of the PCI-to-PCI bridge associated to
 678 + * the given PCIe interface.
 679 + */
 680 +static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
 681 +                                 unsigned int where, int size, u32 *value)
 682 +{
 683 +       struct mvebu_sw_pci_bridge *bridge = &port->bridge;
 684 +
 685 +       switch (where & ~3) {
 686 +       case PCI_VENDOR_ID:
 687 +               *value = bridge->device << 16 | bridge->vendor;
 688 +               break;
 689 +
 690 +       case PCI_COMMAND:
 691 +               *value = bridge->status << 16 | bridge->command;
 692 +               break;
 693 +
 694 +       case PCI_CLASS_REVISION:
 695 +               *value = bridge->class << 16 | bridge->interface << 8 |
 696 +                        bridge->revision;
 697 +               break;
 698 +
 699 +       case PCI_CACHE_LINE_SIZE:
 700 +               *value = bridge->bist << 24 | bridge->header_type << 16 |
 701 +                        bridge->latency_timer << 8 | bridge->cache_line_size;
 702 +               break;
 703 +
 704 +       case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
 705 +               *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
 706 +               break;
 707 +
 708 +       case PCI_PRIMARY_BUS:
 709 +               *value = (bridge->secondary_latency_timer << 24 |
 710 +                         bridge->subordinate_bus         << 16 |
 711 +                         bridge->secondary_bus           <<  8 |
 712 +                         bridge->primary_bus);
 713 +               break;
 714 +
 715 +       case PCI_IO_BASE:
 716 +               *value = (bridge->secondary_status << 16 |
 717 +                         bridge->iolimit          <<  8 |
 718 +                         bridge->iobase);
 719 +               break;
 720 +
 721 +       case PCI_MEMORY_BASE:
 722 +               *value = (bridge->memlimit << 16 | bridge->membase);
 723 +               break;
 724 +
 725 +       case PCI_PREF_MEMORY_BASE:
 726 +               *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
 727 +               break;
 728 +
 729 +       case PCI_PREF_BASE_UPPER32:
 730 +               *value = bridge->prefbaseupper;
 731 +               break;
 732 +
 733 +       case PCI_PREF_LIMIT_UPPER32:
 734 +               *value = bridge->preflimitupper;
 735 +               break;
 736 +
 737 +       case PCI_IO_BASE_UPPER16:
 738 +               *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
 739 +               break;
 740 +
 741 +       case PCI_ROM_ADDRESS1:
 742 +               *value = 0;
 743 +               break;
 744 +
 745 +       default:
 746 +               *value = 0xffffffff;
 747 +               return PCIBIOS_BAD_REGISTER_NUMBER;
 748 +       }
 749 +
 750 +       if (size == 2)
 751 +               *value = (*value >> (8 * (where & 3))) & 0xffff;
 752 +       else if (size == 1)
 753 +               *value = (*value >> (8 * (where & 3))) & 0xff;
 754 +
 755 +       return PCIBIOS_SUCCESSFUL;
 756 +}
 757 +
 758 +/* Write to the PCI-to-PCI bridge configuration space */
 759 +static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
 760 +                                    unsigned int where, int size, u32 value)
 761 +{
 762 +       struct mvebu_sw_pci_bridge *bridge = &port->bridge;
 763 +       u32 mask, reg;
 764 +       int err;
 765 +
 766 +       if (size == 4)
 767 +               mask = 0x0;
 768 +       else if (size == 2)
 769 +               mask = ~(0xffff << ((where & 3) * 8));
 770 +       else if (size == 1)
 771 +               mask = ~(0xff << ((where & 3) * 8));
 772 +       else
 773 +               return PCIBIOS_BAD_REGISTER_NUMBER;
 774 +
 775 +       err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
 776 +       if (err)
 777 +               return err;
 778 +
 779 +       value = (reg & mask) | value << ((where & 3) * 8);
 780 +
 781 +       switch (where & ~3) {
 782 +       case PCI_COMMAND:
 783 +               bridge->command = value & 0xffff;
 784 +               bridge->status = value >> 16;
 785 +               break;
 786 +
 787 +       case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
 788 +               bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
 789 +               break;
 790 +
 791 +       case PCI_IO_BASE:
 792 +               /*
 793 +                * We also keep bit 1 set, it is a read-only bit that
 794 +                * indicates we support 32 bits addressing for the
 795 +                * I/O
 796 +                */
 797 +               bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
 798 +               bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
 799 +               bridge->secondary_status = value >> 16;
 800 +               mvebu_pcie_handle_iobase_change(port);
 801 +               break;
 802 +
 803 +       case PCI_MEMORY_BASE:
 804 +               bridge->membase = value & 0xffff;
 805 +               bridge->memlimit = value >> 16;
 806 +               mvebu_pcie_handle_membase_change(port);
 807 +               break;
 808 +
 809 +       case PCI_PREF_MEMORY_BASE:
 810 +               bridge->prefmembase = value & 0xffff;
 811 +               bridge->prefmemlimit = value >> 16;
 812 +               break;
 813 +
 814 +       case PCI_PREF_BASE_UPPER32:
 815 +               bridge->prefbaseupper = value;
 816 +               break;
 817 +
 818 +       case PCI_PREF_LIMIT_UPPER32:
 819 +               bridge->preflimitupper = value;
 820 +               break;
 821 +
 822 +       case PCI_IO_BASE_UPPER16:
 823 +               bridge->iobaseupper = value & 0xffff;
 824 +               bridge->iolimitupper = value >> 16;
 825 +               mvebu_pcie_handle_iobase_change(port);
 826 +               break;
 827 +
 828 +       case PCI_PRIMARY_BUS:
 829 +               bridge->primary_bus             = value & 0xff;
 830 +               bridge->secondary_bus           = (value >> 8) & 0xff;
 831 +               bridge->subordinate_bus         = (value >> 16) & 0xff;
 832 +               bridge->secondary_latency_timer = (value >> 24) & 0xff;
 833 +               mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
 834 +               break;
 835 +
 836 +       default:
 837 +               break;
 838 +       }
 839 +
 840 +       return PCIBIOS_SUCCESSFUL;
 841 +}
 842 +
 843 +static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
 844 +{
 845 +       return sys->private_data;
 846 +}
 847 +
 848 +static struct mvebu_pcie_port *
 849 +mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
 850 +                    int devfn)
 851 +{
 852 +       int i;
 853 +
 854 +       for (i = 0; i < pcie->nports; i++) {
 855 +               struct mvebu_pcie_port *port = &pcie->ports[i];
 856 +               if (bus->number == 0 && port->devfn == devfn)
 857 +                       return port;
 858 +               if (bus->number != 0 &&
 859 +                   port->bridge.secondary_bus == bus->number)
 860 +                       return port;
 861 +       }
 862 +
 863 +       return NULL;
 864 +}
 865 +
 866 +/* PCI configuration space write function */
 867 +static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 868 +                             int where, int size, u32 val)
 869 +{
 870 +       struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
 871 +       struct mvebu_pcie_port *port;
 872 +       unsigned long flags;
 873 +       int ret;
 874 +
 875 +       port = mvebu_pcie_find_port(pcie, bus, devfn);
 876 +       if (!port)
 877 +               return PCIBIOS_DEVICE_NOT_FOUND;
 878 +
 879 +       /* Access the emulated PCI-to-PCI bridge */
 880 +       if (bus->number == 0)
 881 +               return mvebu_sw_pci_bridge_write(port, where, size, val);
 882 +
 883 +       if (!port->haslink || PCI_SLOT(devfn) != 0)
 884 +               return PCIBIOS_DEVICE_NOT_FOUND;
 885 +
 886 +       /* Access the real PCIe interface */
 887 +       spin_lock_irqsave(&port->conf_lock, flags);
 888 +       ret = mvebu_pcie_hw_wr_conf(port, bus,
 889 +                                   PCI_DEVFN(1, PCI_FUNC(devfn)),
 890 +                                   where, size, val);
 891 +       spin_unlock_irqrestore(&port->conf_lock, flags);
 892 +
 893 +       return ret;
 894 +}
 895 +
 896 +/* PCI configuration space read function */
 897 +static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 898 +                             int size, u32 *val)
 899 +{
 900 +       struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
 901 +       struct mvebu_pcie_port *port;
 902 +       unsigned long flags;
 903 +       int ret;
 904 +
 905 +       port = mvebu_pcie_find_port(pcie, bus, devfn);
 906 +       if (!port) {
 907 +               *val = 0xffffffff;
 908 +               return PCIBIOS_DEVICE_NOT_FOUND;
 909 +       }
 910 +
 911 +       /* Access the emulated PCI-to-PCI bridge */
 912 +       if (bus->number == 0)
 913 +               return mvebu_sw_pci_bridge_read(port, where, size, val);
 914 +
 915 +       if (!port->haslink || PCI_SLOT(devfn) != 0) {
 916 +               *val = 0xffffffff;
 917 +               return PCIBIOS_DEVICE_NOT_FOUND;
 918 +       }
 919 +
 920 +       /* Access the real PCIe interface */
 921 +       spin_lock_irqsave(&port->conf_lock, flags);
 922 +       ret = mvebu_pcie_hw_rd_conf(port, bus,
 923 +                                   PCI_DEVFN(1, PCI_FUNC(devfn)),
 924 +                                   where, size, val);
 925 +       spin_unlock_irqrestore(&port->conf_lock, flags);
 926 +
 927 +       return ret;
 928 +}
 929 +
 930 +static struct pci_ops mvebu_pcie_ops = {
 931 +       .read = mvebu_pcie_rd_conf,
 932 +       .write = mvebu_pcie_wr_conf,
 933 +};
 934 +
 935 +static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
 936 +{
 937 +       struct mvebu_pcie *pcie = sys_to_pcie(sys);
 938 +       int i;
 939 +
 940 +       pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
 941 +       pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
 942 +       pci_add_resource(&sys->resources, &pcie->busn);
 943 +
 944 +       for (i = 0; i < pcie->nports; i++) {
 945 +               struct mvebu_pcie_port *port = &pcie->ports[i];
 946 +               mvebu_pcie_setup_hw(port);
 947 +       }
 948 +
 949 +       return 1;
 950 +}
 951 +
 952 +static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 953 +{
 954 +       struct of_irq oirq;
 955 +       int ret;
 956 +
 957 +       ret = of_irq_map_pci(dev, &oirq);
 958 +       if (ret)
 959 +               return ret;
 960 +
 961 +       return irq_create_of_mapping(oirq.controller, oirq.specifier,
 962 +                                    oirq.size);
 963 +}
 964 +
 965 +static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 966 +{
 967 +       struct mvebu_pcie *pcie = sys_to_pcie(sys);
 968 +       struct pci_bus *bus;
 969 +
 970 +       bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
 971 +                                 &mvebu_pcie_ops, sys, &sys->resources);
 972 +       if (!bus)
 973 +               return NULL;
 974 +
 975 +       pci_scan_child_bus(bus);
 976 +
 977 +       return bus;
 978 +}
 979 +
 980 +resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
 981 +                                         const struct resource *res,
 982 +                                         resource_size_t start,
 983 +                                         resource_size_t size,
 984 +                                         resource_size_t align)
 985 +{
 986 +       if (dev->bus->number != 0)
 987 +               return start;
 988 +
 989 +       /*
 990 +        * On the PCI-to-PCI bridge side, the I/O windows must have at
 991 +        * least a 64 KB size and be aligned on their size, and the
 992 +        * memory windows must have at least a 1 MB size and be
 993 +        * aligned on their size
 994 +        */
 995 +       if (res->flags & IORESOURCE_IO)
 996 +               return round_up(start, max((resource_size_t)SZ_64K, size));
 997 +       else if (res->flags & IORESOURCE_MEM)
 998 +               return round_up(start, max((resource_size_t)SZ_1M, size));
 999 +       else
1000 +               return start;
1001 +}
1002 +
1003 +static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
1004 +{
1005 +       struct hw_pci hw;
1006 +
1007 +       memset(&hw, 0, sizeof(hw));
1008 +
1009 +       hw.nr_controllers = 1;
1010 +       hw.private_data   = (void **)&pcie;
1011 +       hw.setup          = mvebu_pcie_setup;
1012 +       hw.scan           = mvebu_pcie_scan_bus;
1013 +       hw.map_irq        = mvebu_pcie_map_irq;
1014 +       hw.ops            = &mvebu_pcie_ops;
1015 +       hw.align_resource = mvebu_pcie_align_resource;
1016 +
1017 +       pci_common_init(&hw);
1018 +}
1019 +
1020 +/*
1021 + * Looks up the list of register addresses encoded into the reg =
1022 + * <...> property for one that matches the given port/lane. Once
1023 + * found, maps it.
1024 + */
1025 +static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
1026 +                                             struct device_node *np,
1027 +                                             struct mvebu_pcie_port *port)
1028 +{
1029 +       struct resource regs;
1030 +       int ret = 0;
1031 +
1032 +       ret = of_address_to_resource(np, 0, &regs);
1033 +       if (ret)
1034 +               return NULL;
1035 +
1036 +       return devm_request_and_ioremap(&pdev->dev, &regs);
1037 +}
1038 +
1039 +static int __init mvebu_pcie_probe(struct platform_device *pdev)
1040 +{
1041 +       struct mvebu_pcie *pcie;
1042 +       struct device_node *np = pdev->dev.of_node;
1043 +       struct of_pci_range range;
1044 +       struct of_pci_range_parser parser;
1045 +       struct device_node *child;
1046 +       int i, ret;
1047 +
1048 +       pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
1049 +                           GFP_KERNEL);
1050 +       if (!pcie)
1051 +               return -ENOMEM;
1052 +
1053 +       pcie->pdev = pdev;
1054 +
1055 +       if (of_pci_range_parser_init(&parser, np))
1056 +               return -EINVAL;
1057 +
1058 +       /* Get the I/O and memory ranges from DT */
1059 +       for_each_of_pci_range(&parser, &range) {
1060 +               unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
1061 +               if (restype == IORESOURCE_IO) {
1062 +                       of_pci_range_to_resource(&range, np, &pcie->io);
1063 +                       of_pci_range_to_resource(&range, np, &pcie->realio);
1064 +                       pcie->io.name = "I/O";
1065 +                       pcie->realio.start = max_t(resource_size_t,
1066 +                                                  PCIBIOS_MIN_IO,
1067 +                                                  range.pci_addr);
1068 +                       pcie->realio.end = min_t(resource_size_t,
1069 +                                                IO_SPACE_LIMIT,
1070 +                                                range.pci_addr + range.size);
1071 +               }
1072 +               if (restype == IORESOURCE_MEM) {
1073 +                       of_pci_range_to_resource(&range, np, &pcie->mem);
1074 +                       pcie->mem.name = "MEM";
1075 +               }
1076 +       }
1077 +
1078 +       /* Get the bus range */
1079 +       ret = of_pci_parse_bus_range(np, &pcie->busn);
1080 +       if (ret) {
1081 +               dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
1082 +                       ret);
1083 +               return ret;
1084 +       }
1085 +
1086 +       for_each_child_of_node(pdev->dev.of_node, child) {
1087 +               if (!of_device_is_available(child))
1088 +                       continue;
1089 +               pcie->nports++;
1090 +       }
1091 +
1092 +       pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
1093 +                                  sizeof(struct mvebu_pcie_port),
1094 +                                  GFP_KERNEL);
1095 +       if (!pcie->ports)
1096 +               return -ENOMEM;
1097 +
1098 +       i = 0;
1099 +       for_each_child_of_node(pdev->dev.of_node, child) {
1100 +               struct mvebu_pcie_port *port = &pcie->ports[i];
1101 +
1102 +               if (!of_device_is_available(child))
1103 +                       continue;
1104 +
1105 +               port->pcie = pcie;
1106 +
1107 +               if (of_property_read_u32(child, "marvell,pcie-port",
1108 +                                        &port->port)) {
1109 +                       dev_warn(&pdev->dev,
1110 +                                "ignoring PCIe DT node, missing pcie-port property\n");
1111 +                       continue;
1112 +               }
1113 +
1114 +               if (of_property_read_u32(child, "marvell,pcie-lane",
1115 +                                        &port->lane))
1116 +                       port->lane = 0;
1117 +
1118 +               port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
1119 +                                      port->port, port->lane);
1120 +
1121 +               port->devfn = of_pci_get_devfn(child);
1122 +               if (port->devfn < 0)
1123 +                       continue;
1124 +
1125 +               port->base = mvebu_pcie_map_registers(pdev, child, port);
1126 +               if (!port->base) {
1127 +                       dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
1128 +                               port->port, port->lane);
1129 +                       continue;
1130 +               }
1131 +
1132 +               if (mvebu_pcie_link_up(port)) {
1133 +                       port->haslink = 1;
1134 +                       dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
1135 +                                port->port, port->lane);
1136 +               } else {
1137 +                       port->haslink = 0;
1138 +                       dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
1139 +                                port->port, port->lane);
1140 +               }
1141 +
1142 +               port->clk = of_clk_get_by_name(child, NULL);
1143 +               if (!port->clk) {
1144 +                       dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
1145 +                              port->port, port->lane);
1146 +                       iounmap(port->base);
1147 +                       port->haslink = 0;
1148 +                       continue;
1149 +               }
1150 +
1151 +               port->dn = child;
1152 +
1153 +               clk_prepare_enable(port->clk);
1154 +               spin_lock_init(&port->conf_lock);
1155 +
1156 +               mvebu_sw_pci_bridge_init(port);
1157 +
1158 +               i++;
1159 +       }
1160 +
1161 +       mvebu_pcie_enable(pcie);
1162 +
1163 +       return 0;
1164 +}
1165 +
1166 +static const struct of_device_id mvebu_pcie_of_match_table[] = {
1167 +       { .compatible = "marvell,armada-xp-pcie", },
1168 +       { .compatible = "marvell,armada-370-pcie", },
1169 +       {},
1170 +};
1171 +MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1172 +
1173 +static struct platform_driver mvebu_pcie_driver = {
1174 +       .driver = {
1175 +               .owner = THIS_MODULE,
1176 +               .name = "mvebu-pcie",
1177 +               .of_match_table =
1178 +                  of_match_ptr(mvebu_pcie_of_match_table),
1179 +       },
1180 +};
1181 +
1182 +static int mvebu_pcie_init(void)
1183 +{
1184 +       return platform_driver_probe(&mvebu_pcie_driver,
1185 +                                    mvebu_pcie_probe);
1186 +}
1187 +
1188 +subsys_initcall(mvebu_pcie_init);
1189 +
1190 +MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1191 +MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1192 +MODULE_LICENSE("GPLv2");
1193 --
1194 1.8.4.rc1
1195