3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
9 compatible = "lantiq,xway", "lantiq,vr9";
16 stdout-path = "serial0:115200n8";
24 compatible = "mips,mips34Kc";
30 compatible = "lantiq,cputemp";
34 compatible = "syscon-reboot";
44 compatible = "lantiq,biu", "simple-bus";
45 reg = <0x1f800000 0x800000>;
46 ranges = <0x0 0x1f800000 0x7fffff>;
49 #interrupt-cells = <1>;
51 compatible = "lantiq,icu";
52 reg = <0x80200 0xc8 /* icu0 */
53 0x80300 0xc8>; /* icu1 */
57 compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
67 compatible = "lantiq,sram", "simple-bus";
68 reg = <0x1f000000 0x800000>;
69 ranges = <0x0 0x1f000000 0x7fffff>;
72 #interrupt-cells = <1>;
74 compatible = "lantiq,eiu-xway";
75 reg = <0x101000 0x1000>;
76 interrupt-parent = <&icu0>;
77 lantiq,eiu-irqs = <166 135 66 40 41 42>;
81 compatible = "lantiq,pmu-xway";
82 reg = <0x102000 0x1000>;
86 compatible = "lantiq,cgu-xway";
87 reg = <0x103000 0x1000>;
91 compatible = "lantiq,dcdc-xrx200";
92 reg = <0x106a00 0x200>;
97 compatible = "lantiq,vmmc-xway";
98 reg = <0x107000 0x300>;
99 interrupt-parent = <&icu0>;
100 interrupts = <150 151 152 153 154 155>;
103 pcie0_phy: phy@106800 {
104 compatible = "lantiq,vrx200-pcie-phy";
105 reg = <0x106800 0x100>;
106 lantiq,rcu = <&rcu0>;
107 lantiq,rcu-endian-offset = <0x4c>;
108 lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
110 resets = <&reset0 12 24>, <&reset0 22 22>;
111 reset-names = "phy", "pcie";
116 #address-cells = <1>;
118 compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
119 reg = <0x203000 0x100>;
120 ranges = <0x0 0x203000 0x100>;
123 reset0: reset-controller@10 {
124 compatible = "lantiq,xrx200-reset";
125 reg = <0x10 4>, <0x14 4>;
130 reset1: reset-controller@48 {
131 compatible = "lantiq,xrx200-reset";
132 reg = <0x48 4>, <0x24 4>;
137 usb_phy0: usb2-phy@18 {
138 compatible = "lantiq,xrx200-usb2-phy";
139 reg = <0x18 4>, <0x38 4>;
142 resets = <&reset1 4 4>, <&reset0 4 4>;
143 reset-names = "phy", "ctrl";
147 usb_phy1: usb2-phy@34 {
148 compatible = "lantiq,xrx200-usb2-phy";
149 reg = <0x34 4>, <0x3c 4>;
152 resets = <&reset1 5 5>, <&reset0 4 4>;
153 reset-names = "phy", "ctrl";
160 compatible = "lantiq,xrx200-fpi", "simple-bus";
161 ranges = <0x0 0x10000000 0xf000000>;
162 reg = <0x1f400000 0x1000>,
163 <0x10000000 0xf000000>;
165 offset-endianness = <0x4c>;
166 #address-cells = <1>;
169 localbus: localbus@0 {
170 #address-cells = <2>;
172 ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
173 1 0 0x4000000 0x4000010>; /* addsel1 */
174 compatible = "lantiq,localbus", "simple-bus";
178 compatible = "lantiq,gptu-xway";
179 reg = <0xe100a00 0x100>;
180 interrupt-parent = <&icu0>;
181 interrupts = <126 127 128 129 130 131>;
185 compatible = "lantiq,usif";
186 reg = <0xda00000 0x1000000>;
187 interrupt-parent = <&icu0>;
188 interrupts = <29 125 107 108 109 110>;
193 compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
194 reg = <0xe100800 0x100>;
195 interrupt-parent = <&icu0>;
196 interrupts = <22 23 24>;
197 interrupt-names = "spi_rx", "spi_tx", "spi_err",
199 #address-cells = <1>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
206 gpio: pinmux@e100b10 {
207 compatible = "lantiq,xrx200-pinctrl";
210 gpio-ranges = <&gpio 0 0 50>;
211 reg = <0xe100b10 0xa0>;
213 gphy0_led0_pins: gphy0-led0 {
215 lantiq,groups = "gphy0 led0";
216 lantiq,function = "gphy";
217 lantiq,open-drain = <0>;
223 gphy0_led1_pins: gphy0-led1 {
225 lantiq,groups = "gphy0 led1";
226 lantiq,function = "gphy";
227 lantiq,open-drain = <0>;
233 gphy0_led2_pins: gphy0-led2 {
235 lantiq,groups = "gphy0 led2";
236 lantiq,function = "gphy";
237 lantiq,open-drain = <0>;
243 gphy1_led0_pins: gphy1-led0 {
245 lantiq,groups = "gphy1 led0";
246 lantiq,function = "gphy";
247 lantiq,open-drain = <0>;
253 gphy1_led1_pins: gphy1-led1 {
255 lantiq,groups = "gphy1 led1";
256 lantiq,function = "gphy";
257 lantiq,open-drain = <0>;
263 gphy1_led2_pins: gphy1-led2 {
265 lantiq,groups = "gphy1 led2";
266 lantiq,function = "gphy";
267 lantiq,open-drain = <0>;
275 lantiq,groups = "mdio";
276 lantiq,function = "mdio";
282 lantiq,groups = "nand cle", "nand ale",
284 lantiq,function = "ebu";
286 lantiq,open-drain = <0>;
290 lantiq,groups = "nand rdy";
291 lantiq,function = "ebu";
297 nand_cs1_pins: nand-cs1 {
299 lantiq,groups = "nand cs1";
300 lantiq,function = "ebu";
301 lantiq,open-drain = <0>;
306 pci_gnt1_pins: pci-gnt1 {
308 lantiq,groups = "gnt1";
309 lantiq,function = "pci";
311 lantiq,open-drain = <0>;
316 pci_req1_pins: pci-req1 {
318 lantiq,groups = "req1";
319 lantiq,function = "pci";
321 lantiq,open-drain = <1>;
328 lantiq,groups = "spi_di";
329 lantiq,function = "spi";
332 lantiq,groups = "spi_do", "spi_clk";
333 lantiq,function = "spi";
338 spi_cs4_pins: spi-cs4 {
340 lantiq,groups = "spi_cs4";
341 lantiq,function = "spi";
348 lantiq,groups = "stp";
349 lantiq,function = "stp";
351 lantiq,open-drain = <0>;
359 compatible = "lantiq,gpio-stp-xway";
360 reg = <0xe100bb0 0x40>;
364 pinctrl-0 = <&stp_pins>;
365 pinctrl-names = "default";
367 lantiq,shadow = <0xffffff>;
368 lantiq,groups = <0x7>;
374 asc1: serial@e100c00 {
375 compatible = "lantiq,asc";
376 reg = <0xe100c00 0x400>;
377 interrupt-parent = <&icu0>;
378 interrupts = <112 113 114>;
382 compatible = "lantiq,deu-xrx200";
383 reg = <0xe103100 0xf00>;
387 compatible = "lantiq,dma-xway";
388 reg = <0xe104100 0x800>;
392 compatible = "lantiq,ebu-xway";
393 reg = <0xe105300 0x100>;
397 #address-cells = <1>;
400 compatible = "lantiq,xrx200-usb";
401 reg = <0xe101000 0x1000
403 interrupt-parent = <&icu0>;
404 interrupts = <62 91>;
407 phy-names = "usb2-phy";
411 #trigger-source-cells = <0>;
416 #address-cells = <1>;
419 compatible = "lantiq,xrx200-usb";
420 reg = <0xe106000 0x1000>;
421 interrupt-parent = <&icu0>;
425 phy-names = "usb2-phy";
429 #trigger-source-cells = <0>;
433 gswip: switch@e108000 {
434 compatible = "lantiq,xrx200-gswip";
435 #address-cells = <1>;
437 reg = < 0xe108000 0x3000 /* switch */
438 0xe10b100 0x70 /* mdio */
439 0xe10b1d8 0x30 /* mii */
445 #address-cells = <1>;
456 #address-cells = <1>;
458 compatible = "lantiq,xrx200-mdio";
462 compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
463 lantiq,rcu = <&rcu0>;
464 #address-cells = <1>;
470 resets = <&reset0 31 30>;
471 reset-names = "gphy";
477 resets = <&reset0 29 28>;
478 reset-names = "gphy";
484 compatible = "lantiq,xrx200-net";
485 reg = <0xe10b308 0x30>; /* pmac */
486 interrupt-parent = <&icu0>;
487 interrupts = <73>, <72>;
488 interrupt-names = "tx", "rx";
489 resets = <&reset0 21 16>, <&reset0 8 8>, <&reset0 3 3>;
490 reset-names = "switch", "ppe", "ppe_dsp";
491 #address-cells = <1>;
501 compatible = "lantiq,mei-xrx200";
502 reg = <0xe116000 0x9c>;
503 interrupt-parent = <&icu0>;
508 compatible = "lantiq,ppe-xrx200";
509 reg = <0xe234000 0x3ffd>;
510 interrupt-parent = <&icu0>;
512 resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>;
513 reset-names = "dsp", "dfe", "tc";
516 pcie0: pcie@d900000 {
517 compatible = "lantiq,pcie-xrx200";
519 #interrupt-cells = <1>;
521 #address-cells = <3>;
523 reg = <0xd900000 0x1000>;
525 interrupt-parent = <&icu0>;
526 interrupts = <161 144>;
528 phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;
531 resets = <&reset0 22 22>;
533 lantiq,rcu = <&rcu0>;
537 gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
543 #address-cells = <3>;
545 #interrupt-cells = <1>;
546 compatible = "lantiq,pci-xway";
547 bus-range = <0x0 0x0>;
548 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
549 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
550 reg = <0x7000000 0x8000 /* config space */
551 0xe105400 0x400>; /* pci bridge */
552 lantiq,bus-clock = <33333333>;
553 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
554 interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */
555 req-mask = <0x1>; /* GNT1 */
562 compatible = "lantiq,vdsl-vrx200";