target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
   7  */
   8
   9 #ifndef _FALCON_IRQ__
  10 #define _FALCON_IRQ__
  11
  12 #define INT_NUM_IRQ0                    8
  13 #define INT_NUM_IM0_IRL0                (INT_NUM_IRQ0 + 0)
  14 #define INT_NUM_IM1_IRL0                (INT_NUM_IM0_IRL0 + 32)
  15 #define INT_NUM_IM2_IRL0                (INT_NUM_IM1_IRL0 + 32)
  16 #define INT_NUM_IM3_IRL0                (INT_NUM_IM2_IRL0 + 32)
  17 #define INT_NUM_IM4_IRL0                (INT_NUM_IM3_IRL0 + 32)
  18 #define INT_NUM_EXTRA_START             (INT_NUM_IM4_IRL0 + 32)
  19 #define INT_NUM_IM_OFFSET               (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
  20
  21 #define MIPS_CPU_TIMER_IRQ                      7
  22
  23 /* HOST IF Event Interrupt */
  24 #define FALCON_IRQ_HOST                         (INT_NUM_IM0_IRL0 + 0)
  25 /* HOST IF Mailbox0 Receive Interrupt */
  26 #define FALCON_IRQ_HOST_MB0_RX                  (INT_NUM_IM0_IRL0 + 1)
  27 /* HOST IF Mailbox0 Transmit Interrupt */
  28 #define FALCON_IRQ_HOST_MB0_TX                  (INT_NUM_IM0_IRL0 + 2)
  29 /* HOST IF Mailbox1 Receive Interrupt */
  30 #define FALCON_IRQ_HOST_MB1_RX                  (INT_NUM_IM0_IRL0 + 3)
  31 /* HOST IF Mailbox1 Transmit Interrupt */
  32 #define FALCON_IRQ_HOST_MB1_TX                  (INT_NUM_IM0_IRL0 + 4)
  33 /* I2C Last Single Data Transfer Request */
  34 #define FALCON_IRQ_I2C_LSREQ                    (INT_NUM_IM0_IRL0 + 8)
  35 /* I2C Single Data Transfer Request */
  36 #define FALCON_IRQ_I2C_SREQ                     (INT_NUM_IM0_IRL0 + 9)
  37 /* I2C Last Burst Data Transfer Request */
  38 #define FALCON_IRQ_I2C_LBREQ                    (INT_NUM_IM0_IRL0 + 10)
  39 /* I2C Burst Data Transfer Request */
  40 #define FALCON_IRQ_I2C_BREQ                     (INT_NUM_IM0_IRL0 + 11)
  41 /* I2C Error Interrupt */
  42 #define FALCON_IRQ_I2C_I2C_ERR                  (INT_NUM_IM0_IRL0 + 12)
  43 /* I2C Protocol Interrupt */
  44 #define FALCON_IRQ_I2C_I2C_P                    (INT_NUM_IM0_IRL0 + 13)
  45 /* SSC Transmit Interrupt */
  46 #define FALCON_IRQ_SSC_T                        (INT_NUM_IM0_IRL0 + 14)
  47 /* SSC Receive Interrupt */
  48 #define FALCON_IRQ_SSC_R                        (INT_NUM_IM0_IRL0 + 15)
  49 /* SSC Error Interrupt */
  50 #define FALCON_IRQ_SSC_E                        (INT_NUM_IM0_IRL0 + 16)
  51 /* SSC Frame Interrupt */
  52 #define FALCON_IRQ_SSC_F                        (INT_NUM_IM0_IRL0 + 17)
  53 /* Advanced Encryption Standard Interrupt */
  54 #define FALCON_IRQ_AES_AES                      (INT_NUM_IM0_IRL0 + 27)
  55 /* Secure Hash Algorithm Interrupt */
  56 #define FALCON_IRQ_SHA_HASH                     (INT_NUM_IM0_IRL0 + 28)
  57 /* PCM Receive Interrupt */
  58 #define FALCON_IRQ_PCM_RX                       (INT_NUM_IM0_IRL0 + 29)
  59 /* PCM Transmit Interrupt */
  60 #define FALCON_IRQ_PCM_TX                       (INT_NUM_IM0_IRL0 + 30)
  61 /* PCM Transmit Crash Interrupt */
  62 #define FALCON_IRQ_PCM_HW2_CRASH                (INT_NUM_IM0_IRL0 + 31)
  63
  64 /* EBU Serial Flash Command Error */
  65 #define FALCON_IRQ_EBU_SF_CMDERR                (INT_NUM_IM1_IRL0 + 0)
  66 /* EBU Serial Flash Command Overwrite Error */
  67 #define FALCON_IRQ_EBU_SF_COVERR                (INT_NUM_IM1_IRL0 + 1)
  68 /* EBU Serial Flash Busy */
  69 #define FALCON_IRQ_EBU_SF_BUSY                  (INT_NUM_IM1_IRL0 + 2)
  70 /* External Interrupt from GPIO P0 */
  71 #define FALCON_IRQ_GPIO_P0                      (INT_NUM_IM1_IRL0 + 4)
  72 /* External Interrupt from GPIO P1 */
  73 #define FALCON_IRQ_GPIO_P1                      (INT_NUM_IM1_IRL0 + 5)
  74 /* External Interrupt from GPIO P2 */
  75 #define FALCON_IRQ_GPIO_P2                      (INT_NUM_IM1_IRL0 + 6)
  76 /* External Interrupt from GPIO P3 */
  77 #define FALCON_IRQ_GPIO_P3                      (INT_NUM_IM1_IRL0 + 7)
  78 /* External Interrupt from GPIO P4 */
  79 #define FALCON_IRQ_GPIO_P4                      (INT_NUM_IM1_IRL0 + 8)
  80 /* 8kHz backup interrupt derived from core-PLL */
  81 #define FALCON_IRQ_FSC_BKP                      (INT_NUM_IM1_IRL0 + 10)
  82 /* FSC Timer Interrupt 0 */
  83 #define FALCON_IRQ_FSCT_CMP0                    (INT_NUM_IM1_IRL0 + 11)
  84 /* FSC Timer Interrupt 1 */
  85 #define FALCON_IRQ_FSCT_CMP1                    (INT_NUM_IM1_IRL0 + 12)
  86 /* 8kHz root interrupt derived from GPON interface */
  87 #define FALCON_IRQ_FSC_ROOT                     (INT_NUM_IM1_IRL0 + 13)
  88 /* Time of Day */
  89 #define FALCON_IRQ_TOD                          (INT_NUM_IM1_IRL0 + 14)
  90 /* PMA Interrupt from IntNode of the 200MHz Domain */
  91 #define FALCON_IRQ_PMA_200M                     (INT_NUM_IM1_IRL0 + 15)
  92 /* PMA Interrupt from IntNode of the TX Clk Domain */
  93 #define FALCON_IRQ_PMA_TX                       (INT_NUM_IM1_IRL0 + 16)
  94 /* PMA Interrupt from IntNode of the RX Clk Domain */
  95 #define FALCON_IRQ_PMA_RX                       (INT_NUM_IM1_IRL0 + 17)
  96 /* SYS1 Interrupt */
  97 #define FALCON_IRQ_SYS1                         (INT_NUM_IM1_IRL0 + 20)
  98 /* SYS GPE Interrupt */
  99 #define FALCON_IRQ_SYS_GPE                      (INT_NUM_IM1_IRL0 + 21)
 100 /* Watchdog Access Error Interrupt */
 101 #define FALCON_IRQ_WDT_AEIR                     (INT_NUM_IM1_IRL0 + 24)
 102 /* Watchdog Prewarning Interrupt */
 103 #define FALCON_IRQ_WDT_PIR                      (INT_NUM_IM1_IRL0 + 25)
 104 /* SBIU interrupt */
 105 #define FALCON_IRQ_SBIU0                        (INT_NUM_IM1_IRL0 + 27)
 106 /* FPI Bus Control Unit Interrupt */
 107 #define FALCON_IRQ_BCU0                         (INT_NUM_IM1_IRL0 + 29)
 108 /* DDR Controller Interrupt */
 109 #define FALCON_IRQ_DDR                          (INT_NUM_IM1_IRL0 + 30)
 110 /* Crossbar Error Interrupt */
 111 #define FALCON_IRQ_XBAR_ERROR                   (INT_NUM_IM1_IRL0 + 31)
 112
 113 /* ICTRLL 0 Interrupt */
 114 #define FALCON_IRQ_ICTRLL0                      (INT_NUM_IM2_IRL0 + 0)
 115 /* ICTRLL 1 Interrupt */
 116 #define FALCON_IRQ_ICTRLL1                      (INT_NUM_IM2_IRL0 + 1)
 117 /* ICTRLL 2 Interrupt */
 118 #define FALCON_IRQ_ICTRLL2                      (INT_NUM_IM2_IRL0 + 2)
 119 /* ICTRLL 3 Interrupt */
 120 #define FALCON_IRQ_ICTRLL3                      (INT_NUM_IM2_IRL0 + 3)
 121 /* OCTRLL 0 Interrupt */
 122 #define FALCON_IRQ_OCTRLL0                      (INT_NUM_IM2_IRL0 + 4)
 123 /* OCTRLL 1 Interrupt */
 124 #define FALCON_IRQ_OCTRLL1                      (INT_NUM_IM2_IRL0 + 5)
 125 /* OCTRLL 2 Interrupt */
 126 #define FALCON_IRQ_OCTRLL2                      (INT_NUM_IM2_IRL0 + 6)
 127 /* OCTRLL 3 Interrupt */
 128 #define FALCON_IRQ_OCTRLL3                      (INT_NUM_IM2_IRL0 + 7)
 129 /* OCTRLG Interrupt */
 130 #define FALCON_IRQ_OCTRLG                       (INT_NUM_IM2_IRL0 + 9)
 131 /* IQM Interrupt */
 132 #define FALCON_IRQ_IQM                          (INT_NUM_IM2_IRL0 + 10)
 133 /* FSQM Interrupt */
 134 #define FALCON_IRQ_FSQM                         (INT_NUM_IM2_IRL0 + 11)
 135 /* TMU Interrupt */
 136 #define FALCON_IRQ_TMU                          (INT_NUM_IM2_IRL0 + 12)
 137 /* LINK1 Interrupt */
 138 #define FALCON_IRQ_LINK1                        (INT_NUM_IM2_IRL0 + 14)
 139 /* ICTRLC 0 Interrupt */
 140 #define FALCON_IRQ_ICTRLC0                      (INT_NUM_IM2_IRL0 + 16)
 141 /* ICTRLC 1 Interrupt */
 142 #define FALCON_IRQ_ICTRLC1                      (INT_NUM_IM2_IRL0 + 17)
 143 /* OCTRLC Interrupt */
 144 #define FALCON_IRQ_OCTRLC                       (INT_NUM_IM2_IRL0 + 18)
 145 /* CONFIG Break Interrupt */
 146 #define FALCON_IRQ_CONFIG_BREAK                 (INT_NUM_IM2_IRL0 + 19)
 147 /* CONFIG Interrupt */
 148 #define FALCON_IRQ_CONFIG                       (INT_NUM_IM2_IRL0 + 20)
 149 /* Dispatcher Interrupt */
 150 #define FALCON_IRQ_DISP                         (INT_NUM_IM2_IRL0 + 21)
 151 /* TBM Interrupt */
 152 #define FALCON_IRQ_TBM                          (INT_NUM_IM2_IRL0 + 22)
 153 /* GTC Downstream Interrupt */
 154 #define FALCON_IRQ_GTC_DS                       (INT_NUM_IM2_IRL0 + 29)
 155 /* GTC Upstream Interrupt */
 156 #define FALCON_IRQ_GTC_US                       (INT_NUM_IM2_IRL0 + 30)
 157 /* EIM Interrupt */
 158 #define FALCON_IRQ_EIM                          (INT_NUM_IM2_IRL0 + 31)
 159
 160 /* ASC0 Transmit Interrupt */
 161 #define FALCON_IRQ_ASC0_T                       (INT_NUM_IM3_IRL0 + 0)
 162 /* ASC0 Receive Interrupt */
 163 #define FALCON_IRQ_ASC0_R                       (INT_NUM_IM3_IRL0 + 1)
 164 /* ASC0 Error Interrupt */
 165 #define FALCON_IRQ_ASC0_E                       (INT_NUM_IM3_IRL0 + 2)
 166 /* ASC0 Transmit Buffer Interrupt */
 167 #define FALCON_IRQ_ASC0_TB                      (INT_NUM_IM3_IRL0 + 3)
 168 /* ASC0 Autobaud Start Interrupt */
 169 #define FALCON_IRQ_ASC0_ABST                    (INT_NUM_IM3_IRL0 + 4)
 170 /* ASC0 Autobaud Detection Interrupt */
 171 #define FALCON_IRQ_ASC0_ABDET                   (INT_NUM_IM3_IRL0 + 5)
 172 /* ASC1 Modem Status Interrupt */
 173 #define FALCON_IRQ_ASC0_MS                      (INT_NUM_IM3_IRL0 + 6)
 174 /* ASC0 Soft Flow Control Interrupt */
 175 #define FALCON_IRQ_ASC0_SFC                     (INT_NUM_IM3_IRL0 + 7)
 176 /* ASC1 Transmit Interrupt */
 177 #define FALCON_IRQ_ASC1_T                       (INT_NUM_IM3_IRL0 + 8)
 178 /* ASC1 Receive Interrupt */
 179 #define FALCON_IRQ_ASC1_R                       (INT_NUM_IM3_IRL0 + 9)
 180 /* ASC1 Error Interrupt */
 181 #define FALCON_IRQ_ASC1_E                       (INT_NUM_IM3_IRL0 + 10)
 182 /* ASC1 Transmit Buffer Interrupt */
 183 #define FALCON_IRQ_ASC1_TB                      (INT_NUM_IM3_IRL0 + 11)
 184 /* ASC1 Autobaud Start Interrupt */
 185 #define FALCON_IRQ_ASC1_ABST                    (INT_NUM_IM3_IRL0 + 12)
 186 /* ASC1 Autobaud Detection Interrupt */
 187 #define FALCON_IRQ_ASC1_ABDET                   (INT_NUM_IM3_IRL0 + 13)
 188 /* ASC1 Modem Status Interrupt */
 189 #define FALCON_IRQ_ASC1_MS                      (INT_NUM_IM3_IRL0 + 14)
 190 /* ASC1 Soft Flow Control Interrupt */
 191 #define FALCON_IRQ_ASC1_SFC                     (INT_NUM_IM3_IRL0 + 15)
 192 /* GPTC Timer/Counter 1A Interrupt */
 193 #define FALCON_IRQ_GPTC_TC1A                    (INT_NUM_IM3_IRL0 + 16)
 194 /* GPTC Timer/Counter 1B Interrupt */
 195 #define FALCON_IRQ_GPTC_TC1B                    (INT_NUM_IM3_IRL0 + 17)
 196 /* GPTC Timer/Counter 2A Interrupt */
 197 #define FALCON_IRQ_GPTC_TC2A                    (INT_NUM_IM3_IRL0 + 18)
 198 /* GPTC Timer/Counter 2B Interrupt */
 199 #define FALCON_IRQ_GPTC_TC2B                    (INT_NUM_IM3_IRL0 + 19)
 200 /* GPTC Timer/Counter 3A Interrupt */
 201 #define FALCON_IRQ_GPTC_TC3A                    (INT_NUM_IM3_IRL0 + 20)
 202 /* GPTC Timer/Counter 3B Interrupt */
 203 #define FALCON_IRQ_GPTC_TC3B                    (INT_NUM_IM3_IRL0 + 21)
 204 /* DFEV0, Channel 1 Transmit Interrupt */
 205 #define FALCON_IRQ_DFEV0_2TX                    (INT_NUM_IM3_IRL0 + 26)
 206 /* DFEV0, Channel 1 Receive Interrupt */
 207 #define FALCON_IRQ_DFEV0_2RX                    (INT_NUM_IM3_IRL0 + 27)
 208 /* DFEV0, Channel 1 General Purpose Interrupt */
 209 #define FALCON_IRQ_DFEV0_2GP                    (INT_NUM_IM3_IRL0 + 28)
 210 /* DFEV0, Channel 0 Transmit Interrupt */
 211 #define FALCON_IRQ_DFEV0_1TX                    (INT_NUM_IM3_IRL0 + 29)
 212 /* DFEV0, Channel 0 Receive Interrupt */
 213 #define FALCON_IRQ_DFEV0_1RX                    (INT_NUM_IM3_IRL0 + 30)
 214 /* DFEV0, Channel 0 General Purpose Interrupt */
 215 #define FALCON_IRQ_DFEV0_1GP                    (INT_NUM_IM3_IRL0 + 31)
 216
 217 /* ICTRLL 0 Error */
 218 #define FALCON_IRQ_ICTRLL0_ERR                  (INT_NUM_IM4_IRL0 + 0)
 219 /* ICTRLL 1 Error */
 220 #define FALCON_IRQ_ICTRLL1_ERR                  (INT_NUM_IM4_IRL0 + 1)
 221 /* ICTRLL 2 Error */
 222 #define FALCON_IRQ_ICTRLL2_ERR                  (INT_NUM_IM4_IRL0 + 2)
 223 /* ICTRLL 3 Error */
 224 #define FALCON_IRQ_ICTRLL3_ERR                  (INT_NUM_IM4_IRL0 + 3)
 225 /* OCTRLL 0 Error */
 226 #define FALCON_IRQ_OCTRLL0_ERR                  (INT_NUM_IM4_IRL0 + 4)
 227 /* OCTRLL 1 Error */
 228 #define FALCON_IRQ_OCTRLL1_ERR                  (INT_NUM_IM4_IRL0 + 5)
 229 /* OCTRLL 2 Error */
 230 #define FALCON_IRQ_OCTRLL2_ERR                  (INT_NUM_IM4_IRL0 + 6)
 231 /* OCTRLL 3 Error */
 232 #define FALCON_IRQ_OCTRLL3_ERR                  (INT_NUM_IM4_IRL0 + 7)
 233 /* ICTRLG Error */
 234 #define FALCON_IRQ_ICTRLG_ERR                   (INT_NUM_IM4_IRL0 + 8)
 235 /* OCTRLG Error */
 236 #define FALCON_IRQ_OCTRLG_ERR                   (INT_NUM_IM4_IRL0 + 9)
 237 /* IQM Error */
 238 #define FALCON_IRQ_IQM_ERR                      (INT_NUM_IM4_IRL0 + 10)
 239 /* FSQM Error */
 240 #define FALCON_IRQ_FSQM_ERR                     (INT_NUM_IM4_IRL0 + 11)
 241 /* TMU Error */
 242 #define FALCON_IRQ_TMU_ERR                      (INT_NUM_IM4_IRL0 + 12)
 243 /* MPS Status Interrupt #0 (VPE1 to VPE0) */
 244 #define FALCON_IRQ_MPS_IR0                      (INT_NUM_IM4_IRL0 + 14)
 245 /* MPS Status Interrupt #1 (VPE1 to VPE0) */
 246 #define FALCON_IRQ_MPS_IR1                      (INT_NUM_IM4_IRL0 + 15)
 247 /* MPS Status Interrupt #2 (VPE1 to VPE0) */
 248 #define FALCON_IRQ_MPS_IR2                      (INT_NUM_IM4_IRL0 + 16)
 249 /* MPS Status Interrupt #3 (VPE1 to VPE0) */
 250 #define FALCON_IRQ_MPS_IR3                      (INT_NUM_IM4_IRL0 + 17)
 251 /* MPS Status Interrupt #4 (VPE1 to VPE0) */
 252 #define FALCON_IRQ_MPS_IR4                      (INT_NUM_IM4_IRL0 + 18)
 253 /* MPS Status Interrupt #5 (VPE1 to VPE0) */
 254 #define FALCON_IRQ_MPS_IR5                      (INT_NUM_IM4_IRL0 + 19)
 255 /* MPS Status Interrupt #6 (VPE1 to VPE0) */
 256 #define FALCON_IRQ_MPS_IR6                      (INT_NUM_IM4_IRL0 + 20)
 257 /* MPS Status Interrupt #7 (VPE1 to VPE0) */
 258 #define FALCON_IRQ_MPS_IR7                      (INT_NUM_IM4_IRL0 + 21)
 259 /* MPS Status Interrupt #8 (VPE1 to VPE0) */
 260 #define FALCON_IRQ_MPS_IR8                      (INT_NUM_IM4_IRL0 + 22)
 261 /* VPE0 Exception Level Flag Interrupt */
 262 #define FALCON_IRQ_VPE0_EXL                     (INT_NUM_IM4_IRL0 + 29)
 263 /* VPE0 Error Level Flag Interrupt */
 264 #define FALCON_IRQ_VPE0_ERL                     (INT_NUM_IM4_IRL0 + 30)
 265 /* VPE0 Performance Monitoring Counter Interrupt */
 266 #define FALCON_IRQ_VPE0_PMCIR                   (INT_NUM_IM4_IRL0 + 31)
 267
 268 #endif /* _FALCON_IRQ__ */