2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
12 #include <asm/bootinfo.h>
13 #include <asm/irq_cpu.h>
18 #define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
20 #define LQ_ICU_IM0_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
21 #define LQ_ICU_IM0_IER ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
22 #define LQ_ICU_IM0_IOSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
23 #define LQ_ICU_IM0_IRSR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
24 #define LQ_ICU_IM0_IMR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
26 #define LQ_ICU_IM1_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
27 #define LQ_ICU_IM2_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
28 #define LQ_ICU_IM3_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
29 #define LQ_ICU_IM4_ISR ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
31 #define LQ_ICU_OFFSET (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
34 lq_disable_irq(unsigned int irq_nr
)
36 u32
*ier
= LQ_ICU_IM0_IER
;
37 irq_nr
-= INT_NUM_IRQ0
;
38 ier
+= LQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
39 irq_nr
%= INT_NUM_IM_OFFSET
;
40 lq_w32(lq_r32(ier
) & ~(1 << irq_nr
), ier
);
42 EXPORT_SYMBOL(lq_disable_irq
);
45 lq_mask_and_ack_irq(unsigned int irq_nr
)
47 u32
*ier
= LQ_ICU_IM0_IER
;
48 u32
*isr
= LQ_ICU_IM0_ISR
;
49 irq_nr
-= INT_NUM_IRQ0
;
50 ier
+= LQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
51 isr
+= LQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
52 irq_nr
%= INT_NUM_IM_OFFSET
;
53 lq_w32(lq_r32(ier
) & ~(1 << irq_nr
), ier
);
54 lq_w32((1 << irq_nr
), isr
);
56 EXPORT_SYMBOL(lq_mask_and_ack_irq
);
59 lq_ack_irq(unsigned int irq_nr
)
61 u32
*isr
= LQ_ICU_IM0_ISR
;
62 irq_nr
-= INT_NUM_IRQ0
;
63 isr
+= LQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
64 irq_nr
%= INT_NUM_IM_OFFSET
;
65 lq_w32((1 << irq_nr
), isr
);
69 lq_enable_irq(unsigned int irq_nr
)
71 u32
*ier
= LQ_ICU_IM0_IER
;
72 irq_nr
-= INT_NUM_IRQ0
;
73 ier
+= LQ_ICU_OFFSET
* (irq_nr
/ INT_NUM_IM_OFFSET
);
74 irq_nr
%= INT_NUM_IM_OFFSET
;
75 lq_w32(lq_r32(ier
) | (1 << irq_nr
), ier
);
77 EXPORT_SYMBOL(lq_enable_irq
);
80 lq_startup_irq(unsigned int irq
)
87 lq_end_irq(unsigned int irq
)
89 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
93 static struct irq_chip
96 .startup
= lq_startup_irq
,
97 .enable
= lq_enable_irq
,
98 .disable
= lq_disable_irq
,
99 .unmask
= lq_enable_irq
,
101 .mask
= lq_disable_irq
,
102 .mask_ack
= lq_mask_and_ack_irq
,
107 lq_hw_irqdispatch(int module
)
111 irq
= lq_r32(LQ_ICU_IM0_IOSR
+ (module
* LQ_ICU_OFFSET
));
115 /* silicon bug causes only the msb set to 1 to be valid. all
116 other bits might be bogus */
118 do_IRQ((int)irq
+ INT_NUM_IM0_IRL0
+ (INT_NUM_IM_OFFSET
* module
));
121 #define DEFINE_HWx_IRQDISPATCH(x) \
122 static void lq_hw ## x ## _irqdispatch(void)\
124 lq_hw_irqdispatch(x); \
126 static void lq_hw5_irqdispatch(void)
128 do_IRQ(MIPS_CPU_TIMER_IRQ
);
130 DEFINE_HWx_IRQDISPATCH(0)
131 DEFINE_HWx_IRQDISPATCH(1)
132 DEFINE_HWx_IRQDISPATCH(2)
133 DEFINE_HWx_IRQDISPATCH(3)
134 DEFINE_HWx_IRQDISPATCH(4)
135 /*DEFINE_HWx_IRQDISPATCH(5)*/
138 plat_irq_dispatch(void)
140 unsigned int pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
143 if (pending
& CAUSEF_IP7
)
145 do_IRQ(MIPS_CPU_TIMER_IRQ
);
148 for (i
= 0; i
< 5; i
++)
150 if (pending
& (CAUSEF_IP2
<< i
))
152 lq_hw_irqdispatch(i
);
157 printk(KERN_ALERT
"Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
163 static struct irqaction
165 .handler
= no_action
,
166 .flags
= IRQF_DISABLED
,
175 for (i
= 0; i
< 5; i
++)
176 lq_w32(0, LQ_ICU_IM0_IER
+ (i
* LQ_ICU_OFFSET
));
180 for (i
= 2; i
<= 6; i
++)
181 setup_irq(i
, &cascade
);
184 printk(KERN_INFO
"Setting up vectored interrupts\n");
185 set_vi_handler(2, lq_hw0_irqdispatch
);
186 set_vi_handler(3, lq_hw1_irqdispatch
);
187 set_vi_handler(4, lq_hw2_irqdispatch
);
188 set_vi_handler(5, lq_hw3_irqdispatch
);
189 set_vi_handler(6, lq_hw4_irqdispatch
);
190 set_vi_handler(7, lq_hw5_irqdispatch
);
193 for (i
= INT_NUM_IRQ0
; i
<= (INT_NUM_IRQ0
+ (5 * INT_NUM_IM_OFFSET
)); i
++)
194 set_irq_chip_and_handler(i
, &lq_irq_type
,
197 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
198 set_c0_status(IE_IRQ0
| IE_IRQ1
| IE_IRQ2
|
199 IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
201 set_c0_status(IE_SW0
| IE_SW1
| IE_IRQ0
| IE_IRQ1
|
202 IE_IRQ2
| IE_IRQ3
| IE_IRQ4
| IE_IRQ5
);
207 arch_fixup_c0_irqs(void)
209 /* FIXME: check for CPUID and only do fix for specific chips/versions */
210 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
211 cp0_perfcount_irq
= CP0_LEGACY_PERFCNT_IRQ
;