2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
10 #include <linux/export.h>
11 #include <linux/init.h>
12 #include <linux/clk.h>
16 #include <asm/div64.h>
18 #include <lantiq_soc.h>
22 static unsigned int ltq_ram_clocks
[] = {
23 CLOCK_167M
, CLOCK_133M
, CLOCK_111M
, CLOCK_83M
};
24 #define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
26 #define BASIC_FREQUENCY_1 35328000
27 #define BASIC_FREQUENCY_2 36000000
28 #define BASIS_REQUENCY_USB 12000000
30 #define GET_BITS(x, msb, lsb) \
31 (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
33 /* legacy xway clock */
34 #define LTQ_CGU_PLL0_CFG 0x0004
35 #define LTQ_CGU_PLL1_CFG 0x0008
36 #define LTQ_CGU_PLL2_CFG 0x000C
37 #define LTQ_CGU_SYS 0x0010
38 #define LTQ_CGU_UPDATE 0x0014
39 #define LTQ_CGU_IF_CLK 0x0018
40 #define LTQ_CGU_OSC_CON 0x001C
41 #define LTQ_CGU_SMD 0x0020
42 #define LTQ_CGU_CT1SR 0x0028
43 #define LTQ_CGU_CT2SR 0x002C
44 #define LTQ_CGU_PCMCR 0x0030
45 #define LTQ_CGU_PCI_CR 0x0034
46 #define LTQ_CGU_PD_PC 0x0038
47 #define LTQ_CGU_FMR 0x003C
49 #define CGU_PLL0_PHASE_DIVIDER_ENABLE \
50 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
51 #define CGU_PLL0_BYPASS \
52 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
53 #define CGU_PLL0_CFG_DSMSEL \
54 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
55 #define CGU_PLL0_CFG_FRAC_EN \
56 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
57 #define CGU_PLL1_SRC \
58 (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
59 #define CGU_PLL2_PHASE_DIVIDER_ENABLE \
60 (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
61 #define CGU_SYS_FPI_SEL (1 << 6)
62 #define CGU_SYS_DDR_SEL 0x3
63 #define CGU_PLL0_SRC (1 << 29)
65 #define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
66 #define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
67 #define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
68 #define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
69 #define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
72 #define LTQ_CGU_SYS_VR9 0x0c
73 #define LTQ_CGU_IF_CLK_VR9 0x24
76 static unsigned int ltq_get_pll0_fdiv(void);
78 static inline unsigned int get_input_clock(int pll
)
82 if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG
) & CGU_PLL0_SRC
)
83 return BASIS_REQUENCY_USB
;
84 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE
)
85 return BASIC_FREQUENCY_1
;
87 return BASIC_FREQUENCY_2
;
90 return BASIS_REQUENCY_USB
;
91 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE
)
92 return BASIC_FREQUENCY_1
;
94 return BASIC_FREQUENCY_2
;
96 switch (CGU_PLL2_SRC
) {
98 return ltq_get_pll0_fdiv();
100 return CGU_PLL2_PHASE_DIVIDER_ENABLE
?
104 return BASIS_REQUENCY_USB
;
111 static inline unsigned int cal_dsm(int pll
, unsigned int num
, unsigned int den
)
113 u64 res
, clock
= get_input_clock(pll
);
120 static inline unsigned int mash_dsm(int pll
, unsigned int M
, unsigned int N
,
123 unsigned int num
= ((N
+ 1) << 10) + K
;
124 unsigned int den
= (M
+ 1) << 10;
126 return cal_dsm(pll
, num
, den
);
129 static inline unsigned int ssff_dsm_1(int pll
, unsigned int M
, unsigned int N
,
132 unsigned int num
= ((N
+ 1) << 11) + K
+ 512;
133 unsigned int den
= (M
+ 1) << 11;
135 return cal_dsm(pll
, num
, den
);
138 static inline unsigned int ssff_dsm_2(int pll
, unsigned int M
, unsigned int N
,
141 unsigned int num
= K
>= 512 ?
142 ((N
+ 1) << 12) + K
- 512 : ((N
+ 1) << 12) + K
+ 3584;
143 unsigned int den
= (M
+ 1) << 12;
145 return cal_dsm(pll
, num
, den
);
148 static inline unsigned int dsm(int pll
, unsigned int M
, unsigned int N
,
149 unsigned int K
, unsigned int dsmsel
, unsigned int phase_div_en
)
152 return mash_dsm(pll
, M
, N
, K
);
153 else if (!phase_div_en
)
154 return mash_dsm(pll
, M
, N
, K
);
156 return ssff_dsm_2(pll
, M
, N
, K
);
159 static inline unsigned int ltq_get_pll0_fosc(void)
162 return get_input_clock(0);
164 return !CGU_PLL0_CFG_FRAC_EN
165 ? dsm(0, CGU_PLL0_CFG_PLLM
, CGU_PLL0_CFG_PLLN
, 0,
167 CGU_PLL0_PHASE_DIVIDER_ENABLE
)
168 : dsm(0, CGU_PLL0_CFG_PLLM
, CGU_PLL0_CFG_PLLN
,
169 CGU_PLL0_CFG_PLLK
, CGU_PLL0_CFG_DSMSEL
,
170 CGU_PLL0_PHASE_DIVIDER_ENABLE
);
173 static unsigned int ltq_get_pll0_fdiv(void)
175 unsigned int div
= CGU_PLL2_CFG_INPUT_DIV
+ 1;
177 return (ltq_get_pll0_fosc() + (div
>> 1)) / div
;
180 unsigned long ltq_danube_io_region_clock(void)
182 unsigned int ret
= ltq_get_pll0_fosc();
184 switch (ltq_cgu_r32(LTQ_CGU_SYS
) & 0x3) {
187 return (ret
+ 1) / 2;
189 return (ret
* 2 + 2) / 5;
191 return (ret
+ 1) / 3;
193 return (ret
+ 2) / 4;
197 unsigned long ltq_danube_fpi_bus_clock(int fpi
)
199 unsigned long ret
= ltq_danube_io_region_clock();
201 if ((fpi
== 2) && (ltq_cgu_r32(LTQ_CGU_SYS
) & CGU_SYS_FPI_SEL
))
206 unsigned long ltq_danube_fpi_hz(void)
208 unsigned long ddr_clock
= DDR_HZ
;
210 if (ltq_cgu_r32(LTQ_CGU_SYS
) & 0x40)
211 return ddr_clock
>> 1;
215 unsigned long ltq_danube_cpu_hz(void)
217 switch (ltq_cgu_r32(LTQ_CGU_SYS
) & 0xc) {
229 unsigned long ltq_ar9_sys_hz(void)
231 if (((ltq_cgu_r32(LTQ_CGU_SYS
) >> 3) & 0x3) == 0x2)
236 unsigned long ltq_ar9_fpi_hz(void)
238 unsigned long sys
= ltq_ar9_sys_hz();
240 if (ltq_cgu_r32(LTQ_CGU_SYS
) & BIT(0))
245 unsigned long ltq_ar9_cpu_hz(void)
247 if (ltq_cgu_r32(LTQ_CGU_SYS
) & BIT(2))
248 return ltq_ar9_fpi_hz();
250 return ltq_ar9_sys_hz();
253 unsigned long ltq_vr9_cpu_hz(void)
255 unsigned int cpu_sel
;
258 cpu_sel
= (ltq_cgu_r32(LTQ_CGU_SYS_VR9
) >> 4) & 0xf;
275 clk
= CLOCK_196_608M
;
293 unsigned long ltq_vr9_fpi_hz(void)
295 unsigned int ocp_sel
, cpu_clk
;
298 cpu_clk
= ltq_vr9_cpu_hz();
299 ocp_sel
= ltq_cgu_r32(LTQ_CGU_SYS_VR9
) & 0x3;
312 clk
= (cpu_clk
* 2) / 5;
326 unsigned long ltq_vr9_fpi_bus_clock(int fpi
)
328 return ltq_vr9_fpi_hz();