1 /******************************************************************************
3 ** FILE NAME : dwc_otg_ifx.c
4 ** PROJECT : Twinpass/Danube
5 ** MODULES : DWC OTG USB
7 ** DATE : 12 Auguest 2007
8 ** AUTHOR : Sung Winder
9 ** DESCRIPTION : Platform specific initialization.
10 ** COPYRIGHT : Copyright (c) 2007
11 ** Infineon Technologies AG
12 ** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park,
13 ** Hsin-chu City, 300 Taiwan.
15 ** This program is free software; you can redistribute it and/or modify
16 ** it under the terms of the GNU General Public License as published by
17 ** the Free Software Foundation; either version 2 of the License, or
18 ** (at your option) any later version.
21 ** $Date $Author $Comment
22 ** 12 Auguest 2007 Sung Winder Initiate Version
23 *******************************************************************************/
24 #include "dwc_otg_ifx.h"
26 #include <linux/platform_device.h>
27 #include <linux/kernel.h>
28 #include <linux/ioport.h>
29 #include <linux/gpio.h>
32 //#include <asm/mach-ifxmips/ifxmips.h>
33 #include <lantiq_soc.h>
35 #define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00)
37 #define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010))
38 #define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040))
39 #define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014))
40 #define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044))
41 #define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018))
42 #define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048))
43 #define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C))
44 #define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C))
45 #define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020))
46 #define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050))
47 #define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024))
48 #define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054))
49 #define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028))
50 #define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058))
51 #define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C))
52 #define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C))
53 #define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030))
54 #define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060))
57 #define writel ltq_w32
59 void dwc_otg_power_on (void)
62 writel(readl(DANUBE_PMU_PWDCR
) | 0x41, DANUBE_PMU_PWDCR
);
65 writel(readl(DANUBE_CGU_IFCCR
) & ~0x20, DANUBE_CGU_IFCCR
);
67 writel(readl(DANUBE_CGU_IFCCR
) | 0x30, DANUBE_CGU_IFCCR
);
69 writel(readl(DANUBE_PMU_PWDCR
) & ~0x1, DANUBE_PMU_PWDCR
);
70 writel(readl(DANUBE_PMU_PWDCR
) & ~0x40, DANUBE_PMU_PWDCR
);
71 writel(readl(DANUBE_PMU_PWDCR
) & ~0x8000, DANUBE_PMU_PWDCR
);
73 #if 1//defined (DWC_HOST_ONLY)
74 // make the hardware be a host controller (default)
75 //clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
76 writel(readl(DANUBE_RCU_UBSCFG
) & ~(1<<DANUBE_USBCFG_HDSEL_BIT
), DANUBE_RCU_UBSCFG
);
78 //#elif defined (DWC_DEVICE_ONLY)
79 /* set the controller to the device mode */
80 // set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
82 #error "For Danube/Twinpass, it should be HOST or Device Only."
85 // set the HC's byte-order to big-endian
86 //set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
87 writel(readl(DANUBE_RCU_UBSCFG
) | (1<<DANUBE_USBCFG_HOST_END_BIT
), DANUBE_RCU_UBSCFG
);
88 //clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG);
89 writel(readl(DANUBE_RCU_UBSCFG
) & ~(1<<DANUBE_USBCFG_SLV_END_BIT
), DANUBE_RCU_UBSCFG
);
90 //writel(0x400, DANUBE_RCU_UBSCFG);
92 // PHY configurations.
93 writel (0x14014, (volatile unsigned long *)0xbe10103c);
96 int ifx_usb_hc_init(unsigned long base_addr
, int irq
)
101 void ifx_usb_hc_remove(void)