target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2007
   4   Infineon Technologies AG
   5   St. Martin Strasse 53; 81669 Munich, Germany
   6
   7   Any use of this Software is subject to the conclusion of a respective
   8   License Agreement. Without such a License Agreement no rights to the
   9   Software are granted.
  10
  11  ******************************************************************************/
  12
  13 #ifndef __EBU_REG_H
  14 #define __EBU_REG_H
  15
  16 #define ebu_r32(reg) ltq_r32(&ebu->reg)
  17 #define ebu_w32(val, reg) ltq_w32(val, &ebu->reg)
  18 #define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg)
  19
  20 /** EBU register structure */
  21 struct svip_reg_ebu {
  22         volatile unsigned long  clc;  /*  0x0000 */
  23         volatile unsigned long  reserved0;  /*  0x04 */
  24         volatile unsigned long  id;  /*  0x0008 */
  25         volatile unsigned long  reserved1;  /*  0x0c */
  26         volatile unsigned long  con;  /*  0x0010 */
  27         volatile unsigned long  reserved2[3];  /*  0x14 */
  28         volatile unsigned long  addr_sel_0;  /*  0x0020 */
  29         volatile unsigned long  addr_sel_1;  /*  0x0024 */
  30         volatile unsigned long  addr_sel_2;  /*  0x0028 */
  31         volatile unsigned long  addr_sel_3;  /*  0x002c */
  32         volatile unsigned long  reserved3[12];  /*  0x30 */
  33         volatile unsigned long  con_0;  /*  0x0060 */
  34         volatile unsigned long  con_1;  /*  0x0064 */
  35         volatile unsigned long  con_2;  /*  0x0068 */
  36         volatile unsigned long  con_3;  /*  0x006c */
  37         volatile unsigned long  reserved4[4];  /*  0x70 */
  38         volatile unsigned long  emu_addr;  /*  0x0080 */
  39         volatile unsigned long  emu_bc;  /*  0x0084 */
  40         volatile unsigned long  emu_con;  /*  0x0088 */
  41         volatile unsigned long  reserved5;  /*  0x8c */
  42         volatile unsigned long  pcc_con;  /*  0x0090 */
  43         volatile unsigned long  pcc_stat;  /*  0x0094 */
  44         volatile unsigned long  reserved6[2];  /*  0x98 */
  45         volatile unsigned long  pcc_istat;  /*  0x00A0 */
  46         volatile unsigned long  pcc_ien;  /*  0x00A4 */
  47         volatile unsigned long  pcc_int_out;  /*  0x00A8 */
  48         volatile unsigned long  pcc_irs;  /*  0x00AC */
  49         volatile unsigned long  nand_con;  /*  0x00B0 */
  50         volatile unsigned long  nand_wait;  /*  0x00B4 */
  51         volatile unsigned long  nand_ecc0;  /*  0x00B8 */
  52         volatile unsigned long  nand_ecc_ac;  /*  0x00BC */
  53 };
  54
  55 /*******************************************************************************
  56  * EBU
  57  ******************************************************************************/
  58 #define LTQ_EBU_CLC   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000))
  59 #define LTQ_EBU_ID   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008))
  60 #define LTQ_EBU_CON   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010))
  61 #define LTQ_EBU_ADDR_SEL_0   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020))
  62 #define LTQ_EBU_ADDR_SEL_1   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024))
  63 #define LTQ_EBU_ADDR_SEL_2   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028))
  64 #define LTQ_EBU_ADDR_SEL_3   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c))
  65 #define LTQ_EBU_CON_0   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060))
  66 #define LTQ_EBU_CON_1   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064))
  67 #define LTQ_EBU_CON_2   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068))
  68 #define LTQ_EBU_CON_3   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c))
  69 #define LTQ_EBU_EMU_BC   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084))
  70 #define LTQ_EBU_PCC_CON   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090))
  71 #define LTQ_EBU_PCC_STAT   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094))
  72 #define LTQ_EBU_PCC_ISTAT   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0))
  73 #define LTQ_EBU_PCC_IEN   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4))
  74 #define LTQ_EBU_PCC_INT_OUT   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8))
  75 #define LTQ_EBU_PCC_IRS   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC))
  76 #define LTQ_EBU_NAND_CON   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0))
  77 #define LTQ_EBU_NAND_WAIT   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4))
  78 #define LTQ_EBU_NAND_ECC0   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8))
  79 #define LTQ_EBU_NAND_ECC_AC   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC))
  80 #define LTQ_EBU_EMU_ADDR   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080))
  81 #define LTQ_EBU_EMU_CON   ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088))
  82
  83 /*******************************************************************************
  84  * EBU Clock Control Register
  85  ******************************************************************************/
  86
  87 /* EBU Disable Status Bit (1) */
  88 #define LTQ_EBU_CLC_DISS   (0x1 << 1)
  89 #define LTQ_EBU_CLC_DISS_GET(val)   ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1)
  90 /* Used for Enable/disable Control of the EBU (0) */
  91 #define LTQ_EBU_CLC_DISR   (0x1)
  92 #define LTQ_EBU_CLC_DISR_VAL(val)   (((val) & 0x1) << 0)
  93 #define LTQ_EBU_CLC_DISR_GET(val)   ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1)
  94 #define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0))
  95
  96 /*******************************************************************************
  97  * EBU Identification Register (Internal)
  98  ******************************************************************************/
  99
 100 /* Module Number (31:8) */
 101 #define LTQ_EBU_ID_MODNUM   (0xffffff << 8)
 102 #define LTQ_EBU_ID_MODNUM_GET(val)   ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff)
 103 /* Revision Number (7:0) */
 104 #define LTQ_EBU_ID_REVNUM   (0xff)
 105 #define LTQ_EBU_ID_REVNUM_GET(val)   ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff)
 106
 107 /*******************************************************************************
 108  * External Bus Unit Control Register
 109  ******************************************************************************/
 110
 111 /* Driver Turn-Around Control, Chip Select Triggered (22:20) */
 112 #define LTQ_EBU_CON_DTACS   (0x7 << 20)
 113 #define LTQ_EBU_CON_DTACS_VAL(val)   (((val) & 0x7) << 20)
 114 #define LTQ_EBU_CON_DTACS_GET(val)   ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7)
 115 #define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20))
 116 /* Driver Turn-Around Control, Read-write Triggered (18:16) */
 117 #define LTQ_EBU_CON_DTARW   (0x7 << 16)
 118 #define LTQ_EBU_CON_DTARW_VAL(val)   (((val) & 0x7) << 16)
 119 #define LTQ_EBU_CON_DTARW_GET(val)   ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7)
 120 #define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16))
 121 /* Time-Out Control (15:8) */
 122 #define LTQ_EBU_CON_TOUTC   (0xff << 8)
 123 #define LTQ_EBU_CON_TOUTC_VAL(val)   (((val) & 0xff) << 8)
 124 #define LTQ_EBU_CON_TOUTC_GET(val)   ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff)
 125 #define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8))
 126 /* Arbitration Mode (7:6) */
 127 #define LTQ_EBU_CON_ARBMODE   (0x3 << 6)
 128 #define LTQ_EBU_CON_ARBMODE_VAL(val)   (((val) & 0x3) << 6)
 129 #define LTQ_EBU_CON_ARBMODE_GET(val)   ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3)
 130 #define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6))
 131 /* Arbitration Synchronization (5) */
 132 #define LTQ_EBU_CON_ARBSYNC   (0x1 << 5)
 133 #define LTQ_EBU_CON_ARBSYNC_VAL(val)   (((val) & 0x1) << 5)
 134 #define LTQ_EBU_CON_ARBSYNC_GET(val)   ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1)
 135 #define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5))
 136
 137 /*******************************************************************************
 138  * Address Select Registers
 139  ******************************************************************************/
 140
 141 /* Memory Region Base Address (31:12) */
 142 #define LTQ_EBU_ADDR_SEL_0_BASE   (0xfffff << 12)
 143 #define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val)   (((val) & 0xfffff) << 12)
 144 #define LTQ_EBU_ADDR_SEL_0_BASE_GET(val)   ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff)
 145 #define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12))
 146 /* Memory Region Address Mask (7:4) */
 147 #define LTQ_EBU_ADDR_SEL_0_MASK   (0xf << 4)
 148 #define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val)   (((val) & 0xf) << 4)
 149 #define LTQ_EBU_ADDR_SEL_0_MASK_GET(val)   ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf)
 150 #define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4))
 151 /* Memory Region Mirror Enable Control (1) */
 152 #define LTQ_EBU_ADDR_SEL_0_MRME   (0x1 << 1)
 153 #define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val)   (((val) & 0x1) << 1)
 154 #define LTQ_EBU_ADDR_SEL_0_MRME_GET(val)   ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1)
 155 #define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1))
 156 /* Memory Region Enable Control (0) */
 157 #define LTQ_EBU_ADDR_SEL_0_REGEN   (0x1)
 158 #define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val)   (((val) & 0x1) << 0)
 159 #define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val)   ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1)
 160 #define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0))
 161
 162 /*******************************************************************************
 163  * Bus Configuration Registers
 164  ******************************************************************************/
 165
 166 /* Memory Region Write Protection (31) */
 167 #define LTQ_EBU_CON_0_WRDIS   (0x1 << 31)
 168 #define LTQ_EBU_CON_0_WRDIS_VAL(val)   (((val) & 0x1) << 31)
 169 #define LTQ_EBU_CON_0_WRDIS_GET(val)   ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1)
 170 #define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31))
 171 /* Address Swapping (30) */
 172 #define LTQ_EBU_CON_0_ADSWP   (0x1 << 30)
 173 #define LTQ_EBU_CON_0_ADSWP_VAL(val)   (((val) & 0x1) << 30)
 174 #define LTQ_EBU_CON_0_ADSWP_GET(val)   ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1)
 175 #define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30))
 176 /* Address Generation Control (26:24) */
 177 #define LTQ_EBU_CON_0_AGEN   (0x7 << 24)
 178 #define LTQ_EBU_CON_0_AGEN_VAL(val)   (((val) & 0x7) << 24)
 179 #define LTQ_EBU_CON_0_AGEN_GET(val)   ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7)
 180 #define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24))
 181 /* Extended Address Setup Control (22) */
 182 #define LTQ_EBU_CON_0_SETUP   (0x1 << 22)
 183 #define LTQ_EBU_CON_0_SETUP_VAL(val)   (((val) & 0x1) << 22)
 184 #define LTQ_EBU_CON_0_SETUP_GET(val)   ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1)
 185 #define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22))
 186 /* Variable Wait-State Insertion Control (21:20) */
 187 #define LTQ_EBU_CON_0_WAIT   (0x3 << 20)
 188 #define LTQ_EBU_CON_0_WAIT_VAL(val)   (((val) & 0x3) << 20)
 189 #define LTQ_EBU_CON_0_WAIT_GET(val)   ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3)
 190 #define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20))
 191 /* Active WAIT Level Control (19) */
 192 #define LTQ_EBU_CON_0_WINV   (0x1 << 19)
 193 #define LTQ_EBU_CON_0_WINV_VAL(val)   (((val) & 0x1) << 19)
 194 #define LTQ_EBU_CON_0_WINV_GET(val)   ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1)
 195 #define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19))
 196 /* External Device Data Width Control (17:16) */
 197 #define LTQ_EBU_CON_0_PW   (0x3 << 16)
 198 #define LTQ_EBU_CON_0_PW_VAL(val)   (((val) & 0x3) << 16)
 199 #define LTQ_EBU_CON_0_PW_GET(val)   ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3)
 200 #define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16))
 201 /* Address Latch Enable ALE Duration Control (15:14) */
 202 #define LTQ_EBU_CON_0_ALEC   (0x3 << 14)
 203 #define LTQ_EBU_CON_0_ALEC_VAL(val)   (((val) & 0x3) << 14)
 204 #define LTQ_EBU_CON_0_ALEC_GET(val)   ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3)
 205 #define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14))
 206 /* Byte Control Signal Timing Mode Control (13:12) */
 207 #define LTQ_EBU_CON_0_BCGEN   (0x3 << 12)
 208 #define LTQ_EBU_CON_0_BCGEN_VAL(val)   (((val) & 0x3) << 12)
 209 #define LTQ_EBU_CON_0_BCGEN_GET(val)   ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3)
 210 #define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12))
 211 /* Write Access Wait-State Control (10:8) */
 212 #define LTQ_EBU_CON_0_WAITWRC   (0x7 << 8)
 213 #define LTQ_EBU_CON_0_WAITWRC_VAL(val)   (((val) & 0x7) << 8)
 214 #define LTQ_EBU_CON_0_WAITWRC_GET(val)   ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7)
 215 #define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8))
 216 /* Read Access Wait-State Control (7:6) */
 217 #define LTQ_EBU_CON_0_WAITRDC   (0x3 << 6)
 218 #define LTQ_EBU_CON_0_WAITRDC_VAL(val)   (((val) & 0x3) << 6)
 219 #define LTQ_EBU_CON_0_WAITRDC_GET(val)   ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3)
 220 #define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6))
 221 /* Hold/Pause Cycle Control (5:4) */
 222 #define LTQ_EBU_CON_0_HOLDC   (0x3 << 4)
 223 #define LTQ_EBU_CON_0_HOLDC_VAL(val)   (((val) & 0x3) << 4)
 224 #define LTQ_EBU_CON_0_HOLDC_GET(val)   ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3)
 225 #define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4))
 226 /* Recovery Cycle Control (3:2) */
 227 #define LTQ_EBU_CON_0_RECOVC   (0x3 << 2)
 228 #define LTQ_EBU_CON_0_RECOVC_VAL(val)   (((val) & 0x3) << 2)
 229 #define LTQ_EBU_CON_0_RECOVC_GET(val)   ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3)
 230 #define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2))
 231 /* Wait Cycle Multiplier Control (1:0) */
 232 #define LTQ_EBU_CON_0_CMULT   (0x3)
 233 #define LTQ_EBU_CON_0_CMULT_VAL(val)   (((val) & 0x3) << 0)
 234 #define LTQ_EBU_CON_0_CMULT_GET(val)   ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3)
 235 #define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0))
 236
 237 /*******************************************************************************
 238  * External Bus Unit Emulator Bus Configuration Register
 239  ******************************************************************************/
 240
 241 /* Write Protection (31) */
 242 #define LTQ_EBU_EMU_BC_WRITE   (0x1 << 31)
 243 #define LTQ_EBU_EMU_BC_WRITE_VAL(val)   (((val) & 0x1) << 31)
 244 #define LTQ_EBU_EMU_BC_WRITE_GET(val)   ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1)
 245 #define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31))
 246 /* Address Generation Control (26:24) */
 247 #define LTQ_EBU_EMU_BC_AGEN   (0x7 << 24)
 248 #define LTQ_EBU_EMU_BC_AGEN_VAL(val)   (((val) & 0x7) << 24)
 249 #define LTQ_EBU_EMU_BC_AGEN_GET(val)   ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7)
 250 #define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24))
 251 /* Extended Address Setup Control (22) */
 252 #define LTQ_EBU_EMU_BC_SETUP   (0x1 << 22)
 253 #define LTQ_EBU_EMU_BC_SETUP_VAL(val)   (((val) & 0x1) << 22)
 254 #define LTQ_EBU_EMU_BC_SETUP_GET(val)   ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1)
 255 #define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22))
 256 /* Variable Waitstate Insertion Control (21:20) */
 257 #define LTQ_EBU_EMU_BC_WAIT   (0x3 << 20)
 258 #define LTQ_EBU_EMU_BC_WAIT_VAL(val)   (((val) & 0x3) << 20)
 259 #define LTQ_EBU_EMU_BC_WAIT_GET(val)   ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3)
 260 #define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20))
 261 /* Active WAIT Level Control (19) */
 262 #define LTQ_EBU_EMU_BC_WINV   (0x1 << 19)
 263 #define LTQ_EBU_EMU_BC_WINV_VAL(val)   (((val) & 0x1) << 19)
 264 #define LTQ_EBU_EMU_BC_WINV_GET(val)   ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1)
 265 #define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19))
 266 /* External Device Data Width Control (17:16) */
 267 #define LTQ_EBU_EMU_BC_PORTW   (0x3 << 16)
 268 #define LTQ_EBU_EMU_BC_PORTW_VAL(val)   (((val) & 0x3) << 16)
 269 #define LTQ_EBU_EMU_BC_PORTW_GET(val)   ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3)
 270 #define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16))
 271 /* Address Latch Enable Function (15:14) */
 272 #define LTQ_EBU_EMU_BC_ALEC   (0x3 << 14)
 273 #define LTQ_EBU_EMU_BC_ALEC_VAL(val)   (((val) & 0x3) << 14)
 274 #define LTQ_EBU_EMU_BC_ALEC_GET(val)   ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3)
 275 #define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14))
 276 /* Byte Control Signal Timing Mode (13:12) */
 277 #define LTQ_EBU_EMU_BC_BCGEN   (0x3 << 12)
 278 #define LTQ_EBU_EMU_BC_BCGEN_VAL(val)   (((val) & 0x3) << 12)
 279 #define LTQ_EBU_EMU_BC_BCGEN_GET(val)   ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3)
 280 #define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12))
 281 /* Write Access Waitstate Control (10:8) */
 282 #define LTQ_EBU_EMU_BC_WAITWRC   (0x7 << 8)
 283 #define LTQ_EBU_EMU_BC_WAITWRC_VAL(val)   (((val) & 0x7) << 8)
 284 #define LTQ_EBU_EMU_BC_WAITWRC_GET(val)   ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7)
 285 #define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8))
 286 /* Read Access Waitstate Control (7:6) */
 287 #define LTQ_EBU_EMU_BC_WAITRDC   (0x3 << 6)
 288 #define LTQ_EBU_EMU_BC_WAITRDC_VAL(val)   (((val) & 0x3) << 6)
 289 #define LTQ_EBU_EMU_BC_WAITRDC_GET(val)   ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3)
 290 #define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6))
 291 /* Hold/Pause Cycle Control (5:4) */
 292 #define LTQ_EBU_EMU_BC_HOLDC   (0x3 << 4)
 293 #define LTQ_EBU_EMU_BC_HOLDC_VAL(val)   (((val) & 0x3) << 4)
 294 #define LTQ_EBU_EMU_BC_HOLDC_GET(val)   ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3)
 295 #define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4))
 296 /* Recovery Cycles Control (3:2) */
 297 #define LTQ_EBU_EMU_BC_RECOVC   (0x3 << 2)
 298 #define LTQ_EBU_EMU_BC_RECOVC_VAL(val)   (((val) & 0x3) << 2)
 299 #define LTQ_EBU_EMU_BC_RECOVC_GET(val)   ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3)
 300 #define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2))
 301 /* Cycle Multiplier Control (1:0) */
 302 #define LTQ_EBU_EMU_BC_CMULT   (0x3)
 303 #define LTQ_EBU_EMU_BC_CMULT_VAL(val)   (((val) & 0x3) << 0)
 304 #define LTQ_EBU_EMU_BC_CMULT_GET(val)   ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3)
 305 #define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0))
 306
 307 /*******************************************************************************
 308  * PC-Card Control Register
 309  ******************************************************************************/
 310
 311 /* External Interrupt Input IREQ (3:1) */
 312 #define LTQ_EBU_PCC_CON_IREQ   (0x7 << 1)
 313 #define LTQ_EBU_PCC_CON_IREQ_VAL(val)   (((val) & 0x7) << 1)
 314 #define LTQ_EBU_PCC_CON_IREQ_GET(val)   ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7)
 315 #define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1))
 316 /* PC Card ON (0) */
 317 #define LTQ_EBU_PCC_CON_ON   (0x1)
 318 #define LTQ_EBU_PCC_CON_ON_VAL(val)   (((val) & 0x1) << 0)
 319 #define LTQ_EBU_PCC_CON_ON_GET(val)   ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1)
 320 #define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0))
 321
 322 /*******************************************************************************
 323  * PCC Status Register
 324  ******************************************************************************/
 325
 326 /* Interrupt Request (6) */
 327 #define LTQ_EBU_PCC_STAT_IRQ   (0x1 << 6)
 328 #define LTQ_EBU_PCC_STAT_IRQ_GET(val)   ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1)
 329 /* PC-Card Overcurrent (5) */
 330 #define LTQ_EBU_PCC_STAT_OC   (0x1 << 5)
 331 #define LTQ_EBU_PCC_STAT_OC_GET(val)   ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1)
 332 /* PC-Card Socket Power On (4) */
 333 #define LTQ_EBU_PCC_STAT_SPON   (0x1 << 4)
 334 #define LTQ_EBU_PCC_STAT_SPON_GET(val)   ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1)
 335 /* Card Detect Status (1:0) */
 336 #define LTQ_EBU_PCC_STAT_CD   (0x3)
 337 #define LTQ_EBU_PCC_STAT_CD_GET(val)   ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3)
 338
 339 /*******************************************************************************
 340  * PCC Interrupt Status Register
 341  ******************************************************************************/
 342
 343 /* Interrupt Request Active Interrupt (4) */
 344 #define LTQ_EBU_PCC_ISTAT_IREQ   (0x1 << 4)
 345 #define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val)   (((val) & 0x1) << 4)
 346 #define LTQ_EBU_PCC_ISTAT_IREQ_GET(val)   ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1)
 347 #define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4))
 348 /* Over Current Status Change Interrupt (3) */
 349 #define LTQ_EBU_PCC_ISTAT_OC   (0x1 << 3)
 350 #define LTQ_EBU_PCC_ISTAT_OC_VAL(val)   (((val) & 0x1) << 3)
 351 #define LTQ_EBU_PCC_ISTAT_OC_GET(val)   ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1)
 352 #define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3))
 353 /* Socket Power on Status Change Interrupt (2) */
 354 #define LTQ_EBU_PCC_ISTAT_SPON   (0x1 << 2)
 355 #define LTQ_EBU_PCC_ISTAT_SPON_VAL(val)   (((val) & 0x1) << 2)
 356 #define LTQ_EBU_PCC_ISTAT_SPON_GET(val)   ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1)
 357 #define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2))
 358 /* Voltage Sense Status Change Interrupt (1) */
 359 #define LTQ_EBU_PCC_ISTAT_VS   (0x1 << 1)
 360 #define LTQ_EBU_PCC_ISTAT_VS_VAL(val)   (((val) & 0x1) << 1)
 361 #define LTQ_EBU_PCC_ISTAT_VS_GET(val)   ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1)
 362 #define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1))
 363 /* Card Detect Status Change Interrupt (0) */
 364 #define LTQ_EBU_PCC_ISTAT_CD   (0x1)
 365 #define LTQ_EBU_PCC_ISTAT_CD_VAL(val)   (((val) & 0x1) << 0)
 366 #define LTQ_EBU_PCC_ISTAT_CD_GET(val)   ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1)
 367 #define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0))
 368
 369 /*******************************************************************************
 370  * PCC Interrupt Enable Register
 371  ******************************************************************************/
 372
 373 /* Enable of Interrupt Request IR (4) */
 374 #define LTQ_EBU_PCC_IEN_IR   (0x1 << 4)
 375 #define LTQ_EBU_PCC_IEN_IR_VAL(val)   (((val) & 0x1) << 4)
 376 #define LTQ_EBU_PCC_IEN_IR_GET(val)   ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1)
 377 #define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4))
 378 /* Enable of Interrupt Request OC event (3) */
 379 #define LTQ_EBU_PCC_IEN_OC   (0x1 << 3)
 380 #define LTQ_EBU_PCC_IEN_OC_VAL(val)   (((val) & 0x1) << 3)
 381 #define LTQ_EBU_PCC_IEN_OC_GET(val)   ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1)
 382 #define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3))
 383 /* Enable of Interrupt Request Socket Power On (2) */
 384 #define LTQ_EBU_PCC_IEN_PWRON   (0x1 << 2)
 385 #define LTQ_EBU_PCC_IEN_PWRON_VAL(val)   (((val) & 0x1) << 2)
 386 #define LTQ_EBU_PCC_IEN_PWRON_GET(val)   ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1)
 387 #define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2))
 388 /* Enable of Interrupt Request Voltage Sense (1) */
 389 #define LTQ_EBU_PCC_IEN_VS   (0x1 << 1)
 390 #define LTQ_EBU_PCC_IEN_VS_VAL(val)   (((val) & 0x1) << 1)
 391 #define LTQ_EBU_PCC_IEN_VS_GET(val)   ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1)
 392 #define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1))
 393 /* Enable of Interrupt Request Card Detect (0) */
 394 #define LTQ_EBU_PCC_IEN_CD   (0x1)
 395 #define LTQ_EBU_PCC_IEN_CD_VAL(val)   (((val) & 0x1) << 0)
 396 #define LTQ_EBU_PCC_IEN_CD_GET(val)   ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1)
 397 #define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0))
 398
 399 /*******************************************************************************
 400  * PCC Interrupt Output Status Register
 401  ******************************************************************************/
 402
 403 /* Status of Interrupt Request IR (4) */
 404 #define LTQ_EBU_PCC_INT_OUT_IR   (0x1 << 4)
 405 #define LTQ_EBU_PCC_INT_OUT_IR_GET(val)   ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1)
 406 /* Status of Interrupt Request OC (3) */
 407 #define LTQ_EBU_PCC_INT_OUT_OC   (0x1 << 3)
 408 #define LTQ_EBU_PCC_INT_OUT_OC_GET(val)   ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1)
 409 /* Status of Interrupt Request Socket Power On (2) */
 410 #define LTQ_EBU_PCC_INT_OUT_PWRON   (0x1 << 2)
 411 #define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val)   ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1)
 412 /* Status of Interrupt Request Voltage Sense (1) */
 413 #define LTQ_EBU_PCC_INT_OUT_VS   (0x1 << 1)
 414 #define LTQ_EBU_PCC_INT_OUT_VS_GET(val)   ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1)
 415 /* Status of Interrupt Request Card Detect (0) */
 416 #define LTQ_EBU_PCC_INT_OUT_CD   (0x1)
 417 #define LTQ_EBU_PCC_INT_OUT_CD_GET(val)   ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1)
 418
 419 /*******************************************************************************
 420  * PCC Interrupt Request Set Register
 421  ******************************************************************************/
 422
 423 /* Set Interrupt Request IR (4) */
 424 #define LTQ_EBU_PCC_IRS_IR   (0x1 << 4)
 425 #define LTQ_EBU_PCC_IRS_IR_VAL(val)   (((val) & 0x1) << 4)
 426 #define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4)
 427 /* Set Interrupt Request OC (3) */
 428 #define LTQ_EBU_PCC_IRS_OC   (0x1 << 3)
 429 #define LTQ_EBU_PCC_IRS_OC_VAL(val)   (((val) & 0x1) << 3)
 430 #define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3)
 431 /* Set Interrupt Request Socket Power On (2) */
 432 #define LTQ_EBU_PCC_IRS_PWRON   (0x1 << 2)
 433 #define LTQ_EBU_PCC_IRS_PWRON_VAL(val)   (((val) & 0x1) << 2)
 434 #define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2)
 435 /* Set Interrupt Request Voltage Sense (1) */
 436 #define LTQ_EBU_PCC_IRS_VS   (0x1 << 1)
 437 #define LTQ_EBU_PCC_IRS_VS_VAL(val)   (((val) & 0x1) << 1)
 438 #define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1)
 439 /* Set Interrupt Request Card Detect (0) */
 440 #define LTQ_EBU_PCC_IRS_CD   (0x1)
 441 #define LTQ_EBU_PCC_IRS_CD_VAL(val)   (((val) & 0x1) << 0)
 442 #define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0)
 443
 444 /*******************************************************************************
 445  * NAND Flash Control Register
 446  ******************************************************************************/
 447
 448 /* ECC Enabling (31) */
 449 #define LTQ_EBU_NAND_CON_ECC_ON   (0x1 << 31)
 450 #define LTQ_EBU_NAND_CON_ECC_ON_VAL(val)   (((val) & 0x1) << 31)
 451 #define LTQ_EBU_NAND_CON_ECC_ON_GET(val)   ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1)
 452 #define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31))
 453 /* Latch enable (23:18) */
 454 #define LTQ_EBU_NAND_CON_LAT_EN   (0x3f << 18)
 455 #define LTQ_EBU_NAND_CON_LAT_EN_VAL(val)   (((val) & 0x3f) << 18)
 456 #define LTQ_EBU_NAND_CON_LAT_EN_GET(val)   ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f)
 457 #define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18))
 458 /* Output ChipSelect# Selection (11:10) */
 459 #define LTQ_EBU_NAND_CON_OUT_CS_S   (0x3 << 10)
 460 #define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val)   (((val) & 0x3) << 10)
 461 #define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val)   ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3)
 462 #define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10))
 463 /* Input ChipSelect# Selection (9:8) */
 464 #define LTQ_EBU_NAND_CON_IN_CS_S   (0x3 << 8)
 465 #define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val)   (((val) & 0x3) << 8)
 466 #define LTQ_EBU_NAND_CON_IN_CS_S_GET(val)   ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3)
 467 #define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8))
 468 /* Set PRE (7) */
 469 #define LTQ_EBU_NAND_CON_PRE_P   (0x1 << 7)
 470 #define LTQ_EBU_NAND_CON_PRE_P_VAL(val)   (((val) & 0x1) << 7)
 471 #define LTQ_EBU_NAND_CON_PRE_P_GET(val)   ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1)
 472 #define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7))
 473 /* Set WP Active Polarity (6) */
 474 #define LTQ_EBU_NAND_CON_WP_P   (0x1 << 6)
 475 #define LTQ_EBU_NAND_CON_WP_P_VAL(val)   (((val) & 0x1) << 6)
 476 #define LTQ_EBU_NAND_CON_WP_P_GET(val)   ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1)
 477 #define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6))
 478 /* Set SE Active Polarity (5) */
 479 #define LTQ_EBU_NAND_CON_SE_P   (0x1 << 5)
 480 #define LTQ_EBU_NAND_CON_SE_P_VAL(val)   (((val) & 0x1) << 5)
 481 #define LTQ_EBU_NAND_CON_SE_P_GET(val)   ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1)
 482 #define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5))
 483 /* Set CS Active Polarity (4) */
 484 #define LTQ_EBU_NAND_CON_CS_P   (0x1 << 4)
 485 #define LTQ_EBU_NAND_CON_CS_P_VAL(val)   (((val) & 0x1) << 4)
 486 #define LTQ_EBU_NAND_CON_CS_P_GET(val)   ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1)
 487 #define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4))
 488 /* Set CLE Active Polarity (3) */
 489 #define LTQ_EBU_NAND_CON_CLE_P   (0x1 << 3)
 490 #define LTQ_EBU_NAND_CON_CLE_P_VAL(val)   (((val) & 0x1) << 3)
 491 #define LTQ_EBU_NAND_CON_CLE_P_GET(val)   ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1)
 492 #define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3))
 493 /* Set ALE Active Polarity (2) */
 494 #define LTQ_EBU_NAND_CON_ALE_P   (0x1 << 2)
 495 #define LTQ_EBU_NAND_CON_ALE_P_VAL(val)   (((val) & 0x1) << 2)
 496 #define LTQ_EBU_NAND_CON_ALE_P_GET(val)   ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1)
 497 #define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2))
 498 /* NAND CS Mux with EBU CS Enable (1) */
 499 #define LTQ_EBU_NAND_CON_CSMUX_E   (0x1 << 1)
 500 #define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val)   (((val) & 0x1) << 1)
 501 #define LTQ_EBU_NAND_CON_CSMUX_E_GET(val)   ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1)
 502 #define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1))
 503 /* NAND FLASH Mode Support (0) */
 504 #define LTQ_EBU_NAND_CON_NANDMODE   (0x1)
 505 #define LTQ_EBU_NAND_CON_NANDMODE_VAL(val)   (((val) & 0x1) << 0)
 506 #define LTQ_EBU_NAND_CON_NANDMODE_GET(val)   ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1)
 507 #define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0))
 508
 509 /*******************************************************************************
 510  * NAND Flash State Register
 511  ******************************************************************************/
 512
 513 /* Reserved (31:3) */
 514 #define LTQ_EBU_NAND_WAIT_RES   (0x1fffffff << 3)
 515 #define LTQ_EBU_NAND_WAIT_RES_GET(val)   ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff)
 516 /* NAND Write Complete (3) */
 517 #define LTQ_EBU_NAND_WAIT_WR_C   (0x1 << 3)
 518 #define LTQ_EBU_NAND_WAIT_WR_C_GET(val)   ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1)
 519 /* Record the RD Edge (rising ) (2) */
 520 #define LTQ_EBU_NAND_WAIT_RD_EDGE   (0x1 << 2)
 521 #define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val)   ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1)
 522 /* Record the BY# Edge (falling) (1) */
 523 #define LTQ_EBU_NAND_WAIT_BY_EDGE   (0x1 << 1)
 524 #define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val)   ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1)
 525 /* Rd/BY# value (0) */
 526 #define LTQ_EBU_NAND_WAIT_RDBY_VALUE   (0x1)
 527 #define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val)   ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1)
 528
 529 /*******************************************************************************
 530  * NAND ECC Result Register 0
 531  ******************************************************************************/
 532
 533 /* Reserved (31:24) */
 534 #define LTQ_EBU_NAND_ECC0_RES   (0xff << 24)
 535 #define LTQ_EBU_NAND_ECC0_RES_GET(val)   ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff)
 536 /* ECC value (23:16) */
 537 #define LTQ_EBU_NAND_ECC0_ECC_B2   (0xff << 16)
 538 #define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val)   (((val) & 0xff) << 16)
 539 #define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val)   ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff)
 540 #define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16))
 541 /* ECC value (15:8) */
 542 #define LTQ_EBU_NAND_ECC0_ECC_B1   (0xff << 8)
 543 #define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val)   (((val) & 0xff) << 8)
 544 #define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val)   ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff)
 545 #define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8))
 546 /* ECC value (7:0) */
 547 #define LTQ_EBU_NAND_ECC0_ECC_B0   (0xff)
 548 #define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val)   (((val) & 0xff) << 0)
 549 #define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val)   ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff)
 550 #define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0))
 551
 552 /*******************************************************************************
 553  * NAND ECC Address Counter Register
 554  ******************************************************************************/
 555
 556 /* Reserved (31:9) */
 557 #define LTQ_EBU_NAND_ECC_AC_RES   (0x7fffff << 9)
 558 #define LTQ_EBU_NAND_ECC_AC_RES_GET(val)   ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff)
 559 /* ECC address counter (8:0) */
 560 #define LTQ_EBU_NAND_ECC_AC_ECC_AC   (0x1ff)
 561 #define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val)   (((val) & 0x1ff) << 0)
 562 #define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val)   ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff)
 563 #define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0))
 564
 565 /*******************************************************************************
 566  * Internal Address Emulation Register
 567  ******************************************************************************/
 568
 569 /* Memory Region Base Address (31:12) */
 570 #define LTQ_EBU_EMU_ADDR_BASE   (0xfffff << 12)
 571 #define LTQ_EBU_EMU_ADDR_BASE_VAL(val)   (((val) & 0xfffff) << 12)
 572 #define LTQ_EBU_EMU_ADDR_BASE_GET(val)   ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff)
 573 #define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12))
 574 /* Memory Region Address Mask (7:4) */
 575 #define LTQ_EBU_EMU_ADDR_MASK   (0xf << 4)
 576 #define LTQ_EBU_EMU_ADDR_MASK_VAL(val)   (((val) & 0xf) << 4)
 577 #define LTQ_EBU_EMU_ADDR_MASK_GET(val)   ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf)
 578 #define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4))
 579 /* Memory Region Mirror Segment B Control (1) */
 580 #define LTQ_EBU_EMU_ADDR_MRMB   (0x1 << 1)
 581 #define LTQ_EBU_EMU_ADDR_MRMB_VAL(val)   (((val) & 0x1) << 1)
 582 #define LTQ_EBU_EMU_ADDR_MRMB_GET(val)   ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1)
 583 #define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1))
 584 /* Memory Region Enable Control (0) */
 585 #define LTQ_EBU_EMU_ADDR_MREC   (0x1)
 586 #define LTQ_EBU_EMU_ADDR_MREC_VAL(val)   (((val) & 0x1) << 0)
 587 #define LTQ_EBU_EMU_ADDR_MREC_GET(val)   ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1)
 588 #define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0))
 589
 590 /*******************************************************************************
 591  * nternal Emulator Configuration Register
 592  ******************************************************************************/
 593
 594 /* Overlay Memory Control Region 3 (3) */
 595 #define LTQ_EBU_EMU_CON_OVL3   (0x1 << 3)
 596 #define LTQ_EBU_EMU_CON_OVL3_VAL(val)   (((val) & 0x1) << 3)
 597 #define LTQ_EBU_EMU_CON_OVL3_GET(val)   ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1)
 598 #define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3))
 599 /* Overlay Memory Control Region 2 (2) */
 600 #define LTQ_EBU_EMU_CON_OVL2   (0x1 << 2)
 601 #define LTQ_EBU_EMU_CON_OVL2_VAL(val)   (((val) & 0x1) << 2)
 602 #define LTQ_EBU_EMU_CON_OVL2_GET(val)   ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1)
 603 #define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2))
 604 /* Overlay Memory Control Region 1 (1) */
 605 #define LTQ_EBU_EMU_CON_OVL1   (0x1 << 1)
 606 #define LTQ_EBU_EMU_CON_OVL1_VAL(val)   (((val) & 0x1) << 1)
 607 #define LTQ_EBU_EMU_CON_OVL1_GET(val)   ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1)
 608 #define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1))
 609 /* Overlay Memory Control Region 0 (0) */
 610 #define LTQ_EBU_EMU_CON_OVL0   (0x1)
 611 #define LTQ_EBU_EMU_CON_OVL0_VAL(val)   (((val) & 0x1) << 0)
 612 #define LTQ_EBU_EMU_CON_OVL0_GET(val)   ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1)
 613 #define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0))
 614
 615 #endif /* __LTQ_EBU_H */