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[lantiq] move files/ -> files-3.3/
[openwrt/svn-archive/archive.git] / target / linux / lantiq / files-3.3 / arch / mips / lantiq / xway / timer.c
1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/fs.h>
6 #include <linux/miscdevice.h>
7 #include <linux/init.h>
8 #include <linux/uaccess.h>
9 #include <linux/unistd.h>
10 #include <linux/errno.h>
11 #include <linux/interrupt.h>
12 #include <linux/sched.h>
13
14 #include <asm/irq.h>
15 #include <asm/div64.h>
16 #include "../clk.h"
17
18 #include <lantiq_soc.h>
19 #include <lantiq_irq.h>
20 #include <lantiq_timer.h>
21
22 #define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
23
24 #ifdef TIMER1A
25 #define FIRST_TIMER TIMER1A
26 #else
27 #define FIRST_TIMER 2
28 #endif
29
30 /*
31 * GPTC divider is set or not.
32 */
33 #define GPTU_CLC_RMC_IS_SET 0
34
35 /*
36 * Timer Interrupt (IRQ)
37 */
38 /* Must be adjusted when ICU driver is available */
39 #define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
40
41 /*
42 * Bits Operation
43 */
44 #define GET_BITS(x, msb, lsb) \
45 (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
46 #define SET_BITS(x, msb, lsb, value) \
47 (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
48 (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
49
50 /*
51 * GPTU Register Mapping
52 */
53 #define LQ_GPTU (KSEG1 + 0x1E100A00)
54 #define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
55 #define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
56 #define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
57 #define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
58 #define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
59 #define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
60 #define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
61 #define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
62 #define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
63
64 /*
65 * Clock Control Register
66 */
67 #define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
68 #define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
69 #define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
70 #define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
71 #define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
72 #define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
73 #define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
74
75 #define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
76 #define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
77 #define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
78 #define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
79 #define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
80 #define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
81 #define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
82
83 /*
84 * ID Register
85 */
86 #define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
87 #define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
88 #define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
89
90 /*
91 * Control Register of Timer/Counter nX
92 * n is the index of block (1 based index)
93 * X is either A or B
94 */
95 #define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
96 #define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
97 #define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
98 #define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
99 #define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
100 #define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
101 #define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
102 #define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
103 #define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
104 #define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
105
106 #define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
107 #define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
108 #define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
109 #define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
110 #define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
111 #define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
112 #define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
113 #define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
114 #define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
115
116 #define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
117 #define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
118 #define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
119
120 #define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
121 #define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
122
123 #define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
124 #define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
125 #define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
126 #define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
127 #define TIMER_FLAG_NONE_EDGE 0x0000
128 #define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
129 #define TIMER_FLAG_REAL 0x0000
130 #define TIMER_FLAG_INVERT 0x0040
131 #define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
132 #define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
133 #define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
134 #define TIMER_FLAG_CALLBACK_IN_HB 0x0200
135 #define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
136 #define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
137
138 struct timer_dev_timer {
139 unsigned int f_irq_on;
140 unsigned int irq;
141 unsigned int flag;
142 unsigned long arg1;
143 unsigned long arg2;
144 };
145
146 struct timer_dev {
147 struct mutex gptu_mutex;
148 unsigned int number_of_timers;
149 unsigned int occupation;
150 unsigned int f_gptu_on;
151 struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
152 };
153
154 unsigned long ltq_danube_fpi_bus_clock(int fpi);
155 unsigned long ltq_vr9_fpi_bus_clock(int fpi);
156
157 unsigned int ltq_get_fpi_bus_clock(int fpi) {
158 if (ltq_is_ase())
159 return CLOCK_133M;
160 else if (ltq_is_vr9())
161 return ltq_vr9_fpi_bus_clock(fpi);
162
163 return ltq_danube_fpi_bus_clock(fpi);
164 }
165
166
167 static long gptu_ioctl(struct file *, unsigned int, unsigned long);
168 static int gptu_open(struct inode *, struct file *);
169 static int gptu_release(struct inode *, struct file *);
170
171 static struct file_operations gptu_fops = {
172 .owner = THIS_MODULE,
173 .unlocked_ioctl = gptu_ioctl,
174 .open = gptu_open,
175 .release = gptu_release
176 };
177
178 static struct miscdevice gptu_miscdev = {
179 .minor = MISC_DYNAMIC_MINOR,
180 .name = "gptu",
181 .fops = &gptu_fops,
182 };
183
184 static struct timer_dev timer_dev;
185
186 static irqreturn_t timer_irq_handler(int irq, void *p)
187 {
188 unsigned int timer;
189 unsigned int flag;
190 struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
191
192 timer = irq - TIMER_INTERRUPT;
193 if (timer < timer_dev.number_of_timers
194 && dev_timer == &timer_dev.timer[timer]) {
195 /* Clear interrupt. */
196 ltq_w32(1 << timer, LQ_GPTU_IRNCR);
197
198 /* Call user hanler or signal. */
199 flag = dev_timer->flag;
200 if (!(timer & 0x01)
201 || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
202 /* 16-bit timer or timer A of 32-bit timer */
203 switch (TIMER_FLAG_MASK_HANDLE(flag)) {
204 case TIMER_FLAG_CALLBACK_IN_IRQ:
205 case TIMER_FLAG_CALLBACK_IN_HB:
206 if (dev_timer->arg1)
207 (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
208 break;
209 case TIMER_FLAG_SIGNAL:
210 send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
211 break;
212 }
213 }
214 }
215 return IRQ_HANDLED;
216 }
217
218 static inline void lq_enable_gptu(void)
219 {
220 struct clk *clk = clk_get_sys("ltq_gptu", NULL);
221 clk_enable(clk);
222
223 //ltq_pmu_enable(PMU_GPT);
224
225 /* Set divider as 1, disable write protection for SPEN, enable module. */
226 *LQ_GPTU_CLC =
227 GPTU_CLC_SMC_SET(0x00) |
228 GPTU_CLC_RMC_SET(0x01) |
229 GPTU_CLC_FSOE_SET(0) |
230 GPTU_CLC_SBWE_SET(1) |
231 GPTU_CLC_EDIS_SET(0) |
232 GPTU_CLC_SPEN_SET(0) |
233 GPTU_CLC_DISR_SET(0);
234 }
235
236 static inline void lq_disable_gptu(void)
237 {
238 struct clk *clk = clk_get_sys("ltq_gptu", NULL);
239 ltq_w32(0x00, LQ_GPTU_IRNEN);
240 ltq_w32(0xfff, LQ_GPTU_IRNCR);
241
242 /* Set divider as 0, enable write protection for SPEN, disable module. */
243 *LQ_GPTU_CLC =
244 GPTU_CLC_SMC_SET(0x00) |
245 GPTU_CLC_RMC_SET(0x00) |
246 GPTU_CLC_FSOE_SET(0) |
247 GPTU_CLC_SBWE_SET(0) |
248 GPTU_CLC_EDIS_SET(0) |
249 GPTU_CLC_SPEN_SET(0) |
250 GPTU_CLC_DISR_SET(1);
251
252 clk_enable(clk);
253 }
254
255 int lq_request_timer(unsigned int timer, unsigned int flag,
256 unsigned long value, unsigned long arg1, unsigned long arg2)
257 {
258 int ret = 0;
259 unsigned int con_reg, irnen_reg;
260 int n, X;
261
262 if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
263 return -EINVAL;
264
265 printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
266 timer, flag, value);
267
268 if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
269 value &= 0xFFFF;
270 else
271 timer &= ~0x01;
272
273 mutex_lock(&timer_dev.gptu_mutex);
274
275 /*
276 * Allocate timer.
277 */
278 if (timer < FIRST_TIMER) {
279 unsigned int mask;
280 unsigned int shift;
281 /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
282 unsigned int offset = TIMER2A;
283
284 /*
285 * Pick up a free timer.
286 */
287 if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
288 mask = 1 << offset;
289 shift = 1;
290 } else {
291 mask = 3 << offset;
292 shift = 2;
293 }
294 for (timer = offset;
295 timer < offset + timer_dev.number_of_timers;
296 timer += shift, mask <<= shift)
297 if (!(timer_dev.occupation & mask)) {
298 timer_dev.occupation |= mask;
299 break;
300 }
301 if (timer >= offset + timer_dev.number_of_timers) {
302 printk("failed![%d]\n", __LINE__);
303 mutex_unlock(&timer_dev.gptu_mutex);
304 return -EINVAL;
305 } else
306 ret = timer;
307 } else {
308 register unsigned int mask;
309
310 /*
311 * Check if the requested timer is free.
312 */
313 mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
314 if ((timer_dev.occupation & mask)) {
315 printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
316 __LINE__, mask, timer_dev.occupation);
317 mutex_unlock(&timer_dev.gptu_mutex);
318 return -EBUSY;
319 } else {
320 timer_dev.occupation |= mask;
321 ret = 0;
322 }
323 }
324
325 /*
326 * Prepare control register value.
327 */
328 switch (TIMER_FLAG_MASK_EDGE(flag)) {
329 default:
330 case TIMER_FLAG_NONE_EDGE:
331 con_reg = GPTU_CON_EDGE_SET(0x00);
332 break;
333 case TIMER_FLAG_RISE_EDGE:
334 con_reg = GPTU_CON_EDGE_SET(0x01);
335 break;
336 case TIMER_FLAG_FALL_EDGE:
337 con_reg = GPTU_CON_EDGE_SET(0x02);
338 break;
339 case TIMER_FLAG_ANY_EDGE:
340 con_reg = GPTU_CON_EDGE_SET(0x03);
341 break;
342 }
343 if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
344 con_reg |=
345 TIMER_FLAG_MASK_SRC(flag) ==
346 TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
347 GPTU_CON_SRC_EXT_SET(0);
348 else
349 con_reg |=
350 TIMER_FLAG_MASK_SRC(flag) ==
351 TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
352 GPTU_CON_SRC_EG_SET(0);
353 con_reg |=
354 TIMER_FLAG_MASK_SYNC(flag) ==
355 TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
356 GPTU_CON_SYNC_SET(1);
357 con_reg |=
358 TIMER_FLAG_MASK_INVERT(flag) ==
359 TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
360 con_reg |=
361 TIMER_FLAG_MASK_SIZE(flag) ==
362 TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
363 GPTU_CON_EXT_SET(1);
364 con_reg |=
365 TIMER_FLAG_MASK_STOP(flag) ==
366 TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
367 con_reg |=
368 TIMER_FLAG_MASK_TYPE(flag) ==
369 TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
370 GPTU_CON_CNT_SET(1);
371 con_reg |=
372 TIMER_FLAG_MASK_DIR(flag) ==
373 TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
374
375 /*
376 * Fill up running data.
377 */
378 timer_dev.timer[timer - FIRST_TIMER].flag = flag;
379 timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
380 timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
381 if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
382 timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
383
384 /*
385 * Enable GPTU module.
386 */
387 if (!timer_dev.f_gptu_on) {
388 lq_enable_gptu();
389 timer_dev.f_gptu_on = 1;
390 }
391
392 /*
393 * Enable IRQ.
394 */
395 if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
396 if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
397 timer_dev.timer[timer - FIRST_TIMER].arg1 =
398 (unsigned long) find_task_by_vpid((int) arg1);
399
400 irnen_reg = 1 << (timer - FIRST_TIMER);
401
402 if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
403 || (TIMER_FLAG_MASK_HANDLE(flag) ==
404 TIMER_FLAG_CALLBACK_IN_IRQ
405 && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
406 enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
407 timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
408 }
409 } else
410 irnen_reg = 0;
411
412 /*
413 * Write config register, reload value and enable interrupt.
414 */
415 n = timer >> 1;
416 X = timer & 0x01;
417 *LQ_GPTU_CON(n, X) = con_reg;
418 *LQ_GPTU_RELOAD(n, X) = value;
419 /* printk("reload value = %d\n", (u32)value); */
420 *LQ_GPTU_IRNEN |= irnen_reg;
421
422 mutex_unlock(&timer_dev.gptu_mutex);
423 printk("successful!\n");
424 return ret;
425 }
426 EXPORT_SYMBOL(lq_request_timer);
427
428 int lq_free_timer(unsigned int timer)
429 {
430 unsigned int flag;
431 unsigned int mask;
432 int n, X;
433
434 if (!timer_dev.f_gptu_on)
435 return -EINVAL;
436
437 if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
438 return -EINVAL;
439
440 mutex_lock(&timer_dev.gptu_mutex);
441
442 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
443 if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
444 timer &= ~0x01;
445
446 mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
447 if (((timer_dev.occupation & mask) ^ mask)) {
448 mutex_unlock(&timer_dev.gptu_mutex);
449 return -EINVAL;
450 }
451
452 n = timer >> 1;
453 X = timer & 0x01;
454
455 if (GPTU_CON_EN(n, X))
456 *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
457
458 *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
459 *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
460
461 if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
462 disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
463 timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
464 }
465
466 timer_dev.occupation &= ~mask;
467 if (!timer_dev.occupation && timer_dev.f_gptu_on) {
468 lq_disable_gptu();
469 timer_dev.f_gptu_on = 0;
470 }
471
472 mutex_unlock(&timer_dev.gptu_mutex);
473
474 return 0;
475 }
476 EXPORT_SYMBOL(lq_free_timer);
477
478 int lq_start_timer(unsigned int timer, int is_resume)
479 {
480 unsigned int flag;
481 unsigned int mask;
482 int n, X;
483
484 if (!timer_dev.f_gptu_on)
485 return -EINVAL;
486
487 if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
488 return -EINVAL;
489
490 mutex_lock(&timer_dev.gptu_mutex);
491
492 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
493 if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
494 timer &= ~0x01;
495
496 mask = (TIMER_FLAG_MASK_SIZE(flag) ==
497 TIMER_FLAG_16BIT ? 1 : 3) << timer;
498 if (((timer_dev.occupation & mask) ^ mask)) {
499 mutex_unlock(&timer_dev.gptu_mutex);
500 return -EINVAL;
501 }
502
503 n = timer >> 1;
504 X = timer & 0x01;
505
506 *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
507
508 mutex_unlock(&timer_dev.gptu_mutex);
509
510 return 0;
511 }
512 EXPORT_SYMBOL(lq_start_timer);
513
514 int lq_stop_timer(unsigned int timer)
515 {
516 unsigned int flag;
517 unsigned int mask;
518 int n, X;
519
520 if (!timer_dev.f_gptu_on)
521 return -EINVAL;
522
523 if (timer < FIRST_TIMER
524 || timer >= FIRST_TIMER + timer_dev.number_of_timers)
525 return -EINVAL;
526
527 mutex_lock(&timer_dev.gptu_mutex);
528
529 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
530 if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
531 timer &= ~0x01;
532
533 mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
534 if (((timer_dev.occupation & mask) ^ mask)) {
535 mutex_unlock(&timer_dev.gptu_mutex);
536 return -EINVAL;
537 }
538
539 n = timer >> 1;
540 X = timer & 0x01;
541
542 *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
543
544 mutex_unlock(&timer_dev.gptu_mutex);
545
546 return 0;
547 }
548 EXPORT_SYMBOL(lq_stop_timer);
549
550 int lq_reset_counter_flags(u32 timer, u32 flags)
551 {
552 unsigned int oflag;
553 unsigned int mask, con_reg;
554 int n, X;
555
556 if (!timer_dev.f_gptu_on)
557 return -EINVAL;
558
559 if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
560 return -EINVAL;
561
562 mutex_lock(&timer_dev.gptu_mutex);
563
564 oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
565 if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
566 timer &= ~0x01;
567
568 mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
569 if (((timer_dev.occupation & mask) ^ mask)) {
570 mutex_unlock(&timer_dev.gptu_mutex);
571 return -EINVAL;
572 }
573
574 switch (TIMER_FLAG_MASK_EDGE(flags)) {
575 default:
576 case TIMER_FLAG_NONE_EDGE:
577 con_reg = GPTU_CON_EDGE_SET(0x00);
578 break;
579 case TIMER_FLAG_RISE_EDGE:
580 con_reg = GPTU_CON_EDGE_SET(0x01);
581 break;
582 case TIMER_FLAG_FALL_EDGE:
583 con_reg = GPTU_CON_EDGE_SET(0x02);
584 break;
585 case TIMER_FLAG_ANY_EDGE:
586 con_reg = GPTU_CON_EDGE_SET(0x03);
587 break;
588 }
589 if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
590 con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
591 else
592 con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
593 con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
594 con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
595 con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
596 con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
597 con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
598 con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
599
600 timer_dev.timer[timer - FIRST_TIMER].flag = flags;
601 if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
602 timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
603
604 n = timer >> 1;
605 X = timer & 0x01;
606
607 *LQ_GPTU_CON(n, X) = con_reg;
608 smp_wmb();
609 printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
610 mutex_unlock(&timer_dev.gptu_mutex);
611 return 0;
612 }
613 EXPORT_SYMBOL(lq_reset_counter_flags);
614
615 int lq_get_count_value(unsigned int timer, unsigned long *value)
616 {
617 unsigned int flag;
618 unsigned int mask;
619 int n, X;
620
621 if (!timer_dev.f_gptu_on)
622 return -EINVAL;
623
624 if (timer < FIRST_TIMER
625 || timer >= FIRST_TIMER + timer_dev.number_of_timers)
626 return -EINVAL;
627
628 mutex_lock(&timer_dev.gptu_mutex);
629
630 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
631 if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
632 timer &= ~0x01;
633
634 mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
635 if (((timer_dev.occupation & mask) ^ mask)) {
636 mutex_unlock(&timer_dev.gptu_mutex);
637 return -EINVAL;
638 }
639
640 n = timer >> 1;
641 X = timer & 0x01;
642
643 *value = *LQ_GPTU_COUNT(n, X);
644
645 mutex_unlock(&timer_dev.gptu_mutex);
646
647 return 0;
648 }
649 EXPORT_SYMBOL(lq_get_count_value);
650
651 u32 lq_cal_divider(unsigned long freq)
652 {
653 u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
654 u32 clock_divider = 1;
655 module_freq = fpi * 1000;
656 do_div(module_freq, clock_divider * freq);
657 return module_freq;
658 }
659 EXPORT_SYMBOL(lq_cal_divider);
660
661 int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
662 int is_ext_src, unsigned int handle_flag, unsigned long arg1,
663 unsigned long arg2)
664 {
665 unsigned long divider;
666 unsigned int flag;
667
668 divider = lq_cal_divider(freq);
669 if (divider == 0)
670 return -EINVAL;
671 flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
672 | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
673 | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
674 | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
675 | TIMER_FLAG_MASK_HANDLE(handle_flag);
676
677 printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
678 timer, freq, divider);
679 return lq_request_timer(timer, flag, divider, arg1, arg2);
680 }
681 EXPORT_SYMBOL(lq_set_timer);
682
683 int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
684 unsigned long arg1, unsigned long arg2)
685 {
686 printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
687 return lq_request_timer(timer, flag, reload, arg1, arg2);
688 }
689 EXPORT_SYMBOL(lq_set_counter);
690
691 static long gptu_ioctl(struct file *file, unsigned int cmd,
692 unsigned long arg)
693 {
694 int ret;
695 struct gptu_ioctl_param param;
696
697 if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
698 return -EFAULT;
699 copy_from_user(&param, (void *) arg, sizeof(param));
700
701 if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
702 || GPTU_SET_COUNTER) && param.timer < 2)
703 || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
704 && !access_ok(VERIFY_WRITE, arg,
705 sizeof(struct gptu_ioctl_param)))
706 return -EFAULT;
707
708 switch (cmd) {
709 case GPTU_REQUEST_TIMER:
710 ret = lq_request_timer(param.timer, param.flag, param.value,
711 (unsigned long) param.pid,
712 (unsigned long) param.sig);
713 if (ret > 0) {
714 copy_to_user(&((struct gptu_ioctl_param *) arg)->
715 timer, &ret, sizeof(&ret));
716 ret = 0;
717 }
718 break;
719 case GPTU_FREE_TIMER:
720 ret = lq_free_timer(param.timer);
721 break;
722 case GPTU_START_TIMER:
723 ret = lq_start_timer(param.timer, param.flag);
724 break;
725 case GPTU_STOP_TIMER:
726 ret = lq_stop_timer(param.timer);
727 break;
728 case GPTU_GET_COUNT_VALUE:
729 ret = lq_get_count_value(param.timer, &param.value);
730 if (!ret)
731 copy_to_user(&((struct gptu_ioctl_param *) arg)->
732 value, &param.value,
733 sizeof(param.value));
734 break;
735 case GPTU_CALCULATE_DIVIDER:
736 param.value = lq_cal_divider(param.value);
737 if (param.value == 0)
738 ret = -EINVAL;
739 else {
740 copy_to_user(&((struct gptu_ioctl_param *) arg)->
741 value, &param.value,
742 sizeof(param.value));
743 ret = 0;
744 }
745 break;
746 case GPTU_SET_TIMER:
747 ret = lq_set_timer(param.timer, param.value,
748 TIMER_FLAG_MASK_STOP(param.flag) !=
749 TIMER_FLAG_ONCE ? 1 : 0,
750 TIMER_FLAG_MASK_SRC(param.flag) ==
751 TIMER_FLAG_EXT_SRC ? 1 : 0,
752 TIMER_FLAG_MASK_HANDLE(param.flag) ==
753 TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
754 TIMER_FLAG_NO_HANDLE,
755 (unsigned long) param.pid,
756 (unsigned long) param.sig);
757 if (ret > 0) {
758 copy_to_user(&((struct gptu_ioctl_param *) arg)->
759 timer, &ret, sizeof(&ret));
760 ret = 0;
761 }
762 break;
763 case GPTU_SET_COUNTER:
764 lq_set_counter(param.timer, param.flag, param.value, 0, 0);
765 if (ret > 0) {
766 copy_to_user(&((struct gptu_ioctl_param *) arg)->
767 timer, &ret, sizeof(&ret));
768 ret = 0;
769 }
770 break;
771 default:
772 ret = -ENOTTY;
773 }
774
775 return ret;
776 }
777
778 static int gptu_open(struct inode *inode, struct file *file)
779 {
780 return 0;
781 }
782
783 static int gptu_release(struct inode *inode, struct file *file)
784 {
785 return 0;
786 }
787
788 int __init lq_gptu_init(void)
789 {
790 int ret;
791 unsigned int i;
792
793 ltq_w32(0, LQ_GPTU_IRNEN);
794 ltq_w32(0xfff, LQ_GPTU_IRNCR);
795
796 memset(&timer_dev, 0, sizeof(timer_dev));
797 mutex_init(&timer_dev.gptu_mutex);
798
799 lq_enable_gptu();
800 timer_dev.number_of_timers = GPTU_ID_CFG * 2;
801 lq_disable_gptu();
802 if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
803 timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
804 printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
805
806 ret = misc_register(&gptu_miscdev);
807 if (ret) {
808 printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
809 return ret;
810 } else {
811 printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
812 }
813
814 for (i = 0; i < timer_dev.number_of_timers; i++) {
815 ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
816 if (ret) {
817 for (; i >= 0; i--)
818 free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
819 misc_deregister(&gptu_miscdev);
820 printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
821 return ret;
822 } else {
823 timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
824 disable_irq(timer_dev.timer[i].irq);
825 printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
826 }
827 }
828
829 return 0;
830 }
831
832 void __exit lq_gptu_exit(void)
833 {
834 unsigned int i;
835
836 for (i = 0; i < timer_dev.number_of_timers; i++) {
837 if (timer_dev.timer[i].f_irq_on)
838 disable_irq(timer_dev.timer[i].irq);
839 free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
840 }
841 lq_disable_gptu();
842 misc_deregister(&gptu_miscdev);
843 }
844
845 module_init(lq_gptu_init);
846 module_exit(lq_gptu_exit);
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