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lantiq: add ath9k led pin support
[openwrt/svn-archive/archive.git] / target / linux / lantiq / patches-3.10 / 0205-lantiq-xrx200-switch.patch
1 --- a/drivers/net/ethernet/lantiq_xrx200.c
2 +++ b/drivers/net/ethernet/lantiq_xrx200.c
3 @@ -16,6 +16,7 @@
4 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
5 */
6
7 +#include <linux/switch.h>
8 #include <linux/etherdevice.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 @@ -31,6 +32,7 @@
12 #include <lantiq_soc.h>
13
14 #include "lantiq_pce.h"
15 +#include "lantiq_xrx200_sw.h"
16
17 #define SW_POLLING
18 #define SW_ROUTING
19 @@ -46,6 +48,10 @@
20 #define XRX200_MAX_DEV 1
21 #endif
22
23 +#define XRX200_MAX_VLAN 64
24 +#define XRX200_PCE_ACTVLAN_IDX 0x01
25 +#define XRX200_PCE_VLANMAP_IDX 0x02
26 +
27 #define XRX200_MAX_PORT 7
28 #define XRX200_MAX_DMA 8
29
30 @@ -58,7 +64,6 @@
31 #define XRX200_PORT_TYPE_MAC 2
32
33 /* DMA */
34 -#define XRX200_DMA_CRC_LEN 0x4
35 #define XRX200_DMA_DATA_LEN 0x600
36 #define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
37 #define XRX200_DMA_RX 0
38 @@ -225,6 +230,8 @@ struct xrx200_hw {
39 unsigned short wan_map;
40
41 spinlock_t lock;
42 +
43 + struct switch_dev swdev;
44 };
45
46 struct xrx200_priv {
47 @@ -233,7 +240,8 @@ struct xrx200_priv {
48
49 struct xrx200_port port[XRX200_MAX_PORT];
50 int num_port;
51 - int wan;
52 + bool wan;
53 + bool sw;
54 unsigned short port_map;
55 unsigned char mac[6];
56
57 @@ -265,6 +273,585 @@ static __iomem void *xrx200_pmac_membase
58 #define ltq_pmac_w32_mask(x, y, z) \
59 ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
60
61 +#define XRX200_GLOBAL_REGATTR(reg) \
62 + .id = reg, \
63 + .type = SWITCH_TYPE_INT, \
64 + .set = xrx200_set_global_attr, \
65 + .get = xrx200_get_global_attr
66 +
67 +#define XRX200_PORT_REGATTR(reg) \
68 + .id = reg, \
69 + .type = SWITCH_TYPE_INT, \
70 + .set = xrx200_set_port_attr, \
71 + .get = xrx200_get_port_attr
72 +
73 +static int xrx200sw_read_x(int reg, int x)
74 +{
75 + int value, mask, addr;
76 +
77 + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
78 + value = ltq_switch_r32(addr);
79 + mask = (1 << xrx200sw_reg[reg].size) - 1;
80 + value = (value >> xrx200sw_reg[reg].shift);
81 +
82 + return (value & mask);
83 +}
84 +
85 +static int xrx200sw_read(int reg)
86 +{
87 + return xrx200sw_read_x(reg, 0);
88 +}
89 +
90 +static void xrx200sw_write_x(int value, int reg, int x)
91 +{
92 + int mask, addr;
93 +
94 + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
95 + mask = (1 << xrx200sw_reg[reg].size) - 1;
96 + mask = (mask << xrx200sw_reg[reg].shift);
97 + value = (value << xrx200sw_reg[reg].shift) & mask;
98 +
99 + ltq_switch_w32_mask(mask, value, addr);
100 +}
101 +
102 +static void xrx200sw_write(int value, int reg)
103 +{
104 + xrx200sw_write_x(value, reg, 0);
105 +}
106 +
107 +struct xrx200_pce_table_entry {
108 + int index; // PCE_TBL_ADDR.ADDR = pData->table_index
109 + int table; // PCE_TBL_CTRL.ADDR = pData->table
110 + unsigned short key[8];
111 + unsigned short val[5];
112 + unsigned short mask;
113 + unsigned short type;
114 + unsigned short valid;
115 + unsigned short gmap;
116 +};
117 +
118 +static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl)
119 +{
120 + // wait until hardware is ready
121 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
122 +
123 + // prepare the table access:
124 + // PCE_TBL_ADDR.ADDR = pData->table_index
125 + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
126 + // PCE_TBL_CTRL.ADDR = pData->table
127 + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
128 +
129 + //(address-based read)
130 + xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
131 +
132 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
133 +
134 + // wait until hardware is ready
135 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
136 +
137 + // read the keys
138 + tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7);
139 + tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6);
140 + tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5);
141 + tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4);
142 + tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3);
143 + tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2);
144 + tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1);
145 + tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0);
146 +
147 + // read the values
148 + tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4);
149 + tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3);
150 + tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2);
151 + tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1);
152 + tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0);
153 +
154 + // read the mask
155 + tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0);
156 + // read the type
157 + tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE);
158 + // read the valid flag
159 + tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD);
160 + // read the group map
161 + tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP);
162 +
163 + return 0;
164 +}
165 +
166 +static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl)
167 +{
168 + // wait until hardware is ready
169 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
170 +
171 + // prepare the table access:
172 + // PCE_TBL_ADDR.ADDR = pData->table_index
173 + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
174 + // PCE_TBL_CTRL.ADDR = pData->table
175 + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
176 +
177 + //(address-based write)
178 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
179 +
180 + // read the keys
181 + xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7);
182 + xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6);
183 + xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5);
184 + xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4);
185 + xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3);
186 + xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2);
187 + xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1);
188 + xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0);
189 +
190 + // read the values
191 + xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4);
192 + xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3);
193 + xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2);
194 + xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1);
195 + xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0);
196 +
197 + // read the mask
198 + xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0);
199 + // read the type
200 + xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE);
201 + // read the valid flag
202 + xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD);
203 + // read the group map
204 + xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP);
205 +
206 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
207 +
208 + // wait until hardware is ready
209 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
210 +
211 + return 0;
212 +}
213 +
214 +static void xrx200sw_fixup_pvids(void)
215 +{
216 + int index, p, portmap, untagged;
217 + struct xrx200_pce_table_entry tem;
218 + struct xrx200_pce_table_entry tev;
219 +
220 + portmap = 0;
221 + for (p = 0; p < XRX200_MAX_PORT; p++)
222 + portmap |= BIT(p);
223 +
224 + tem.table = XRX200_PCE_VLANMAP_IDX;
225 + tev.table = XRX200_PCE_ACTVLAN_IDX;
226 +
227 + for (index = XRX200_MAX_VLAN; index-- > 0;)
228 + {
229 + tev.index = index;
230 + xrx200_pce_table_entry_read(&tev);
231 +
232 + if (tev.valid == 0)
233 + continue;
234 +
235 + tem.index = index;
236 + xrx200_pce_table_entry_read(&tem);
237 +
238 + if (tem.val[0] == 0)
239 + continue;
240 +
241 + untagged = portmap & (tem.val[1] ^ tem.val[2]);
242 +
243 + for (p = 0; p < XRX200_MAX_PORT; p++)
244 + if (untagged & BIT(p))
245 + {
246 + portmap &= ~BIT(p);
247 + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
248 + }
249 +
250 + for (p = 0; p < XRX200_MAX_PORT; p++)
251 + if (portmap & BIT(p))
252 + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
253 + }
254 +}
255 +
256 +// swconfig interface
257 +static void xrx200_hw_init(struct xrx200_hw *hw);
258 +
259 +// global
260 +static int xrx200sw_reset_switch(struct switch_dev *dev)
261 +{
262 + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
263 +
264 + xrx200_hw_init(hw);
265 +
266 + return 0;
267 +}
268 +
269 +static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
270 +{
271 + int p;
272 +
273 + if ((attr->max > 0) && (val->value.i > attr->max))
274 + return -EINVAL;
275 +
276 + for (p = 0; p < XRX200_MAX_PORT; p++) {
277 + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p);
278 + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p);
279 + }
280 +
281 + xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN);
282 + return 0;
283 +}
284 +
285 +static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
286 +{
287 + val->value.i = xrx200sw_read(attr->id);
288 + return 0;
289 +}
290 +
291 +static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
292 +{
293 + if ((attr->max > 0) && (val->value.i > attr->max))
294 + return -EINVAL;
295 +
296 + xrx200sw_write(val->value.i, attr->id);
297 + return 0;
298 +}
299 +
300 +static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
301 +{
302 + val->value.i = xrx200sw_read(attr->id);
303 + return 0;
304 +}
305 +
306 +// vlan
307 +static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
308 + struct switch_val *val)
309 +{
310 + int i;
311 + struct xrx200_pce_table_entry tev;
312 + struct xrx200_pce_table_entry tem;
313 +
314 + tev.table = XRX200_PCE_ACTVLAN_IDX;
315 +
316 + for (i = 0; i < XRX200_MAX_VLAN; i++)
317 + {
318 + tev.index = i;
319 + xrx200_pce_table_entry_read(&tev);
320 + if (tev.key[0] == val->value.i && i != val->port_vlan)
321 + return -EINVAL;
322 + }
323 +
324 + tev.index = val->port_vlan;
325 + xrx200_pce_table_entry_read(&tev);
326 + tev.key[0] = val->value.i;
327 + tev.valid = val->value.i > 0;
328 + xrx200_pce_table_entry_write(&tev);
329 +
330 + tem.table = XRX200_PCE_VLANMAP_IDX;
331 + tem.index = val->port_vlan;
332 + xrx200_pce_table_entry_read(&tem);
333 + tem.val[0] = val->value.i;
334 + xrx200_pce_table_entry_write(&tem);
335 +
336 + xrx200sw_fixup_pvids();
337 + return 0;
338 +}
339 +
340 +static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
341 + struct switch_val *val)
342 +{
343 + struct xrx200_pce_table_entry te;
344 +
345 + te.table = XRX200_PCE_ACTVLAN_IDX;
346 + te.index = val->port_vlan;
347 + xrx200_pce_table_entry_read(&te);
348 + val->value.i = te.key[0];
349 +
350 + return 0;
351 +}
352 +
353 +static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
354 +{
355 + int i, portmap, tagmap, untagged;
356 + struct xrx200_pce_table_entry tem;
357 +
358 + portmap = 0;
359 + tagmap = 0;
360 + for (i = 0; i < val->len; i++)
361 + {
362 + struct switch_port *p = &val->value.ports[i];
363 +
364 + portmap |= (1 << p->id);
365 + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
366 + tagmap |= (1 << p->id);
367 + }
368 +
369 + tem.table = XRX200_PCE_VLANMAP_IDX;
370 +
371 + untagged = portmap ^ tagmap;
372 + for (i = 0; i < XRX200_MAX_VLAN; i++)
373 + {
374 + tem.index = i;
375 + xrx200_pce_table_entry_read(&tem);
376 +
377 + if (tem.val[0] == 0)
378 + continue;
379 +
380 + if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i))
381 + return -EINVAL;
382 + }
383 +
384 + tem.index = val->port_vlan;
385 + xrx200_pce_table_entry_read(&tem);
386 +
387 + // auto-enable this vlan if not enabled already
388 + if (tem.val[0] == 0)
389 + {
390 + struct switch_val v;
391 + v.port_vlan = val->port_vlan;
392 + v.value.i = val->port_vlan;
393 + if(xrx200sw_set_vlan_vid(dev, NULL, &v))
394 + return -EINVAL;
395 +
396 + //read updated tem
397 + tem.index = val->port_vlan;
398 + xrx200_pce_table_entry_read(&tem);
399 + }
400 +
401 + tem.val[1] = portmap;
402 + tem.val[2] = tagmap;
403 + xrx200_pce_table_entry_write(&tem);
404 +
405 + xrx200sw_fixup_pvids();
406 +
407 + return 0;
408 +}
409 +
410 +static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
411 +{
412 + int i;
413 + unsigned short ports, tags;
414 + struct xrx200_pce_table_entry tem;
415 +
416 + tem.table = XRX200_PCE_VLANMAP_IDX;
417 + tem.index = val->port_vlan;
418 + xrx200_pce_table_entry_read(&tem);
419 +
420 + ports = tem.val[1];
421 + tags = tem.val[2];
422 +
423 + for (i = 0; i < XRX200_MAX_PORT; i++) {
424 + struct switch_port *p;
425 +
426 + if (!(ports & (1 << i)))
427 + continue;
428 +
429 + p = &val->value.ports[val->len++];
430 + p->id = i;
431 + if (tags & (1 << i))
432 + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
433 + else
434 + p->flags = 0;
435 + }
436 +
437 + return 0;
438 +}
439 +
440 +static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
441 + struct switch_val *val)
442 +{
443 + struct xrx200_pce_table_entry tev;
444 +
445 + tev.table = XRX200_PCE_ACTVLAN_IDX;
446 + tev.index = val->port_vlan;
447 + xrx200_pce_table_entry_read(&tev);
448 +
449 + if (tev.key[0] == 0)
450 + return -EINVAL;
451 +
452 + tev.valid = val->value.i;
453 + xrx200_pce_table_entry_write(&tev);
454 +
455 + xrx200sw_fixup_pvids();
456 + return 0;
457 +}
458 +
459 +static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
460 + struct switch_val *val)
461 +{
462 + struct xrx200_pce_table_entry tev;
463 +
464 + tev.table = XRX200_PCE_ACTVLAN_IDX;
465 + tev.index = val->port_vlan;
466 + xrx200_pce_table_entry_read(&tev);
467 + val->value.i = tev.valid;
468 +
469 + return 0;
470 +}
471 +
472 +// port
473 +static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
474 +{
475 + struct xrx200_pce_table_entry tev;
476 +
477 + if (port >= XRX200_MAX_PORT)
478 + return -EINVAL;
479 +
480 + tev.table = XRX200_PCE_ACTVLAN_IDX;
481 + tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port);
482 + xrx200_pce_table_entry_read(&tev);
483 +
484 + *val = tev.key[0];
485 + return 0;
486 +}
487 +
488 +static int xrx200sw_get_port_link(struct switch_dev *dev,
489 + int port,
490 + struct switch_port_link *link)
491 +{
492 + if (port >= XRX200_MAX_PORT)
493 + return -EINVAL;
494 +
495 + link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port);
496 + if (!link->link)
497 + return 0;
498 +
499 + link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port);
500 +
501 + link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010);
502 + link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020);
503 + link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port));
504 +
505 + link->speed = SWITCH_PORT_SPEED_10;
506 + if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port))
507 + link->speed = SWITCH_PORT_SPEED_100;
508 + if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port))
509 + link->speed = SWITCH_PORT_SPEED_1000;
510 +
511 + return 0;
512 +}
513 +
514 +static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
515 +{
516 + printk("%s %s(%d)\n", __FILE__, __func__, __LINE__);
517 + if (val->port_vlan >= XRX200_MAX_PORT)
518 + return -EINVAL;
519 +
520 + if ((attr->max > 0) && (val->value.i > attr->max))
521 + return -EINVAL;
522 +
523 + xrx200sw_write_x(val->value.i, attr->id, val->port_vlan);
524 + return 0;
525 +}
526 +
527 +static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
528 +{
529 + if (val->port_vlan >= XRX200_MAX_PORT)
530 + return -EINVAL;
531 +
532 + val->value.i = xrx200sw_read_x(attr->id, val->port_vlan);
533 + return 0;
534 +}
535 +
536 +// attributes
537 +static struct switch_attr xrx200sw_globals[] = {
538 + {
539 + .type = SWITCH_TYPE_INT,
540 + .set = xrx200_set_vlan_mode_enable,
541 + .get = xrx200_get_vlan_mode_enable,
542 + .name = "enable_vlan",
543 + .description = "Enable VLAN mode",
544 + .max = 1},
545 +};
546 +
547 +static struct switch_attr xrx200sw_port[] = {
548 + {
549 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR),
550 + .name = "uvr",
551 + .description = "Unknown VLAN Rule",
552 + .max = 1,
553 + },
554 + {
555 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR),
556 + .name = "vsr",
557 + .description = "VLAN Security Rule",
558 + .max = 1,
559 + },
560 + {
561 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR),
562 + .name = "vinr",
563 + .description = "VLAN Ingress Tag Rule",
564 + .max = 2,
565 + },
566 + {
567 + XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM),
568 + .name = "tvm",
569 + .description = "Transparent VLAN Mode",
570 + .max = 1,
571 + },
572 +};
573 +
574 +static struct switch_attr xrx200sw_vlan[] = {
575 + {
576 + .type = SWITCH_TYPE_INT,
577 + .name = "vid",
578 + .description = "VLAN ID (0-4094)",
579 + .set = xrx200sw_set_vlan_vid,
580 + .get = xrx200sw_get_vlan_vid,
581 + .max = 4094,
582 + },
583 + {
584 + .type = SWITCH_TYPE_INT,
585 + .name = "enable",
586 + .description = "Enable VLAN",
587 + .set = xrx200sw_set_vlan_enable,
588 + .get = xrx200sw_get_vlan_enable,
589 + .max = 1,
590 + },
591 +};
592 +
593 +static const struct switch_dev_ops xrx200sw_ops = {
594 + .attr_global = {
595 + .attr = xrx200sw_globals,
596 + .n_attr = ARRAY_SIZE(xrx200sw_globals),
597 + },
598 + .attr_port = {
599 + .attr = xrx200sw_port,
600 + .n_attr = ARRAY_SIZE(xrx200sw_port),
601 + },
602 + .attr_vlan = {
603 + .attr = xrx200sw_vlan,
604 + .n_attr = ARRAY_SIZE(xrx200sw_vlan),
605 + },
606 + .get_vlan_ports = xrx200sw_get_vlan_ports,
607 + .set_vlan_ports = xrx200sw_set_vlan_ports,
608 + .get_port_pvid = xrx200sw_get_port_pvid,
609 + .reset_switch = xrx200sw_reset_switch,
610 + .get_port_link = xrx200sw_get_port_link,
611 +// .get_port_stats = xrx200sw_get_port_stats, //TODO
612 +};
613 +
614 +static int xrx200sw_init(struct xrx200_hw *hw)
615 +{
616 + int netdev_num;
617 +
618 + for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++)
619 + {
620 + struct switch_dev *swdev;
621 + struct net_device *dev = hw->devs[netdev_num];
622 + struct xrx200_priv *priv = netdev_priv(dev);
623 + if (!priv->sw)
624 + continue;
625 +
626 + swdev = &hw->swdev;
627 +
628 + swdev->name = "Lantiq XRX200 Switch";
629 + swdev->vlans = XRX200_MAX_VLAN;
630 + swdev->ports = XRX200_MAX_PORT;
631 + swdev->cpu_port = 6;
632 + swdev->ops = &xrx200sw_ops;
633 +
634 + register_switch(swdev, dev);
635 + return 0; // enough switches
636 + }
637 + return 0;
638 +}
639 +
640 static int xrx200_open(struct net_device *dev)
641 {
642 struct xrx200_priv *priv = netdev_priv(dev);
643 @@ -346,7 +933,7 @@ static void xrx200_hw_receive(struct xrx
644 struct xrx200_priv *priv = netdev_priv(dev);
645 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
646 struct sk_buff *skb = ch->skb[ch->dma.desc];
647 - int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - XRX200_DMA_CRC_LEN;
648 + int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
649 unsigned long flags;
650
651 spin_lock_irqsave(&priv->hw->lock, flags);
652 @@ -924,9 +1511,9 @@ static void xrx200_hw_init(struct xrx200
653 PMAC_HD_CTL);
654 #endif
655
656 - /* enable port fetch/store dma */
657 + /* enable port fetch/store dma & VLAN Modification */
658 for (i = 0; i < 7; i++ ) {
659 - ltq_switch_w32_mask(0, 0x01, FDMA_PCTRLx(i));
660 + ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i));
661 ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
662 ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
663 }
664 @@ -1042,6 +1629,7 @@ static void xrx200_of_iface(struct xrx20
665 struct xrx200_priv *priv;
666 struct device_node *port;
667 const __be32 *wan;
668 + const __be32 *sw;
669
670 /* alloc the network device */
671 hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
672 @@ -1065,6 +1653,11 @@ static void xrx200_of_iface(struct xrx20
673 if (wan && (*wan == 1))
674 priv->wan = 1;
675
676 + /* should the switch be enabled on this interface ? */
677 + sw = of_get_property(iface, "lantiq,switch", NULL);
678 + if (sw && (*sw == 1))
679 + priv->sw = 1;
680 +
681 /* load the ports that are part of the interface */
682 for_each_child_of_node(iface, port)
683 if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
684 @@ -1138,6 +1731,8 @@ static int xrx200_probe(struct platform_
685 return -ENOENT;
686 }
687
688 + xrx200sw_init(&xrx200_hw);
689 +
690 /* set wan port mask */
691 ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
692
693 --- /dev/null
694 +++ b/drivers/net/ethernet/lantiq_xrx200_sw.h
695 @@ -0,0 +1,1328 @@
696 +/*
697 + * This program is free software; you can redistribute it and/or modify it
698 + * under the terms of the GNU General Public License version 2 as published
699 + * by the Free Software Foundation.
700 + *
701 + * This program is distributed in the hope that it will be useful,
702 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
703 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
704 + * GNU General Public License for more details.
705 + *
706 + * You should have received a copy of the GNU General Public License
707 + * along with this program; if not, write to the Free Software
708 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
709 + *
710 + * Copyright (C) 2010 Lantiq Deutschland GmbH
711 + * Copyright (C) 2013 Antonios Vamporakis <vamporakis@yahoo.com>
712 + *
713 + * VR9 switch registers extracted from 310TUJ0 switch api
714 + * WARNING mult values of 0x00 may not be correct
715 + *
716 + */
717 +
718 +enum {
719 +// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */
720 +// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */
721 +// XRX200_ETHSW_SWRES_R0, /* Register Configuration */
722 +// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */
723 +// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */
724 +// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */
725 +// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */
726 +// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */
727 +// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */
728 +// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */
729 +// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */
730 +// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */
731 +// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */
732 +// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */
733 +// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */
734 +// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */
735 +// XRX200_ETHSW_DBG_MODE, /* Debug Mode */
736 +// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */
737 +// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */
738 +// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */
739 +// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */
740 +// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */
741 +// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */
742 +// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */
743 +// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */
744 +// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */
745 +// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */
746 +// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */
747 +// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */
748 +// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */
749 +// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */
750 +// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */
751 +// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */
752 +// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */
753 +// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */
754 +// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */
755 +// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */
756 +// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */
757 +// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */
758 +// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */
759 +// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */
760 +// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */
761 +// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */
762 +// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */
763 +// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */
764 +// XRX200_ETHSW_CAP_6_APPL, /* Application table size */
765 +// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */
766 +// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */
767 +// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */
768 +// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */
769 +// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */
770 +// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */
771 +// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */
772 +// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */
773 +// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */
774 +// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */
775 +// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */
776 +// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */
777 +// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */
778 +// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */
779 +// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */
780 +// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */
781 +// XRX200_ETHSW_IER, /* Interrupt Enable Register */
782 +// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */
783 +// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */
784 +// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */
785 +// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */
786 +// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */
787 +// XRX200_ETHSW_ISR, /* Interrupt Status Register */
788 +// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */
789 +// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */
790 +// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */
791 +// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */
792 +// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */
793 +// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */
794 +// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */
795 +// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */
796 +// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */
797 +// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */
798 +// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */
799 +// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */
800 +// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */
801 +// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */
802 +// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */
803 +// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */
804 +// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */
805 +// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */
806 +// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */
807 +// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */
808 +// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */
809 +// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */
810 +// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */
811 +// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */
812 +// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */
813 +// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */
814 +// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */
815 +// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */
816 +// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */
817 +// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */
818 +// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */
819 +// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */
820 +// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */
821 +// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */
822 +// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */
823 +// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */
824 +// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */
825 +// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */
826 +// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */
827 +// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */
828 +// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */
829 +// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */
830 +// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */
831 +// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */
832 +// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */
833 +// XRX200_BM_RAM_ADDR, /* RAM Address Register */
834 +// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */
835 +// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */
836 +// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */
837 +// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
838 +// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */
839 +// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */
840 +// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */
841 +// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */
842 +// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */
843 +// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */
844 +// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */
845 +// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */
846 +// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */
847 +// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */
848 +// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */
849 +// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */
850 +// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */
851 +// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */
852 +// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */
853 +// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */
854 +// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */
855 +// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */
856 +// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */
857 +// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */
858 +// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */
859 +// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */
860 +// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */
861 +// XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */
862 +// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */
863 +// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */
864 +// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */
865 +// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */
866 +// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */
867 +// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */
868 +// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */
869 +// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */
870 +// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */
871 +// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */
872 +// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */
873 +// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */
874 +// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */
875 +// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */
876 +// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */
877 +// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */
878 +// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */
879 +// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */
880 +// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */
881 +// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */
882 +// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */
883 +// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */
884 +// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */
885 +// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
886 +// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */
887 +// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
888 +// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */
889 +// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */
890 +// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */
891 +// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */
892 +// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */
893 +// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */
894 +// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */
895 +// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */
896 +// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */
897 +// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */
898 +// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */
899 +// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */
900 +// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */
901 +// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */
902 +// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */
903 +// XRX200_BM_CISEL_PORT, /* Port Number */
904 +// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */
905 +// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */
906 +// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */
907 +// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */
908 +// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */
909 +// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */
910 +// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */
911 +// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */
912 +// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */
913 +// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */
914 +// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */
915 +// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */
916 +// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */
917 +// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */
918 +// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */
919 +// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */
920 +// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */
921 +// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */
922 +// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */
923 +// XRX200_RS_CBS_CBS, /* Committed Burst Size */
924 +// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */
925 +// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */
926 +// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */
927 +// XRX200_RS_CIR_EXP_EXP, /* Exponent */
928 +// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */
929 +// XRX200_RS_CIR_MANT_MANT, /* Mantissa */
930 + XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */
931 +// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */
932 + XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */
933 +// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */
934 + XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */
935 +// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */
936 + XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */
937 +// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */
938 + XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */
939 +// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */
940 + XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */
941 +// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */
942 + XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */
943 +// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */
944 + XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */
945 +// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */
946 + XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */
947 +// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */
948 + XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */
949 +// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */
950 + XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */
951 +// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */
952 + XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */
953 +// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */
954 + XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */
955 +// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */
956 + XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */
957 +// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */
958 +// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */
959 + XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */
960 +// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */
961 + XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */
962 + XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */
963 + XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */
964 + XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */
965 + XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
966 + XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */
967 +// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */
968 +// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */
969 +// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */
970 +// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */
971 +// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */
972 +// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */
973 +// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */
974 +// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */
975 +// XRX200_PCE_PMAP_1, /* Port Map Register 1 */
976 +// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */
977 +// XRX200_PCE_PMAP_2, /* Port Map Register 2 */
978 +// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */
979 +// XRX200_PCE_PMAP_3, /* Port Map Register 3 */
980 +// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */
981 +// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */
982 +// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */
983 + XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */
984 +// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */
985 +// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */
986 +// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */
987 +// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */
988 +// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */
989 +// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */
990 +// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */
991 +// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */
992 +// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */
993 +// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */
994 +// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */
995 +// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */
996 +// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */
997 +// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */
998 +// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */
999 +// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */
1000 +// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */
1001 +// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */
1002 +// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */
1003 +// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */
1004 +// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */
1005 +// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */
1006 +// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */
1007 +// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */
1008 +// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */
1009 +// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */
1010 +// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */
1011 +// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */
1012 +// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */
1013 +// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */
1014 +// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */
1015 +// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */
1016 +// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */
1017 +// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */
1018 +// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */
1019 +// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */
1020 +// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */
1021 +// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */
1022 +// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */
1023 +// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */
1024 +// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */
1025 +// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */
1026 +// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */
1027 +// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */
1028 +// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */
1029 +// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */
1030 +// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */
1031 +// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */
1032 +// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */
1033 +// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */
1034 +// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */
1035 +// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */
1036 +// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */
1037 +// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */
1038 +// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */
1039 +// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */
1040 +// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */
1041 +// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */
1042 +// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */
1043 +// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */
1044 +// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */
1045 +// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */
1046 +// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */
1047 +// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */
1048 +// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */
1049 +// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */
1050 +// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */
1051 +// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */
1052 +// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */
1053 +// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */
1054 +// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */
1055 +// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */
1056 +// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */
1057 +// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */
1058 +// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */
1059 +// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */
1060 +// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */
1061 +// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */
1062 +// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */
1063 +// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */
1064 +// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */
1065 +// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */
1066 +// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */
1067 +// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */
1068 +// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */
1069 +// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */
1070 +// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */
1071 +// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */
1072 +// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */
1073 +// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */
1074 +// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */
1075 +// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */
1076 +// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */
1077 +// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */
1078 +// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */
1079 +// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */
1080 +// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */
1081 +// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */
1082 +// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */
1083 +// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */
1084 +// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */
1085 +// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */
1086 +// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */
1087 +// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */
1088 +// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */
1089 +// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */
1090 +// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */
1091 +// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */
1092 +// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */
1093 +// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */
1094 +// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */
1095 +// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */
1096 +// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */
1097 +// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */
1098 +// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */
1099 +// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */
1100 + XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */
1101 +// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */
1102 +// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */
1103 +// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */
1104 +// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */
1105 +// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */
1106 +// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */
1107 +// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */
1108 +// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */
1109 +// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */
1110 +// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */
1111 +// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */
1112 +// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */
1113 +// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */
1114 +// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */
1115 +// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */
1116 +// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */
1117 +// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */
1118 +// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */
1119 +// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */
1120 +// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */
1121 +// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */
1122 +// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */
1123 +// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */
1124 +// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */
1125 +// XRX200_WOL_CTRL_PORT, /* WoL Enable */
1126 +// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */
1127 + XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */
1128 + XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */
1129 + XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */
1130 + XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */
1131 + XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */
1132 +// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */
1133 + XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */
1134 +// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */
1135 +// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */
1136 +// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */
1137 +// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */
1138 +// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */
1139 +// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */
1140 +// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */
1141 +// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */
1142 +// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */
1143 +// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */
1144 +// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */
1145 +// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */
1146 +// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */
1147 +// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */
1148 +// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */
1149 +// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */
1150 +// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */
1151 +// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */
1152 +// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */
1153 +// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */
1154 +// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */
1155 +// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */
1156 +// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */
1157 +// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */
1158 +// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */
1159 +// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */
1160 +// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */
1161 +// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */
1162 +// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */
1163 +// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */
1164 +// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */
1165 +// XRX200_MAC_TEST, /* MAC Test Register */
1166 +// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */
1167 +// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */
1168 +// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */
1169 +// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */
1170 +// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */
1171 +// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */
1172 +// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */
1173 +// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */
1174 +// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */
1175 +// XRX200_MAC_FLEN, /* MAC Frame Length Register */
1176 +// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */
1177 +// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */
1178 +// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */
1179 +// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */
1180 +// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */
1181 +// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */
1182 +// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */
1183 +// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */
1184 +// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */
1185 +// XRX200_MAC_PSTAT, /* MAC Port Status Register */
1186 +// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */
1187 + XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */
1188 + XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */
1189 + XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */
1190 +// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */
1191 +// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */
1192 +// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */
1193 +// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */
1194 + XRX200_MAC_PSTAT_LSTAT, /* Link Status */
1195 +// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */
1196 +// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */
1197 +// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */
1198 +// XRX200_MAC_PISR, /* MAC Interrupt Status Register */
1199 +// XRX200_MAC_PISR_PACT, /* PHY Active Status */
1200 +// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */
1201 +// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */
1202 +// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */
1203 +// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */
1204 +// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */
1205 +// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */
1206 +// XRX200_MAC_PISR_JAM, /* Jam Status Detected */
1207 +// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */
1208 +// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */
1209 +// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */
1210 +// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */
1211 +// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */
1212 +// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */
1213 +// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */
1214 +// XRX200_MAC_PIER_PACT, /* PHY Active Status */
1215 +// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */
1216 +// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */
1217 +// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */
1218 +// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */
1219 +// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */
1220 +// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */
1221 +// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */
1222 +// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */
1223 +// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */
1224 +// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */
1225 +// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */
1226 +// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */
1227 +// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */
1228 +// XRX200_MAC_CTRL_0, /* MAC Control Register0 */
1229 +// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */
1230 +// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */
1231 +// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */
1232 +// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */
1233 +// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */
1234 +// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */
1235 +// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */
1236 + XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */
1237 +// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */
1238 +// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */
1239 +// XRX200_MAC_CTRL_1, /* MAC Control Register1 */
1240 +// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */
1241 +// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */
1242 +// XRX200_MAC_CTRL_2, /* MAC Control Register2 */
1243 +// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */
1244 +// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */
1245 +// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */
1246 +// XRX200_MAC_CTRL_3, /* MAC Control Register3 */
1247 +// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */
1248 +// XRX200_MAC_CTRL_4, /* MAC Control Register4 */
1249 +// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */
1250 +// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */
1251 +// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */
1252 +// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */
1253 +// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */
1254 +// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */
1255 +// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */
1256 +// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */
1257 +// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */
1258 +// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */
1259 +// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */
1260 +// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */
1261 +// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */
1262 +// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */
1263 +// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */
1264 +// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */
1265 +// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */
1266 +// XRX200_MAC_TESTEN, /* MAC Test Enable Register */
1267 +// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */
1268 +// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */
1269 +// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */
1270 +// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */
1271 +// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */
1272 +// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */
1273 +// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */
1274 +// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */
1275 +// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */
1276 +// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */
1277 +// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */
1278 +// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */
1279 +// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */
1280 +// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */
1281 +// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */
1282 +// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */
1283 +// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */
1284 +// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */
1285 +// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */
1286 +// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */
1287 +// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */
1288 +// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */
1289 +// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */
1290 +// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */
1291 +// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */
1292 +// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */
1293 +// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */
1294 +// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */
1295 +// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */
1296 +// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */
1297 +// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */
1298 +// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */
1299 +// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */
1300 +// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */
1301 +// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */
1302 +// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */
1303 +// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */
1304 +// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
1305 +// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */
1306 +// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
1307 +// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */
1308 +// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */
1309 +// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */
1310 +// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */
1311 +// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */
1312 +// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */
1313 +// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */
1314 +// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */
1315 +// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */
1316 +// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */
1317 +// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */
1318 +// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */
1319 +// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */
1320 +// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */
1321 +// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */
1322 +// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */
1323 +// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */
1324 +// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */
1325 +// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */
1326 +// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */
1327 +// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */
1328 +// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */
1329 +// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */
1330 +// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */
1331 +// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */
1332 +// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */
1333 +// XRX200_SDMA_IER_BFULL, /* Buffer Full */
1334 +// XRX200_SDMA_IER_FERR, /* Frame Error */
1335 +// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */
1336 +// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */
1337 +// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */
1338 +// XRX200_SDMA_ISR_BFULL, /* Buffer Full */
1339 +// XRX200_SDMA_ISR_FERR, /* Frame Error */
1340 +// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */
1341 +// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */
1342 +// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */
1343 +// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */
1344 +// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */
1345 +// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */
1346 +// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */
1347 +// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */
1348 +// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */
1349 +// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */
1350 +// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */
1351 +// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */
1352 +// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */
1353 +// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */
1354 +// XRX200_SDMA_PCTRL_PEN, /* Port Enable */
1355 +// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */
1356 +// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */
1357 +// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */
1358 +// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */
1359 +// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */
1360 +// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */
1361 +// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */
1362 +// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
1363 +// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */
1364 +// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
1365 +};
1366 +
1367 +
1368 +struct xrx200sw_reg {
1369 + int offset;
1370 + int shift;
1371 + int size;
1372 + int mult;
1373 +} xrx200sw_reg[] = {
1374 +// offeset shift size mult
1375 +// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */
1376 +// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */
1377 +// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */
1378 +// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */
1379 +// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */
1380 +// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */
1381 +// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */
1382 +// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */
1383 +// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */
1384 +// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */
1385 +// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */
1386 +// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */
1387 +// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */
1388 +// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */
1389 +// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */
1390 +// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */
1391 +// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */
1392 +// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */
1393 +// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */
1394 +// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */
1395 +// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */
1396 +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */
1397 +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */
1398 +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */
1399 +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */
1400 +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */
1401 +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */
1402 +// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */
1403 +// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */
1404 +// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */
1405 +// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */
1406 +// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */
1407 +// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */
1408 +// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */
1409 +// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */
1410 +// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */
1411 +// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */
1412 +// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */
1413 +// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */
1414 +// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */
1415 +// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */
1416 +// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */
1417 +// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */
1418 +// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */
1419 +// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */
1420 +// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */
1421 +// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */
1422 +// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */
1423 +// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */
1424 +// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */
1425 +// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */
1426 +// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */
1427 +// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */
1428 +// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */
1429 +// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */
1430 +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */
1431 +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */
1432 +// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */
1433 +// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */
1434 +// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */
1435 +// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */
1436 +// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */
1437 +// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */
1438 +// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */
1439 +// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */
1440 +// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */
1441 +// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */
1442 +// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */
1443 +// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */
1444 +// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */
1445 +// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */
1446 +// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */
1447 +// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */
1448 +// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */
1449 +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */
1450 +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */
1451 +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */
1452 +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */
1453 +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */
1454 +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */
1455 +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */
1456 +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */
1457 +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */
1458 +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */
1459 +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */
1460 +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */
1461 +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */
1462 +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */
1463 +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */
1464 +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */
1465 +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */
1466 +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */
1467 +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */
1468 +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */
1469 +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */
1470 +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */
1471 +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */
1472 +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */
1473 +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */
1474 +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */
1475 +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */
1476 +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */
1477 +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */
1478 +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */
1479 +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */
1480 +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */
1481 +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */
1482 +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */
1483 +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */
1484 +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */
1485 +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */
1486 +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */
1487 +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */
1488 +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */
1489 +// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */
1490 +// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */
1491 +// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */
1492 +// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */
1493 +// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */
1494 +// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */
1495 +// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */
1496 +// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */
1497 +// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */
1498 +// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */
1499 +// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */
1500 +// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */
1501 +// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */
1502 +// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */
1503 +// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */
1504 +// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */
1505 +// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */
1506 +// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */
1507 +// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */
1508 +// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */
1509 +// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */
1510 +// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */
1511 +// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */
1512 +// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */
1513 +// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */
1514 +// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */
1515 +// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */
1516 +// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */
1517 +// {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */
1518 +// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */
1519 +// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */
1520 +// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */
1521 +// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */
1522 +// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */
1523 +// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */
1524 +// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */
1525 +// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */
1526 +// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */
1527 +// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */
1528 +// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */
1529 +// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */
1530 +// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */
1531 +// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */
1532 +// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */
1533 +// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */
1534 +// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */
1535 +// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */
1536 +// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */
1537 +// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */
1538 +// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */
1539 +// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */
1540 +// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */
1541 +// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
1542 +// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */
1543 +// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
1544 +// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */
1545 +// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */
1546 +// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */
1547 +// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */
1548 +// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */
1549 +// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */
1550 +// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */
1551 +// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */
1552 +// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */
1553 +// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */
1554 +// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */
1555 +// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */
1556 +// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */
1557 +// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */
1558 +// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */
1559 +// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */
1560 +// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */
1561 +// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */
1562 +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */
1563 +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */
1564 +// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */
1565 +// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */
1566 +// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */
1567 +// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */
1568 +// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */
1569 +// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */
1570 +// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */
1571 +// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */
1572 +// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */
1573 +// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */
1574 +// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */
1575 +// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */
1576 +// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */
1577 +// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */
1578 +// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */
1579 +// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */
1580 +// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */
1581 +// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */
1582 +// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */
1583 +// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */
1584 +// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */
1585 +// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */
1586 + {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */
1587 +// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */
1588 + {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */
1589 +// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */
1590 + {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */
1591 +// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */
1592 + {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */
1593 +// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */
1594 + {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */
1595 +// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */
1596 + {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */
1597 +// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */
1598 + {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */
1599 +// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */
1600 + {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */
1601 +// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */
1602 + {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */
1603 +// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */
1604 + {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */
1605 +// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */
1606 + {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */
1607 +// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */
1608 + {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */
1609 +// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */
1610 + {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */
1611 +// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */
1612 + {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */
1613 +// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */
1614 +// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */
1615 + {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */
1616 +// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */
1617 + {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */
1618 + {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */
1619 + {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */
1620 + {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */
1621 + {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */
1622 + {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */
1623 +// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */
1624 +// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */
1625 +// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */
1626 +// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */
1627 +// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */
1628 +// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */
1629 +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */
1630 +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */
1631 +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */
1632 +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */
1633 +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */
1634 +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */
1635 +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */
1636 +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */
1637 +// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */
1638 +// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */
1639 + {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */
1640 +// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */
1641 +// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */
1642 +// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */
1643 +// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */
1644 +// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */
1645 +// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */
1646 +// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */
1647 +// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */
1648 +// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */
1649 +// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */
1650 +// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */
1651 +// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */
1652 +// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */
1653 +// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */
1654 +// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */
1655 +// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */
1656 +// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */
1657 +// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */
1658 +// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */
1659 +// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */
1660 +// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */
1661 +// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */
1662 +// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */
1663 +// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */
1664 +// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */
1665 +// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */
1666 +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */
1667 +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */
1668 +// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */
1669 +// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */
1670 +// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */
1671 +// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */
1672 +// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */
1673 +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */
1674 +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */
1675 +// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */
1676 +// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */
1677 +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */
1678 +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */
1679 +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */
1680 +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */
1681 +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */
1682 +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */
1683 +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */
1684 +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */
1685 +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */
1686 +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */
1687 +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */
1688 +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */
1689 +// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */
1690 +// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */
1691 +// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */
1692 +// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */
1693 +// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */
1694 +// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */
1695 +// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */
1696 +// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */
1697 +// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */
1698 +// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */
1699 +// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */
1700 +// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */
1701 +// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */
1702 +// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */
1703 +// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */
1704 +// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */
1705 +// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */
1706 +// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */
1707 +// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */
1708 +// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */
1709 +// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */
1710 +// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */
1711 +// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */
1712 +// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */
1713 +// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */
1714 +// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */
1715 +// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */
1716 +// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */
1717 +// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */
1718 +// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */
1719 +// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */
1720 +// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */
1721 +// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */
1722 +// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */
1723 +// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */
1724 +// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */
1725 +// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */
1726 +// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */
1727 +// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */
1728 +// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */
1729 +// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */
1730 +// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */
1731 +// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */
1732 +// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */
1733 +// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */
1734 +// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */
1735 +// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */
1736 +// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */
1737 +// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */
1738 +// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */
1739 +// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */
1740 +// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */
1741 +// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */
1742 +// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */
1743 +// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */
1744 +// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */
1745 +// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */
1746 +// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */
1747 +// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */
1748 +// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */
1749 +// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */
1750 +// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */
1751 +// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */
1752 +// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */
1753 +// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */
1754 +// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */
1755 +// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */
1756 + {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */
1757 +// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */
1758 +// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */
1759 +// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */
1760 +// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */
1761 +// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */
1762 +// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */
1763 +// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */
1764 +// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */
1765 +// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */
1766 +// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */
1767 +// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */
1768 +// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */
1769 +// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */
1770 +// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */
1771 +// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */
1772 +// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */
1773 +// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */
1774 +// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */
1775 +// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */
1776 +// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */
1777 +// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */
1778 +// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */
1779 +// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */
1780 +// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */
1781 +// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */
1782 +// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */
1783 + {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */
1784 + {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */
1785 + {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */
1786 + {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */
1787 + {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */
1788 +// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */
1789 + {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */
1790 +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */
1791 +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */
1792 +// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */
1793 +// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */
1794 +// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */
1795 +// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */
1796 +// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */
1797 +// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */
1798 +// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */
1799 +// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */
1800 +// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */
1801 +// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */
1802 +// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */
1803 +// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */
1804 +// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */
1805 +// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */
1806 +// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */
1807 +// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */
1808 +// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */
1809 +// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */
1810 +// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */
1811 +// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */
1812 +// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */
1813 +// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */
1814 +// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */
1815 +// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */
1816 +// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */
1817 +// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */
1818 +// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */
1819 +// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */
1820 +// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */
1821 +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */
1822 +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */
1823 +// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */
1824 +// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */
1825 +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */
1826 +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */
1827 +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */
1828 +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */
1829 +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */
1830 +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */
1831 +// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */
1832 +// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */
1833 +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */
1834 +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */
1835 +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */
1836 +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */
1837 +// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */
1838 +// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */
1839 +// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */
1840 +// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */
1841 +// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */
1842 +// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */
1843 + {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */
1844 + {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */
1845 + {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */
1846 +// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */
1847 +// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */
1848 +// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */
1849 +// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */
1850 + {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */
1851 +// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */
1852 +// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */
1853 +// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */
1854 +// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */
1855 +// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */
1856 +// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */
1857 +// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */
1858 +// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */
1859 +// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */
1860 +// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */
1861 +// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */
1862 +// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */
1863 +// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */
1864 +// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */
1865 +// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */
1866 +// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */
1867 +// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */
1868 +// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */
1869 +// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */
1870 +// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */
1871 +// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */
1872 +// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */
1873 +// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */
1874 +// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */
1875 +// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */
1876 +// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */
1877 +// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */
1878 +// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */
1879 +// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */
1880 +// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */
1881 +// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */
1882 +// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */
1883 +// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */
1884 +// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */
1885 +// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */
1886 +// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */
1887 +// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */
1888 +// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */
1889 +// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */
1890 +// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */
1891 +// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */
1892 + {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */
1893 +// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */
1894 +// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */
1895 +// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */
1896 +// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */
1897 +// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */
1898 +// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */
1899 +// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */
1900 +// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */
1901 +// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */
1902 +// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */
1903 +// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */
1904 +// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */
1905 +// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */
1906 +// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */
1907 +// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */
1908 +// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */
1909 +// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */
1910 +// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */
1911 +// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */
1912 +// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */
1913 +// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */
1914 +// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */
1915 +// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */
1916 +// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */
1917 +// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */
1918 +// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */
1919 +// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */
1920 +// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */
1921 +// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */
1922 +// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */
1923 +// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */
1924 +// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */
1925 +// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */
1926 +// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */
1927 +// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */
1928 +// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */
1929 +// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */
1930 +// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */
1931 +// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */
1932 +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */
1933 +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */
1934 +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */
1935 +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */
1936 +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */
1937 +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */
1938 +// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */
1939 +// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */
1940 +// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */
1941 +// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */
1942 +// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */
1943 +// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */
1944 +// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */
1945 +// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */
1946 +// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */
1947 +// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */
1948 +// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */
1949 +// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */
1950 +// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */
1951 +// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */
1952 +// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */
1953 +// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */
1954 +// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */
1955 +// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */
1956 +// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */
1957 +// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */
1958 +// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */
1959 +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */
1960 +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */
1961 +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */
1962 +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */
1963 +// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */
1964 +// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */
1965 +// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */
1966 +// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */
1967 +// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */
1968 +// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */
1969 +// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */
1970 +// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */
1971 +// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */
1972 +// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */
1973 +// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */
1974 +// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */
1975 +// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */
1976 +// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */
1977 +// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */
1978 +// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */
1979 +// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */
1980 +// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */
1981 +// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */
1982 +// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */
1983 +// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */
1984 +// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */
1985 +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */
1986 +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */
1987 +// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */
1988 +// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */
1989 +// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */
1990 +// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */
1991 +// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */
1992 +// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */
1993 +// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */
1994 +// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */
1995 +// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */
1996 +// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */
1997 +// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */
1998 +// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */
1999 +// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */
2000 +// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */
2001 +// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */
2002 +// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */
2003 +// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */
2004 +// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */
2005 +// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */
2006 +// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */
2007 +// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */
2008 +// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */
2009 +// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */
2010 +// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */
2011 +// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */
2012 +// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */
2013 +// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */
2014 +// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */
2015 +// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */
2016 +// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */
2017 +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */
2018 +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */
2019 +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */
2020 +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */
2021 +};
2022 +
2023 +
OpenWrt SVN history