1 From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Aug 2012 10:27:25 +0200
4 Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
9 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
10 arch/mips/lantiq/irq.c | 2 +
11 arch/mips/mm/cache.c | 2 +
12 include/uapi/linux/atm.h | 6 +
13 net/atm/common.c | 6 +
15 7 files changed, 416 insertions(+), 1 deletion(-)
16 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
17 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
19 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_atm.h b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
21 index 0000000..bf045a9
23 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
25 +/******************************************************************************
27 +** FILE NAME : ifx_atm.h
31 +** DATE : 17 Jun 2009
33 +** DESCRIPTION : Global ATM driver header file
34 +** COPYRIGHT : Copyright (c) 2006
35 +** Infineon Technologies AG
36 +** Am Campeon 1-12, 85579 Neubiberg, Germany
38 +** This program is free software; you can redistribute it and/or modify
39 +** it under the terms of the GNU General Public License as published by
40 +** the Free Software Foundation; either version 2 of the License, or
41 +** (at your option) any later version.
44 +** $Date $Author $Comment
45 +** 07 JUL 2009 Xu Liang Init Version
46 +*******************************************************************************/
54 + \defgroup IFX_ATM UEIP Project - ATM driver module
55 + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
59 + \defgroup IFX_ATM_IOCTL IOCTL Commands
61 + \brief IOCTL Commands used by user application.
65 + \defgroup IFX_ATM_STRUCT Structures
67 + \brief Structures used by user application.
73 + \brief ATM driver header file
79 + * ####################################
81 + * ####################################
85 + \addtogroup IFX_ATM_STRUCT
94 + \struct atm_cell_ifEntry_t
95 + \brief Structure used for Cell Level MIB Counters.
97 + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
100 + __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
101 + __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
102 + __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
103 + __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
104 + __u32 ifInErrors; /*!< counter of error ingress cells */
105 + __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
106 + __u32 ifOutErrors; /*!< counter of error egress cells */
107 +} atm_cell_ifEntry_t;
110 + \struct atm_aal5_ifEntry_t
111 + \brief Structure used for AAL5 Frame Level MIB Counters.
113 + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
116 + __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
117 + __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
118 + __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
119 + __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
120 + __u32 ifInUcastPkts; /*!< counter of ingress packets */
121 + __u32 ifOutUcastPkts; /*!< counter of egress packets */
122 + __u32 ifInErrors; /*!< counter of error ingress packets */
123 + __u32 ifInDiscards; /*!< counter of dropped ingress packets */
124 + __u32 ifOutErros; /*!< counter of error egress packets */
125 + __u32 ifOutDiscards; /*!< counter of dropped egress packets */
126 +} atm_aal5_ifEntry_t;
129 + \struct atm_aal5_vcc_t
130 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
132 + This structure is a part of structure "atm_aal5_vcc_x_t".
135 + __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
136 + __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
137 + __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
141 + \struct atm_aal5_vcc_x_t
142 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
144 + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
147 + int vpi; /*!< VPI of the VCC to get MIB counters */
148 + int vci; /*!< VCI of the VCC to get MIB counters */
149 + atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
157 + * ####################################
159 + * ####################################
163 + \addtogroup IFX_ATM_IOCTL
171 + \brief ATM IOCTL Magic Number
173 +#define PPE_ATM_IOC_MAGIC 'o'
175 + \brief ATM IOCTL Command - Get Cell Level MIB Counters
177 + This command is obsolete. User can get cell level MIB from DSL API.
178 + This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
180 +#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
182 + \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
184 + Get AAL5 packet counters.
185 + This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
187 +#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
189 + \brief ATM IOCTL Command - Get Per PVC MIB Counters
191 + Get AAL5 packet counters for each PVC.
192 + This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
194 +#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
196 + \brief Total Number of ATM IOCTL Commands
198 +#define PPE_ATM_IOC_MAXNR 3
205 + * ####################################
207 + * ####################################
211 +struct port_cell_info {
212 + unsigned int port_num;
213 + unsigned int tx_link_rate[2];
221 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
223 index 0000000..698e5c3
225 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
227 +/******************************************************************************
229 +** FILE NAME : ifx_ptm.h
233 +** DATE : 17 Jun 2009
234 +** AUTHOR : Xu Liang
235 +** DESCRIPTION : Global PTM driver header file
236 +** COPYRIGHT : Copyright (c) 2006
237 +** Infineon Technologies AG
238 +** Am Campeon 1-12, 85579 Neubiberg, Germany
240 +** This program is free software; you can redistribute it and/or modify
241 +** it under the terms of the GNU General Public License as published by
242 +** the Free Software Foundation; either version 2 of the License, or
243 +** (at your option) any later version.
246 +** $Date $Author $Comment
247 +** 07 JUL 2009 Xu Liang Init Version
248 +*******************************************************************************/
256 + \defgroup IFX_PTM UEIP Project - PTM driver module
257 + \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
261 + \defgroup IFX_PTM_IOCTL IOCTL Commands
263 + \brief IOCTL Commands used by user application.
267 + \defgroup IFX_PTM_STRUCT Structures
269 + \brief Structures used by user application.
275 + \brief PTM driver header file
281 + * ####################################
283 + * ####################################
289 + * ####################################
291 + * ####################################
295 + \addtogroup IFX_PTM_IOCTL
303 + \brief PTM IOCTL Command - Get codeword MIB counters.
305 + This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
307 +#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
309 + \brief PTM IOCTL Command - Get packet MIB counters.
311 + This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
313 +#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
315 + \brief PTM IOCTL Command - Get firmware configuration (CRC).
317 + This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
319 +#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
321 + \brief PTM IOCTL Command - Set firmware configuration (CRC).
323 + This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
325 +#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
327 + \brief PTM IOCTL Command - Program priority value to TX queue mapping.
329 + This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
331 +#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
337 + \addtogroup IFX_PTM_STRUCT
346 + \typedef PTM_CW_IF_ENTRY_T
347 + \brief Wrapping of structure "ptm_cw_ifEntry_t".
350 + \struct ptm_cw_ifEntry_t
351 + \brief Structure used for CodeWord level MIB counters.
353 +typedef struct ptm_cw_ifEntry_t {
354 + uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
355 + uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
356 + uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
357 + uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
358 + uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
359 +} PTM_CW_IF_ENTRY_T;
362 + \typedef PTM_FRAME_MIB_T
363 + \brief Wrapping of structure "ptm_frame_mib_t".
366 + \struct ptm_frame_mib_t
367 + \brief Structure used for packet level MIB counters.
369 +typedef struct ptm_frame_mib_t {
370 + uint32_t RxCorrect; /*!< output, number of ingress packet */
371 + uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
372 + uint32_t RxDropped; /*!< output, number of dropped ingress packet */
373 + uint32_t TxSend; /*!< output, number of egress packet */
377 + \typedef IFX_PTM_CFG_T
378 + \brief Wrapping of structure "ptm_cfg_t".
382 + \brief Structure used for ETH/TC CRC configuration.
384 +typedef struct ptm_cfg_t {
385 + uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
386 + uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
387 + uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
388 + uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
389 + uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
390 + uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
391 + uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
395 + \typedef IFX_PTM_PRIO_Q_MAP_T
396 + \brief Wrapping of structure "ppe_prio_q_map".
399 + \struct ppe_prio_q_map
400 + \brief Structure used for Priority Value to TX Queue mapping.
402 +typedef struct ppe_prio_q_map {
405 + int vpi; // ignored in eth interface
406 + int vci; // ignored in eth interface
407 +} IFX_PTM_PRIO_Q_MAP_T;
414 + * ####################################
416 + * ####################################
420 +struct port_cell_info {
421 + unsigned int port_num;
422 + unsigned int tx_link_rate[2];
430 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
431 index 85685e1..6b94cc7 100644
432 --- a/arch/mips/lantiq/irq.c
433 +++ b/arch/mips/lantiq/irq.c
435 #include <linux/of_platform.h>
436 #include <linux/of_address.h>
437 #include <linux/of_irq.h>
438 +#include <linux/module.h>
440 #include <asm/bootinfo.h>
441 #include <asm/irq_cpu.h>
442 @@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
443 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
444 ltq_icu_w32(im, BIT(offset), isr);
446 +EXPORT_SYMBOL(ltq_mask_and_ack_irq);
448 static void ltq_ack_irq(struct irq_data *d)
450 diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
451 index fde7e56..e5bd72f 100644
452 --- a/arch/mips/mm/cache.c
453 +++ b/arch/mips/mm/cache.c
454 @@ -57,6 +57,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
455 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
457 EXPORT_SYMBOL(_dma_cache_wback_inv);
458 +EXPORT_SYMBOL(_dma_cache_wback);
459 +EXPORT_SYMBOL(_dma_cache_inv);
461 #endif /* CONFIG_DMA_NONCOHERENT */
463 diff --git a/include/uapi/linux/atm.h b/include/uapi/linux/atm.h
464 index 88399db..78c8bbc 100644
465 --- a/include/uapi/linux/atm.h
466 +++ b/include/uapi/linux/atm.h
469 #define ATM_ANYCLASS 5 /* compatible with everything */
471 +#define ATM_VBR_NRT ATM_VBR
472 +#define ATM_VBR_RT 6
473 +#define ATM_UBR_PLUS 7
476 #define ATM_MAX_PCR -1 /* maximum available PCR */
480 unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
481 int max_pcr; /* maximum PCR in cells per second */
482 diff --git a/net/atm/common.c b/net/atm/common.c
483 index 7b49100..d2af929 100644
484 --- a/net/atm/common.c
485 +++ b/net/atm/common.c
486 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct sock *sk)
487 write_unlock_irq(&vcc_sklist_lock);
490 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
491 +EXPORT_SYMBOL(ifx_atm_alloc_tx);
493 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
496 struct sock *sk = sk_atm(vcc);
498 + if (ifx_atm_alloc_tx != NULL)
499 + return ifx_atm_alloc_tx(vcc, size);
501 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
502 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
503 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
504 diff --git a/net/atm/proc.c b/net/atm/proc.c
505 index bbb6461..ecb584a 100644
508 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
509 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
511 static const char *const class_name[] = {
512 - "off", "UBR", "CBR", "VBR", "ABR"};
513 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
514 static const char *const aal_name[] = {
515 "---", "1", "2", "3/4", /* 0- 3 */
516 "???", "5", "???", "???", /* 4- 7 */