1 From 222ee25fab35b3c3a4c63903b6af4eb0d0556750 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 10 Aug 2011 14:57:04 +0200
4 Subject: [PATCH 05/73] MIPS: lantiq: reorganize xway code
6 Inside the folder arch/mips/lantiq/xway, there were alot of small files with
7 lots of duplicated code. This patch adds a wrapper function for inserting and
8 requesting resources and unifies the small files into one bigger file.
10 This patch makes the xway code consistent with the falcon support added later
13 Signed-off-by: John Crispin <blogic@openwrt.org>
15 arch/mips/include/asm/mach-lantiq/lantiq.h | 14 +---
16 .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 14 ++++
17 arch/mips/lantiq/clk.c | 25 +------
18 arch/mips/lantiq/devices.c | 30 ++------
19 arch/mips/lantiq/devices.h | 4 +
20 arch/mips/lantiq/prom.c | 51 +++++++++++--
21 arch/mips/lantiq/prom.h | 4 +
22 arch/mips/lantiq/xway/Makefile | 6 +-
23 arch/mips/lantiq/xway/devices.c | 42 ++---------
24 arch/mips/lantiq/xway/dma.c | 21 +----
25 arch/mips/lantiq/xway/ebu.c | 52 -------------
26 arch/mips/lantiq/xway/pmu.c | 69 -----------------
27 arch/mips/lantiq/xway/prom-ase.c | 9 ++
28 arch/mips/lantiq/xway/prom-xway.c | 10 +++
29 arch/mips/lantiq/xway/reset.c | 21 +----
30 arch/mips/lantiq/xway/setup-ase.c | 19 -----
31 arch/mips/lantiq/xway/setup-xway.c | 20 -----
32 arch/mips/lantiq/xway/sysctrl.c | 78 ++++++++++++++++++++
33 drivers/watchdog/lantiq_wdt.c | 2 +-
34 19 files changed, 199 insertions(+), 292 deletions(-)
35 delete mode 100644 arch/mips/lantiq/xway/ebu.c
36 delete mode 100644 arch/mips/lantiq/xway/pmu.c
37 delete mode 100644 arch/mips/lantiq/xway/setup-ase.c
38 delete mode 100644 arch/mips/lantiq/xway/setup-xway.c
39 create mode 100644 arch/mips/lantiq/xway/sysctrl.c
41 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
42 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
46 #include <linux/irq.h>
47 +#include <linux/ioport.h>
49 /* generic reg access functions */
50 #define ltq_r32(reg) __raw_readl(reg)
52 #define ltq_r8(reg) __raw_readb(reg)
53 #define ltq_w8(val, reg) __raw_writeb(val, reg)
55 -/* register access macros for EBU and CGU */
56 -#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
57 -#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
58 -#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
59 -#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
61 -extern __iomem void *ltq_ebu_membase;
62 -extern __iomem void *ltq_cgu_membase;
64 extern unsigned int ltq_get_cpu_ver(void);
65 extern unsigned int ltq_get_soc_type(void);
67 @@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_da
69 /* find out what caused the last cpu reset */
70 extern int ltq_reset_cause(void);
71 -#define LTQ_RST_CAUSE_WDTRST 0x20
73 +/* helper for requesting and remapping resources */
74 +extern void __iomem *ltq_remap_resource(struct resource *res);
76 #define IOPORT_RESOURCE_START 0x10000000
77 #define IOPORT_RESOURCE_END 0xffffffff
78 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
79 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
81 #define LTQ_CGU_BASE_ADDR 0x1F103000
82 #define LTQ_CGU_SIZE 0x1000
84 +#define CGU_EPHY 0x10
86 /* ICU - interrupt control unit */
87 #define LTQ_ICU_BASE_ADDR 0x1F880200
88 #define LTQ_ICU_SIZE 0x100
90 #define LTQ_WDT_BASE_ADDR 0x1F8803F0
91 #define LTQ_WDT_SIZE 0x10
93 +#define LTQ_RST_CAUSE_WDTRST 0x20
95 /* STP - serial to parallel conversion unit */
96 #define LTQ_STP_BASE_ADDR 0x1E100BB0
97 #define LTQ_STP_SIZE 0x40
99 #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
100 #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
102 +/* register access macros for EBU and CGU */
103 +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y))
104 +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x))
105 +#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y))
106 +#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x))
108 +extern __iomem void *ltq_ebu_membase;
109 +extern __iomem void *ltq_cgu_membase;
111 /* request a non-gpio and set the PIO config */
112 extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
113 unsigned int alt1, unsigned int dir, const char *name);
114 extern void ltq_pmu_enable(unsigned int module);
115 extern void ltq_pmu_disable(unsigned int module);
116 +extern void ltq_cgu_enable(unsigned int clk);
118 static inline int ltq_is_ar9(void)
120 --- a/arch/mips/lantiq/clk.c
121 +++ b/arch/mips/lantiq/clk.c
123 #include <lantiq_soc.h>
130 @@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = {
134 -static struct resource ltq_cgu_resource = {
136 - .start = LTQ_CGU_BASE_ADDR,
137 - .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
138 - .flags = IORESOURCE_MEM,
141 -/* remapped clock register range */
142 -void __iomem *ltq_cgu_membase;
146 cpu_clk = cpu_clk_generic;
147 @@ -133,21 +124,11 @@ void __init plat_time_init(void)
151 - if (insert_resource(&iomem_resource, <q_cgu_resource) < 0)
152 - panic("Failed to insert cgu memory\n");
155 - if (request_mem_region(ltq_cgu_resource.start,
156 - resource_size(<q_cgu_resource), "cgu") < 0)
157 - panic("Failed to request cgu memory\n");
159 - ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
160 - resource_size(<q_cgu_resource));
161 - if (!ltq_cgu_membase) {
162 - pr_err("Failed to remap cgu memory\n");
165 clk = clk_get(0, "cpu");
166 mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
167 write_c0_compare(read_c0_count());
168 + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
171 --- a/arch/mips/lantiq/devices.c
172 +++ b/arch/mips/lantiq/devices.c
177 -static struct resource ltq_nor_resource = {
179 - .start = LTQ_FLASH_START,
180 - .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
181 - .flags = IORESOURCE_MEM,
183 +static struct resource ltq_nor_resource =
184 + MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX);
186 static struct platform_device ltq_nor = {
188 @@ -47,12 +43,8 @@ void __init ltq_register_nor(struct phys
192 -static struct resource ltq_wdt_resource = {
193 - .name = "watchdog",
194 - .start = LTQ_WDT_BASE_ADDR,
195 - .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
196 - .flags = IORESOURCE_MEM,
198 +static struct resource ltq_wdt_resource =
199 + MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE);
201 void __init ltq_register_wdt(void)
203 @@ -61,24 +53,14 @@ void __init ltq_register_wdt(void)
206 static struct resource ltq_asc0_resources[] = {
209 - .start = LTQ_ASC0_BASE_ADDR,
210 - .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
211 - .flags = IORESOURCE_MEM,
213 + MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE),
214 IRQ_RES(tx, LTQ_ASC_TIR(0)),
215 IRQ_RES(rx, LTQ_ASC_RIR(0)),
216 IRQ_RES(err, LTQ_ASC_EIR(0)),
219 static struct resource ltq_asc1_resources[] = {
222 - .start = LTQ_ASC1_BASE_ADDR,
223 - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
224 - .flags = IORESOURCE_MEM,
226 + MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
227 IRQ_RES(tx, LTQ_ASC_TIR(1)),
228 IRQ_RES(rx, LTQ_ASC_RIR(1)),
229 IRQ_RES(err, LTQ_ASC_EIR(1)),
230 --- a/arch/mips/lantiq/devices.h
231 +++ b/arch/mips/lantiq/devices.h
234 #define IRQ_RES(resname, irq) \
235 {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
236 +#define MEM_RES(resname, adr_start, adr_size) \
237 + { .name = resname, .flags = IORESOURCE_MEM, \
238 + .start = ((adr_start) & ~KSEG1), \
239 + .end = ((adr_start + adr_size - 1) & ~KSEG1) }
241 extern void ltq_register_nor(struct physmap_flash_data *data);
242 extern void ltq_register_wdt(void);
243 --- a/arch/mips/lantiq/prom.c
244 +++ b/arch/mips/lantiq/prom.c
249 +/* access to the ebu needs to be locked between different drivers */
250 +DEFINE_SPINLOCK(ebu_lock);
251 +EXPORT_SYMBOL_GPL(ebu_lock);
253 static struct ltq_soc_info soc_info;
255 unsigned int ltq_get_cpu_ver(void)
256 @@ -55,16 +59,51 @@ static void __init prom_init_cmdline(voi
260 -void __init prom_init(void)
261 +void __iomem *ltq_remap_resource(struct resource *res)
264 + __iomem void *ret = NULL;
265 + struct resource *lookup = lookup_resource(&iomem_resource, res->start);
267 + if (lookup && strcmp(lookup->name, res->name)) {
268 + pr_err("conflicting memory range %s\n", res->name);
272 + if (insert_resource(&iomem_resource, res) < 0) {
273 + pr_err("Failed to insert %s memory\n", res->name);
277 + if (request_mem_region(res->start,
278 + resource_size(res), res->name) < 0) {
279 + pr_err("Failed to request %s memory\n", res->name);
283 + ret = ioremap_nocache(res->start, resource_size(res));
287 + pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n",
288 + res->start, res->end, res->name);
292 + panic("Failed to remap %s memory\n", res->name);
293 + release_mem_region(res->start, resource_size(res));
296 + release_resource(res);
299 +EXPORT_SYMBOL(ltq_remap_resource);
301 +void __init prom_init(void)
303 ltq_soc_detect(&soc_info);
305 - clk = clk_get(0, "cpu");
306 - snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
307 - soc_info.name, soc_info.rev);
309 + snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
310 + soc_info.name, soc_info.rev_type);
311 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
312 pr_info("SoC: %s\n", soc_info.sys_type);
314 --- a/arch/mips/lantiq/prom.h
315 +++ b/arch/mips/lantiq/prom.h
317 #ifndef _LTQ_PROM_H__
318 #define _LTQ_PROM_H__
320 +#define LTQ_SYS_REV_LEN 0x10
321 #define LTQ_SYS_TYPE_LEN 0x100
323 struct ltq_soc_info {
326 + unsigned char rev_type[LTQ_SYS_REV_LEN];
328 unsigned int partnum;
330 unsigned char sys_type[LTQ_SYS_TYPE_LEN];
333 extern void ltq_soc_detect(struct ltq_soc_info *i);
334 +extern void ltq_soc_init(void);
335 extern void ltq_soc_setup(void);
338 --- a/arch/mips/lantiq/xway/Makefile
339 +++ b/arch/mips/lantiq/xway/Makefile
341 -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
342 +obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
344 -obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
345 -obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
346 +obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
347 +obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
349 obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
350 obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
351 --- a/arch/mips/lantiq/xway/devices.c
352 +++ b/arch/mips/lantiq/xway/devices.c
356 static struct resource ltq_gpio_resource[] = {
359 - .start = LTQ_GPIO0_BASE_ADDR,
360 - .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
361 - .flags = IORESOURCE_MEM,
364 - .start = LTQ_GPIO1_BASE_ADDR,
365 - .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
366 - .flags = IORESOURCE_MEM,
369 - .start = LTQ_GPIO2_BASE_ADDR,
370 - .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
371 - .flags = IORESOURCE_MEM,
373 + MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
374 + MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
375 + MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
378 void __init ltq_register_gpio(void)
379 @@ -64,12 +51,8 @@ void __init ltq_register_gpio(void)
382 /* serial to parallel conversion */
383 -static struct resource ltq_stp_resource = {
385 - .start = LTQ_STP_BASE_ADDR,
386 - .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
387 - .flags = IORESOURCE_MEM,
389 +static struct resource ltq_stp_resource =
390 + MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE);
392 void __init ltq_register_gpio_stp(void)
394 @@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void)
396 /* asc ports - amazon se has its own serial mapping */
397 static struct resource ltq_ase_asc_resources[] = {
400 - .start = LTQ_ASC1_BASE_ADDR,
401 - .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
402 - .flags = IORESOURCE_MEM,
404 + MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
405 IRQ_RES(tx, LTQ_ASC_ASE_TIR),
406 IRQ_RES(rx, LTQ_ASC_ASE_RIR),
407 IRQ_RES(err, LTQ_ASC_ASE_EIR),
408 @@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void)
412 -static struct resource ltq_etop_resources = {
414 - .start = LTQ_ETOP_BASE_ADDR,
415 - .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
416 - .flags = IORESOURCE_MEM,
418 +static struct resource ltq_etop_resources =
419 + MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
421 static struct platform_device ltq_etop = {
423 --- a/arch/mips/lantiq/xway/dma.c
424 +++ b/arch/mips/lantiq/xway/dma.c
426 #include <lantiq_soc.h>
427 #include <xway_dma.h>
429 +#include "../devices.h"
431 #define LTQ_DMA_CTRL 0x10
432 #define LTQ_DMA_CPOLL 0x14
433 #define LTQ_DMA_CS 0x18
435 #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
436 ltq_dma_membase + (z))
438 -static struct resource ltq_dma_resource = {
440 - .start = LTQ_DMA_BASE_ADDR,
441 - .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
442 - .flags = IORESOURCE_MEM,
444 +static struct resource ltq_dma_resource =
445 + MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE);
447 static void __iomem *ltq_dma_membase;
449 @@ -220,17 +218,8 @@ ltq_dma_init(void)
453 - /* insert and request the memory region */
454 - if (insert_resource(&iomem_resource, <q_dma_resource) < 0)
455 - panic("Failed to insert dma memory\n");
457 - if (request_mem_region(ltq_dma_resource.start,
458 - resource_size(<q_dma_resource), "dma") < 0)
459 - panic("Failed to request dma memory\n");
461 /* remap dma register range */
462 - ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
463 - resource_size(<q_dma_resource));
464 + ltq_dma_membase = ltq_remap_resource(<q_dma_resource);
465 if (!ltq_dma_membase)
466 panic("Failed to remap dma memory\n");
468 --- a/arch/mips/lantiq/xway/ebu.c
472 - * This program is free software; you can redistribute it and/or modify it
473 - * under the terms of the GNU General Public License version 2 as published
474 - * by the Free Software Foundation.
476 - * EBU - the external bus unit attaches PCI, NOR and NAND
478 - * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
481 -#include <linux/kernel.h>
482 -#include <linux/module.h>
483 -#include <linux/ioport.h>
485 -#include <lantiq_soc.h>
487 -/* all access to the ebu must be locked */
488 -DEFINE_SPINLOCK(ebu_lock);
489 -EXPORT_SYMBOL_GPL(ebu_lock);
491 -static struct resource ltq_ebu_resource = {
493 - .start = LTQ_EBU_BASE_ADDR,
494 - .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
495 - .flags = IORESOURCE_MEM,
498 -/* remapped base addr of the clock unit and external bus unit */
499 -void __iomem *ltq_ebu_membase;
501 -static int __init lantiq_ebu_init(void)
503 - /* insert and request the memory region */
504 - if (insert_resource(&iomem_resource, <q_ebu_resource) < 0)
505 - panic("Failed to insert ebu memory\n");
507 - if (request_mem_region(ltq_ebu_resource.start,
508 - resource_size(<q_ebu_resource), "ebu") < 0)
509 - panic("Failed to request ebu memory\n");
511 - /* remap ebu register range */
512 - ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
513 - resource_size(<q_ebu_resource));
514 - if (!ltq_ebu_membase)
515 - panic("Failed to remap ebu memory\n");
517 - /* make sure to unprotect the memory region where flash is located */
518 - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
522 -postcore_initcall(lantiq_ebu_init);
523 --- a/arch/mips/lantiq/xway/pmu.c
527 - * This program is free software; you can redistribute it and/or modify it
528 - * under the terms of the GNU General Public License version 2 as published
529 - * by the Free Software Foundation.
531 - * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
534 -#include <linux/kernel.h>
535 -#include <linux/module.h>
536 -#include <linux/ioport.h>
538 -#include <lantiq_soc.h>
540 -/* PMU - the power management unit allows us to turn part of the core
544 -/* the enable / disable registers */
545 -#define LTQ_PMU_PWDCR 0x1C
546 -#define LTQ_PMU_PWDSR 0x20
548 -#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
549 -#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
551 -static struct resource ltq_pmu_resource = {
553 - .start = LTQ_PMU_BASE_ADDR,
554 - .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
555 - .flags = IORESOURCE_MEM,
558 -static void __iomem *ltq_pmu_membase;
560 -void ltq_pmu_enable(unsigned int module)
564 - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
565 - do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
568 - panic("activating PMU module failed!\n");
570 -EXPORT_SYMBOL(ltq_pmu_enable);
572 -void ltq_pmu_disable(unsigned int module)
574 - ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
576 -EXPORT_SYMBOL(ltq_pmu_disable);
578 -int __init ltq_pmu_init(void)
580 - if (insert_resource(&iomem_resource, <q_pmu_resource) < 0)
581 - panic("Failed to insert pmu memory\n");
583 - if (request_mem_region(ltq_pmu_resource.start,
584 - resource_size(<q_pmu_resource), "pmu") < 0)
585 - panic("Failed to request pmu memory\n");
587 - ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
588 - resource_size(<q_pmu_resource));
589 - if (!ltq_pmu_membase)
590 - panic("Failed to remap pmu memory\n");
594 -core_initcall(ltq_pmu_init);
595 --- a/arch/mips/lantiq/xway/prom-ase.c
596 +++ b/arch/mips/lantiq/xway/prom-ase.c
599 #include <lantiq_soc.h>
601 +#include "devices.h"
604 #define SOC_AMAZON_SE "Amazon_SE"
605 @@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_so
607 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
608 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
609 + sprintf(i->rev_type, "1.%d", i->rev);
610 switch (i->partnum) {
611 case SOC_ID_AMAZON_SE:
612 i->name = SOC_AMAZON_SE;
613 @@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_so
618 +void __init ltq_soc_setup(void)
620 + ltq_register_ase_asc();
621 + ltq_register_gpio();
622 + ltq_register_wdt();
624 --- a/arch/mips/lantiq/xway/prom-xway.c
625 +++ b/arch/mips/lantiq/xway/prom-xway.c
628 #include <lantiq_soc.h>
630 +#include "devices.h"
633 #define SOC_DANUBE "Danube"
634 @@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_so
636 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
637 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
638 + sprintf(i->rev_type, "1.%d", i->rev);
639 switch (i->partnum) {
642 @@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_so
647 +void __init ltq_soc_setup(void)
649 + ltq_register_asc(0);
650 + ltq_register_asc(1);
651 + ltq_register_gpio();
652 + ltq_register_wdt();
654 --- a/arch/mips/lantiq/xway/reset.c
655 +++ b/arch/mips/lantiq/xway/reset.c
658 #include <lantiq_soc.h>
660 +#include "../devices.h"
662 #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y))
663 #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x))
666 #define LTQ_RCU_RST_STAT 0x0014
667 #define LTQ_RCU_STAT_SHIFT 26
669 -static struct resource ltq_rcu_resource = {
671 - .start = LTQ_RCU_BASE_ADDR,
672 - .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
673 - .flags = IORESOURCE_MEM,
675 +static struct resource ltq_rcu_resource =
676 + MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
678 /* remapped base addr of the reset control unit */
679 static void __iomem *ltq_rcu_membase;
680 @@ -67,17 +65,8 @@ static void ltq_machine_power_off(void)
682 static int __init mips_reboot_setup(void)
684 - /* insert and request the memory region */
685 - if (insert_resource(&iomem_resource, <q_rcu_resource) < 0)
686 - panic("Failed to insert rcu memory\n");
688 - if (request_mem_region(ltq_rcu_resource.start,
689 - resource_size(<q_rcu_resource), "rcu") < 0)
690 - panic("Failed to request rcu memory\n");
692 /* remap rcu register range */
693 - ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
694 - resource_size(<q_rcu_resource));
695 + ltq_rcu_membase = ltq_remap_resource(<q_rcu_resource);
696 if (!ltq_rcu_membase)
697 panic("Failed to remap rcu memory\n");
699 --- a/arch/mips/lantiq/xway/setup-ase.c
703 - * This program is free software; you can redistribute it and/or modify it
704 - * under the terms of the GNU General Public License version 2 as published
705 - * by the Free Software Foundation.
707 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
710 -#include <lantiq_soc.h>
712 -#include "../prom.h"
713 -#include "devices.h"
715 -void __init ltq_soc_setup(void)
717 - ltq_register_ase_asc();
718 - ltq_register_gpio();
719 - ltq_register_wdt();
721 --- a/arch/mips/lantiq/xway/setup-xway.c
725 - * This program is free software; you can redistribute it and/or modify it
726 - * under the terms of the GNU General Public License version 2 as published
727 - * by the Free Software Foundation.
729 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
732 -#include <lantiq_soc.h>
734 -#include "../prom.h"
735 -#include "devices.h"
737 -void __init ltq_soc_setup(void)
739 - ltq_register_asc(0);
740 - ltq_register_asc(1);
741 - ltq_register_gpio();
742 - ltq_register_wdt();
745 +++ b/arch/mips/lantiq/xway/sysctrl.c
748 + * This program is free software; you can redistribute it and/or modify it
749 + * under the terms of the GNU General Public License version 2 as published
750 + * by the Free Software Foundation.
752 + * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
755 +#include <linux/ioport.h>
756 +#include <linux/export.h>
758 +#include <lantiq_soc.h>
760 +#include "../devices.h"
762 +/* clock control register */
763 +#define LTQ_CGU_IFCCR 0x0018
765 +/* the enable / disable registers */
766 +#define LTQ_PMU_PWDCR 0x1C
767 +#define LTQ_PMU_PWDSR 0x20
769 +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
770 +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
772 +static struct resource ltq_cgu_resource =
773 + MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE);
775 +static struct resource ltq_pmu_resource =
776 + MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE);
778 +static struct resource ltq_ebu_resource =
779 + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
781 +void __iomem *ltq_cgu_membase;
782 +void __iomem *ltq_ebu_membase;
783 +static void __iomem *ltq_pmu_membase;
785 +void ltq_cgu_enable(unsigned int clk)
787 + ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
790 +void ltq_pmu_enable(unsigned int module)
794 + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
795 + do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
798 + panic("activating PMU module failed!\n");
800 +EXPORT_SYMBOL(ltq_pmu_enable);
802 +void ltq_pmu_disable(unsigned int module)
804 + ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
806 +EXPORT_SYMBOL(ltq_pmu_disable);
808 +void __init ltq_soc_init(void)
810 + ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource);
811 + if (!ltq_pmu_membase)
812 + panic("Failed to remap pmu memory\n");
814 + ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource);
815 + if (!ltq_cgu_membase)
816 + panic("Failed to remap cgu memory\n");
818 + ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource);
819 + if (!ltq_ebu_membase)
820 + panic("Failed to remap ebu memory\n");
822 + /* make sure to unprotect the memory region where flash is located */
823 + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
825 --- a/drivers/watchdog/lantiq_wdt.c
826 +++ b/drivers/watchdog/lantiq_wdt.c
828 #include <linux/clk.h>
829 #include <linux/io.h>
832 +#include <lantiq_soc.h>
834 /* Section 3.4 of the datasheet
835 * The password sequence protects the WDT control register from unintended