1 From 6c2374c768e0eacba197e242e8793d93846dc762 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 11 Apr 2012 18:43:50 +0200
4 Subject: [PATCH 70/73] MIPS: lantiq: fix dwc_otg usb for ase
6 changed irq number and pmu settings. little bit of fiddling to get the now variable
9 Signed-off-by: Conor O'Gorman <i@conorogorman.net>
11 .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 1 +
12 drivers/usb/dwc_otg/dwc_otg_driver.c | 3 +++
13 drivers/usb/dwc_otg/dwc_otg_ifx.c | 5 ++++-
14 3 files changed, 8 insertions(+), 1 deletions(-)
16 diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
17 index b7f10e6..d9c892b 100644
18 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
19 +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
22 #define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
23 #define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
24 +#define LTQ_USB_ASE_INT (INT_NUM_IM0_IRL0 + 31)
25 #define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
27 #define MIPS_CPU_TIMER_IRQ 7
28 diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.c b/drivers/usb/dwc_otg/dwc_otg_driver.c
29 index 1b0daab..5c64ebb 100644
30 --- a/drivers/usb/dwc_otg/dwc_otg_driver.c
31 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
32 @@ -860,6 +860,9 @@ static int __init dwc_otg_init(void)
34 printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION);
37 + dwc_irq = LTQ_USB_ASE_INT;
40 retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq);
42 diff --git a/drivers/usb/dwc_otg/dwc_otg_ifx.c b/drivers/usb/dwc_otg/dwc_otg_ifx.c
43 index 0a4c209..e45da85 100644
44 --- a/drivers/usb/dwc_otg/dwc_otg_ifx.c
45 +++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
46 @@ -61,7 +61,10 @@ void dwc_otg_power_on (void)
48 writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
50 - writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
52 + writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
54 + writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
56 writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
57 writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);