1 From 8cbac4b30bed1552503b95bc0ac6276e3cdda9d8 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 30 Nov 2012 21:08:49 +0100
4 Subject: [PATCH 103/123] MIPS: lantiq: adds static clock for PP32
6 The Lantiq DSL SoCs have an internal networking processor. Add code to read
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/include/asm/mach-lantiq/lantiq.h | 1 +
12 arch/mips/lantiq/clk.c | 12 ++++++--
13 arch/mips/lantiq/clk.h | 7 ++++-
14 arch/mips/lantiq/falcon/sysctrl.c | 4 +--
15 arch/mips/lantiq/xway/clk.c | 43 ++++++++++++++++++++++++++++
16 arch/mips/lantiq/xway/sysctrl.c | 12 ++++----
17 6 files changed, 69 insertions(+), 10 deletions(-)
19 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
20 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
21 @@ -41,6 +41,7 @@ extern void clk_deactivate(struct clk *c
22 extern struct clk *clk_get_cpu(void);
23 extern struct clk *clk_get_fpi(void);
24 extern struct clk *clk_get_io(void);
25 +extern struct clk *clk_get_ppe(void);
27 /* find out what bootsource we have */
28 extern unsigned char ltq_boot_select(void);
29 --- a/arch/mips/lantiq/clk.c
30 +++ b/arch/mips/lantiq/clk.c
34 /* lantiq socs have 3 static clocks */
35 -static struct clk cpu_clk_generic[3];
36 +static struct clk cpu_clk_generic[4];
38 -void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
39 +void clkdev_add_static(unsigned long cpu, unsigned long fpi,
40 + unsigned long io, unsigned long ppe)
42 cpu_clk_generic[0].rate = cpu;
43 cpu_clk_generic[1].rate = fpi;
44 cpu_clk_generic[2].rate = io;
45 + cpu_clk_generic[3].rate = ppe;
48 struct clk *clk_get_cpu(void)
49 @@ -51,6 +53,12 @@ struct clk *clk_get_io(void)
50 return &cpu_clk_generic[2];
53 +struct clk *clk_get_ppe(void)
55 + return &cpu_clk_generic[3];
57 +EXPORT_SYMBOL_GPL(clk_get_ppe);
59 static inline int clk_good(struct clk *clk)
61 return clk && !IS_ERR(clk);
62 --- a/arch/mips/lantiq/clk.h
63 +++ b/arch/mips/lantiq/clk.h
65 #define CLOCK_167M 166666667
66 #define CLOCK_196_608M 196608000
67 #define CLOCK_200M 200000000
68 +#define CLOCK_222M 222000000
69 +#define CLOCK_240M 240000000
70 #define CLOCK_250M 250000000
71 #define CLOCK_266M 266666666
72 #define CLOCK_300M 300000000
73 #define CLOCK_333M 333333333
74 #define CLOCK_393M 393215332
75 #define CLOCK_400M 400000000
76 +#define CLOCK_450M 450000000
77 #define CLOCK_500M 500000000
78 #define CLOCK_600M 600000000
80 @@ -64,16 +67,18 @@ struct clk {
83 extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
85 + unsigned long io, unsigned long ppe);
87 extern unsigned long ltq_danube_cpu_hz(void);
88 extern unsigned long ltq_danube_fpi_hz(void);
89 +extern unsigned long ltq_danube_pp32_hz(void);
91 extern unsigned long ltq_ar9_cpu_hz(void);
92 extern unsigned long ltq_ar9_fpi_hz(void);
94 extern unsigned long ltq_vr9_cpu_hz(void);
95 extern unsigned long ltq_vr9_fpi_hz(void);
96 +extern unsigned long ltq_vr9_pp32_hz(void);
98 extern unsigned long ltq_svip_cpu_hz(void);
99 extern unsigned long ltq_svip_fpi_hz(void);
100 --- a/arch/mips/lantiq/falcon/sysctrl.c
101 +++ b/arch/mips/lantiq/falcon/sysctrl.c
102 @@ -241,9 +241,9 @@ void __init ltq_soc_init(void)
104 /* get our 3 static rates for cpu, fpi and io clocks */
105 if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
106 - clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
107 + clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M, 0);
109 - clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
110 + clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M, 0);
112 /* add our clock domains */
113 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
114 --- a/arch/mips/lantiq/xway/clk.c
115 +++ b/arch/mips/lantiq/xway/clk.c
116 @@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
120 +unsigned long ltq_danube_pp32_hz(void)
122 + unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
143 unsigned long ltq_ar9_sys_hz(void)
145 if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
146 @@ -147,5 +170,25 @@ unsigned long ltq_vr9_fpi_hz(void)
153 +unsigned long ltq_vr9_pp32_hz(void)
155 + unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
172 --- a/arch/mips/lantiq/xway/sysctrl.c
173 +++ b/arch/mips/lantiq/xway/sysctrl.c
174 @@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
176 if (of_machine_is_compatible("lantiq,ase")) {
177 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
178 - clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
179 + clkdev_add_static(CLOCK_266M, CLOCK_133M,
180 + CLOCK_133M, CLOCK_266M);
182 - clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
183 + clkdev_add_static(CLOCK_133M, CLOCK_133M,
184 + CLOCK_133M, CLOCK_133M);
185 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
186 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
187 } else if (of_machine_is_compatible("lantiq,vr9")) {
188 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
190 + ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
191 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
192 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
193 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
194 @@ -377,10 +379,10 @@ void __init ltq_soc_init(void)
195 clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
196 } else if (of_machine_is_compatible("lantiq,ar9")) {
197 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
199 + ltq_ar9_fpi_hz(), CLOCK_250M);
200 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
202 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
203 - ltq_danube_fpi_hz());
204 + ltq_danube_fpi_hz(), ltq_danube_pp32_hz());