1 From c7b0e371e1c5e2f6258decfeb948e0dda7109afc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 24 Oct 2012 19:50:30 +0200
4 Subject: [PATCH 116/123] NET: MIPS: lantiq: update etop driver for devicetree
7 drivers/net/ethernet/lantiq_etop.c | 470 +++++++++++++++++++++++++-----------
8 1 file changed, 333 insertions(+), 137 deletions(-)
10 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
11 index 003c5bc..dc5457a 100644
12 --- a/drivers/net/ethernet/lantiq_etop.c
13 +++ b/drivers/net/ethernet/lantiq_etop.c
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
18 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
19 + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
22 #include <linux/kernel.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/module.h>
27 +#include <linux/clk.h>
28 +#include <linux/of_net.h>
29 +#include <linux/of_irq.h>
30 +#include <linux/of_platform.h>
32 #include <asm/checksum.h>
35 #define ETOP_MII_REVERSE 0xe
36 #define ETOP_PLEN_UNDER 0x40
37 #define ETOP_CGEN 0x800
39 -/* use 2 static channels for TX/RX */
40 -#define LTQ_ETOP_TX_CHANNEL 1
41 -#define LTQ_ETOP_RX_CHANNEL 6
42 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
43 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
45 +#define ETOP_CFG_MII0 0x01
47 +#define LTQ_GBIT_MDIO_CTL 0xCC
48 +#define LTQ_GBIT_MDIO_DATA 0xd0
49 +#define LTQ_GBIT_GCTL0 0x68
50 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c
51 +#define LTQ_GBIT_P0_CTL 0x4
52 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8
54 +#define PMAC_HD_CTL_AS (1 << 19)
55 +#define PMAC_HD_CTL_RXSH (1 << 22)
57 +/* Switch Enable (0=disable, 1=enable) */
58 +#define GCTL0_SE 0x80000000
59 +/* Disable MDIO auto polling (0=disable, 1=enable) */
60 +#define PX_CTL_DMDIO 0x00400000
62 +/* register information for the gbit's MDIO bus */
63 +#define MDIO_XR9_REQUEST 0x00008000
64 +#define MDIO_XR9_READ 0x00000800
65 +#define MDIO_XR9_WRITE 0x00000400
66 +#define MDIO_XR9_REG_MASK 0x1f
67 +#define MDIO_XR9_ADDR_MASK 0x1f
68 +#define MDIO_XR9_RD_MASK 0xffff
69 +#define MDIO_XR9_REG_OFFSET 0
70 +#define MDIO_XR9_ADDR_OFFSET 5
71 +#define MDIO_XR9_WR_OFFSET 16
73 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
74 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
76 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
77 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
78 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
79 #define ltq_etop_w32_mask(x, y, z) \
80 ltq_w32_mask(x, y, ltq_etop_membase + (z))
82 -#define DRV_VERSION "1.0"
83 +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
84 +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
85 +#define ltq_gbit_w32_mask(x, y, z) \
86 + ltq_w32_mask(x, y, ltq_gbit_membase + (z))
88 +#define DRV_VERSION "1.2"
90 static void __iomem *ltq_etop_membase;
91 +static void __iomem *ltq_gbit_membase;
93 struct ltq_etop_chan {
97 struct net_device *netdev;
98 struct napi_struct napi;
99 struct ltq_dma_channel dma;
100 @@ -99,22 +134,35 @@ struct ltq_etop_chan {
101 struct ltq_etop_priv {
102 struct net_device *netdev;
103 struct platform_device *pdev;
104 - struct ltq_eth_data *pldata;
105 struct resource *res;
107 struct mii_bus *mii_bus;
108 struct phy_device *phydev;
110 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
111 - int tx_free[MAX_DMA_CHAN >> 1];
112 + struct ltq_etop_chan txch;
113 + struct ltq_etop_chan rxch;
123 + struct clk *clk_ppe;
124 + struct clk *clk_switch;
125 + struct clk *clk_ephy;
126 + struct clk *clk_ephycgu;
129 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
130 + int phy_reg, u16 phy_data);
133 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
135 - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
136 + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
137 if (!ch->skb[ch->dma.desc])
139 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
140 @@ -149,8 +197,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan *ch)
141 spin_unlock_irqrestore(&priv->lock, flags);
144 + skb->dev = ch->netdev;
145 skb->protocol = eth_type_trans(skb, ch->netdev);
146 netif_receive_skb(skb);
147 + ch->netdev->stats.rx_packets++;
148 + ch->netdev->stats.rx_bytes += len;
152 @@ -158,8 +209,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
154 struct ltq_etop_chan *ch = container_of(napi,
155 struct ltq_etop_chan, napi);
156 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
159 + unsigned long flags;
161 while ((rx < budget) && !complete) {
162 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
163 @@ -173,7 +226,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
165 if (complete || !rx) {
166 napi_complete(&ch->napi);
167 + spin_lock_irqsave(&priv->lock, flags);
168 ltq_dma_ack_irq(&ch->dma);
169 + spin_unlock_irqrestore(&priv->lock, flags);
173 @@ -185,12 +240,14 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
174 container_of(napi, struct ltq_etop_chan, napi);
175 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
176 struct netdev_queue *txq =
177 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
178 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
181 spin_lock_irqsave(&priv->lock, flags);
182 while ((ch->dma.desc_base[ch->tx_free].ctl &
183 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
184 + ch->netdev->stats.tx_packets++;
185 + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
186 dev_kfree_skb_any(ch->skb[ch->tx_free]);
187 ch->skb[ch->tx_free] = NULL;
188 memset(&ch->dma.desc_base[ch->tx_free], 0,
189 @@ -203,7 +260,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
190 if (netif_tx_queue_stopped(txq))
191 netif_tx_start_queue(txq);
192 napi_complete(&ch->napi);
193 + spin_lock_irqsave(&priv->lock, flags);
194 ltq_dma_ack_irq(&ch->dma);
195 + spin_unlock_irqrestore(&priv->lock, flags);
199 @@ -211,9 +270,10 @@ static irqreturn_t
200 ltq_etop_dma_irq(int irq, void *_priv)
202 struct ltq_etop_priv *priv = _priv;
203 - int ch = irq - LTQ_DMA_CH0_INT;
205 - napi_schedule(&priv->ch[ch].napi);
206 + if (irq == priv->txch.dma.irq)
207 + napi_schedule(&priv->txch.napi);
209 + napi_schedule(&priv->rxch.napi);
213 @@ -225,7 +285,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
214 ltq_dma_free(&ch->dma);
216 free_irq(ch->dma.irq, priv);
217 - if (IS_RX(ch->idx)) {
218 + if (ch == &priv->txch) {
220 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
221 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
222 @@ -236,23 +296,55 @@ static void
223 ltq_etop_hw_exit(struct net_device *dev)
225 struct ltq_etop_priv *priv = netdev_priv(dev);
228 - ltq_pmu_disable(PMU_PPE);
229 - for (i = 0; i < MAX_DMA_CHAN; i++)
230 - if (IS_TX(i) || IS_RX(i))
231 - ltq_etop_free_channel(dev, &priv->ch[i]);
232 + clk_disable(priv->clk_ppe);
234 + if (of_machine_is_compatible("lantiq,ar9"))
235 + clk_disable(priv->clk_switch);
237 + if (of_machine_is_compatible("lantiq,ase")) {
238 + clk_disable(priv->clk_ephy);
239 + clk_disable(priv->clk_ephycgu);
242 + ltq_etop_free_channel(dev, &priv->txch);
243 + ltq_etop_free_channel(dev, &priv->rxch);
247 +ltq_etop_gbit_init(struct net_device *dev)
249 + struct ltq_etop_priv *priv = netdev_priv(dev);
251 + clk_enable(priv->clk_switch);
253 + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
254 + /** Disable MDIO auto polling mode */
255 + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
256 + /* set 1522 packet size */
257 + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
258 + /* disable pmac & dmac headers */
259 + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
260 + LTQ_GBIT_PMAC_HD_CTL);
261 + /* Due to traffic halt when burst length 8,
262 + replace default IPG value with 0x3B */
263 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
267 ltq_etop_hw_init(struct net_device *dev)
269 struct ltq_etop_priv *priv = netdev_priv(dev);
272 - ltq_pmu_enable(PMU_PPE);
273 + clk_enable(priv->clk_ppe);
275 - switch (priv->pldata->mii_mode) {
276 + if (of_machine_is_compatible("lantiq,ar9")) {
277 + ltq_etop_gbit_init(dev);
278 + /* force the etops link to the gbit to MII */
279 + priv->mii_mode = PHY_INTERFACE_MODE_MII;
282 + switch (priv->mii_mode) {
283 case PHY_INTERFACE_MODE_RMII:
284 ltq_etop_w32_mask(ETOP_MII_MASK,
285 ETOP_MII_REVERSE, LTQ_ETOP_CFG);
286 @@ -264,39 +356,68 @@ ltq_etop_hw_init(struct net_device *dev)
290 + if (of_machine_is_compatible("lantiq,ase")) {
291 + clk_enable(priv->clk_ephy);
292 + /* disable external MII */
293 + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
294 + /* enable clock for internal PHY */
295 + clk_enable(priv->clk_ephycgu);
296 + /* we need to write this magic to the internal phy to
298 + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
299 + pr_info("Selected EPHY mode\n");
302 netdev_err(dev, "unknown mii mode %d\n",
303 - priv->pldata->mii_mode);
308 /* enable crc generation */
309 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
315 +ltq_etop_dma_init(struct net_device *dev)
317 + struct ltq_etop_priv *priv = netdev_priv(dev);
318 + int tx = priv->tx_irq - LTQ_DMA_ETOP;
319 + int rx = priv->rx_irq - LTQ_DMA_ETOP;
322 ltq_dma_init_port(DMA_PORT_ETOP);
324 - for (i = 0; i < MAX_DMA_CHAN; i++) {
325 - int irq = LTQ_DMA_CH0_INT + i;
326 - struct ltq_etop_chan *ch = &priv->ch[i];
328 - ch->idx = ch->dma.nr = i;
331 - ltq_dma_alloc_tx(&ch->dma);
332 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
334 - } else if (IS_RX(i)) {
335 - ltq_dma_alloc_rx(&ch->dma);
336 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
338 - if (ltq_etop_alloc_skb(ch))
341 - request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
343 + priv->txch.dma.nr = tx;
344 + ltq_dma_alloc_tx(&priv->txch.dma);
345 + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
348 + netdev_err(dev, "failed to allocate tx irq\n");
351 + priv->txch.dma.irq = priv->tx_irq;
353 + priv->rxch.dma.nr = rx;
354 + ltq_dma_alloc_rx(&priv->rxch.dma);
355 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
356 + priv->rxch.dma.desc++) {
357 + if (ltq_etop_alloc_skb(&priv->rxch)) {
358 + netdev_err(dev, "failed to allocate skbs\n");
365 + priv->rxch.dma.desc = 0;
366 + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
369 + netdev_err(dev, "failed to allocate rx irq\n");
371 + priv->rxch.dma.irq = priv->rx_irq;
377 @@ -312,7 +433,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
379 struct ltq_etop_priv *priv = netdev_priv(dev);
381 - return phy_ethtool_gset(priv->phydev, cmd);
383 + return phy_ethtool_gset(priv->phydev, cmd);
389 @@ -320,7 +444,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
391 struct ltq_etop_priv *priv = netdev_priv(dev);
393 - return phy_ethtool_sset(priv->phydev, cmd);
395 + return phy_ethtool_sset(priv->phydev, cmd);
401 @@ -328,7 +455,10 @@ ltq_etop_nway_reset(struct net_device *dev)
403 struct ltq_etop_priv *priv = netdev_priv(dev);
405 - return phy_start_aneg(priv->phydev);
407 + return phy_start_aneg(priv->phydev);
412 static const struct ethtool_ops ltq_etop_ethtool_ops = {
413 @@ -339,6 +469,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
417 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
418 + int phy_reg, u16 phy_data)
420 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
421 + (phy_data << MDIO_XR9_WR_OFFSET) |
422 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
423 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
425 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
427 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
428 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
434 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
436 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
437 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
438 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
440 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
442 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
443 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
445 + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
450 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
452 u32 val = MDIO_REQUEST |
453 @@ -379,14 +542,11 @@ ltq_etop_mdio_probe(struct net_device *dev)
455 struct ltq_etop_priv *priv = netdev_priv(dev);
456 struct phy_device *phydev = NULL;
459 - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
460 - if (priv->mii_bus->phy_map[phy_addr]) {
461 - phydev = priv->mii_bus->phy_map[phy_addr];
465 + if (of_machine_is_compatible("lantiq,ase"))
466 + phydev = priv->mii_bus->phy_map[8];
468 + phydev = priv->mii_bus->phy_map[0];
471 netdev_err(dev, "no PHY found\n");
472 @@ -394,7 +554,7 @@ ltq_etop_mdio_probe(struct net_device *dev)
475 phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link,
476 - 0, priv->pldata->mii_mode);
477 + 0, priv->mii_mode);
479 if (IS_ERR(phydev)) {
480 netdev_err(dev, "Could not attach to PHY\n");
481 @@ -408,6 +568,9 @@ ltq_etop_mdio_probe(struct net_device *dev)
485 + if (of_machine_is_compatible("lantiq,ar9"))
486 + phydev->supported &= SUPPORTED_1000baseT_Half
487 + | SUPPORTED_1000baseT_Full;
489 phydev->advertising = phydev->supported;
490 priv->phydev = phydev;
491 @@ -433,8 +596,13 @@ ltq_etop_mdio_init(struct net_device *dev)
494 priv->mii_bus->priv = dev;
495 - priv->mii_bus->read = ltq_etop_mdio_rd;
496 - priv->mii_bus->write = ltq_etop_mdio_wr;
497 + if (of_machine_is_compatible("lantiq,ar9")) {
498 + priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
499 + priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
501 + priv->mii_bus->read = ltq_etop_mdio_rd;
502 + priv->mii_bus->write = ltq_etop_mdio_wr;
504 priv->mii_bus->name = "ltq_mii";
505 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
506 priv->pdev->name, priv->pdev->id);
507 @@ -483,17 +651,19 @@ static int
508 ltq_etop_open(struct net_device *dev)
510 struct ltq_etop_priv *priv = netdev_priv(dev);
512 + unsigned long flags;
514 - for (i = 0; i < MAX_DMA_CHAN; i++) {
515 - struct ltq_etop_chan *ch = &priv->ch[i];
516 + napi_enable(&priv->txch.napi);
517 + napi_enable(&priv->rxch.napi);
519 + spin_lock_irqsave(&priv->lock, flags);
520 + ltq_dma_open(&priv->txch.dma);
521 + ltq_dma_open(&priv->rxch.dma);
522 + spin_unlock_irqrestore(&priv->lock, flags);
525 + phy_start(priv->phydev);
527 - if (!IS_TX(i) && (!IS_RX(i)))
529 - ltq_dma_open(&ch->dma);
530 - napi_enable(&ch->napi);
532 - phy_start(priv->phydev);
533 netif_tx_start_all_queues(dev);
536 @@ -502,18 +672,19 @@ static int
537 ltq_etop_stop(struct net_device *dev)
539 struct ltq_etop_priv *priv = netdev_priv(dev);
541 + unsigned long flags;
543 netif_tx_stop_all_queues(dev);
544 - phy_stop(priv->phydev);
545 - for (i = 0; i < MAX_DMA_CHAN; i++) {
546 - struct ltq_etop_chan *ch = &priv->ch[i];
548 + phy_stop(priv->phydev);
549 + napi_disable(&priv->txch.napi);
550 + napi_disable(&priv->rxch.napi);
552 + spin_lock_irqsave(&priv->lock, flags);
553 + ltq_dma_close(&priv->txch.dma);
554 + ltq_dma_close(&priv->rxch.dma);
555 + spin_unlock_irqrestore(&priv->lock, flags);
557 - if (!IS_RX(i) && !IS_TX(i))
559 - napi_disable(&ch->napi);
560 - ltq_dma_close(&ch->dma);
565 @@ -523,16 +694,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
566 int queue = skb_get_queue_mapping(skb);
567 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
568 struct ltq_etop_priv *priv = netdev_priv(dev);
569 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
570 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
572 + struct ltq_dma_desc *desc =
573 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
578 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
580 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
581 - dev_kfree_skb_any(skb);
582 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
583 + priv->txch.skb[priv->txch.dma.desc]) {
584 netdev_err(dev, "tx ring full\n");
585 netif_tx_stop_queue(txq);
586 return NETDEV_TX_BUSY;
587 @@ -540,7 +711,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
589 /* dma needs to start on a 16 byte aligned address */
590 byte_offset = CPHYSADDR(skb->data) % 16;
591 - ch->skb[ch->dma.desc] = skb;
592 + priv->txch.skb[priv->txch.dma.desc] = skb;
594 dev->trans_start = jiffies;
596 @@ -550,11 +721,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
598 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
599 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
601 - ch->dma.desc %= LTQ_DESC_NUM;
602 + priv->txch.dma.desc++;
603 + priv->txch.dma.desc %= LTQ_DESC_NUM;
604 spin_unlock_irqrestore(&priv->lock, flags);
606 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
607 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
608 netif_tx_stop_queue(txq);
611 @@ -633,34 +804,32 @@ ltq_etop_init(struct net_device *dev)
612 struct ltq_etop_priv *priv = netdev_priv(dev);
615 - bool random_mac = false;
618 dev->watchdog_timeo = 10 * HZ;
619 err = ltq_etop_hw_init(dev);
622 + err = ltq_etop_dma_init(dev);
626 ltq_etop_change_mtu(dev, 1500);
628 - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
629 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
630 if (!is_valid_ether_addr(mac.sa_data)) {
631 pr_warn("etop: invalid MAC, using random\n");
632 - eth_random_addr(mac.sa_data);
634 + random_ether_addr(mac.sa_data);
637 err = ltq_etop_set_mac_address(dev, &mac);
641 - /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
643 - dev->addr_assign_type |= NET_ADDR_RANDOM;
645 ltq_etop_set_multicast_list(dev);
646 - err = ltq_etop_mdio_init(dev);
649 + if (!ltq_etop_mdio_init(dev))
650 + dev->ethtool_ops = <q_etop_ethtool_ops;
652 + pr_warn("etop: mdio probe failed\n");;
656 @@ -680,6 +849,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
657 err = ltq_etop_hw_init(dev);
660 + err = ltq_etop_dma_init(dev);
663 dev->trans_start = jiffies;
664 netif_wake_queue(dev);
666 @@ -703,14 +875,19 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
667 .ndo_tx_timeout = ltq_etop_tx_timeout,
671 +static int __devinit
672 ltq_etop_probe(struct platform_device *pdev)
674 struct net_device *dev;
675 struct ltq_etop_priv *priv;
676 - struct resource *res;
677 + struct resource *res, *gbit_res, irqres[2];
681 + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
683 + dev_err(&pdev->dev, "failed to get etop irqs\n");
687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689 @@ -736,30 +913,58 @@ ltq_etop_probe(struct platform_device *pdev)
693 - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
697 + if (of_machine_is_compatible("lantiq,ar9")) {
698 + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
700 + dev_err(&pdev->dev, "failed to get gbit resource\n");
704 + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
705 + gbit_res->start, resource_size(gbit_res));
706 + if (!ltq_gbit_membase) {
707 + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
714 + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
715 strcpy(dev->name, "eth%d");
716 dev->netdev_ops = <q_eth_netdev_ops;
717 - dev->ethtool_ops = <q_etop_ethtool_ops;
718 priv = netdev_priv(dev);
721 - priv->pldata = dev_get_platdata(&pdev->dev);
723 + priv->tx_irq = irqres[0].start;
724 + priv->rx_irq = irqres[1].start;
725 + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
726 + priv->mac = of_get_mac_address(pdev->dev.of_node);
728 + priv->clk_ppe = clk_get(&pdev->dev, NULL);
729 + if (IS_ERR(priv->clk_ppe))
730 + return PTR_ERR(priv->clk_ppe);
731 + if (of_machine_is_compatible("lantiq,ar9")) {
732 + priv->clk_switch = clk_get(&pdev->dev, "switch");
733 + if (IS_ERR(priv->clk_switch))
734 + return PTR_ERR(priv->clk_switch);
736 + if (of_machine_is_compatible("lantiq,ase")) {
737 + priv->clk_ephy = clk_get(&pdev->dev, "ephy");
738 + if (IS_ERR(priv->clk_ephy))
739 + return PTR_ERR(priv->clk_ephy);
740 + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
741 + if (IS_ERR(priv->clk_ephycgu))
742 + return PTR_ERR(priv->clk_ephycgu);
745 spin_lock_init(&priv->lock);
747 - for (i = 0; i < MAX_DMA_CHAN; i++) {
749 - netif_napi_add(dev, &priv->ch[i].napi,
750 - ltq_etop_poll_tx, 8);
752 - netif_napi_add(dev, &priv->ch[i].napi,
753 - ltq_etop_poll_rx, 32);
754 - priv->ch[i].netdev = dev;
756 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
757 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
758 + priv->txch.netdev = dev;
759 + priv->rxch.netdev = dev;
761 err = register_netdev(dev);
763 @@ -788,32 +993,23 @@ ltq_etop_remove(struct platform_device *pdev)
767 +static const struct of_device_id ltq_etop_match[] = {
768 + { .compatible = "lantiq,etop-xway" },
771 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
773 static struct platform_driver ltq_mii_driver = {
774 + .probe = ltq_etop_probe,
775 .remove = __devexit_p(ltq_etop_remove),
778 .owner = THIS_MODULE,
779 + .of_match_table = ltq_etop_match,
786 - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
789 - pr_err("ltq_etop: Error registering platform driver!");
796 - platform_driver_unregister(<q_mii_driver);
799 -module_init(init_ltq_etop);
800 -module_exit(exit_ltq_etop);
801 +module_platform_driver(ltq_mii_driver);
803 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
804 MODULE_DESCRIPTION("Lantiq SoC ETOP");