1 From 8d2a7d1fb561c9cb098c2b13ded34fe0f49dcca5 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Aug 2012 10:27:25 +0200
4 Subject: [PATCH 20/25] owrt atm
7 arch/mips/lantiq/irq.c | 2 ++
8 arch/mips/mm/cache.c | 2 ++
9 net/atm/common.c | 6 ++++++
11 4 files changed, 11 insertions(+), 1 deletions(-)
13 --- a/arch/mips/lantiq/irq.c
14 +++ b/arch/mips/lantiq/irq.c
16 #include <linux/of_platform.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 +#include <linux/module.h>
21 #include <asm/bootinfo.h>
22 #include <asm/irq_cpu.h>
23 @@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
24 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
25 ltq_icu_w32(im, BIT(offset), isr);
27 +EXPORT_SYMBOL(ltq_mask_and_ack_irq);
29 static void ltq_ack_irq(struct irq_data *d)
31 --- a/arch/mips/mm/cache.c
32 +++ b/arch/mips/mm/cache.c
33 @@ -58,6 +58,8 @@ void (*_dma_cache_wback)(unsigned long s
34 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
36 EXPORT_SYMBOL(_dma_cache_wback_inv);
37 +EXPORT_SYMBOL(_dma_cache_wback);
38 +EXPORT_SYMBOL(_dma_cache_inv);
40 #endif /* CONFIG_DMA_NONCOHERENT */
42 --- a/net/atm/common.c
43 +++ b/net/atm/common.c
44 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc
45 write_unlock_irq(&vcc_sklist_lock);
48 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
49 +EXPORT_SYMBOL(ifx_atm_alloc_tx);
51 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
54 struct sock *sk = sk_atm(vcc);
56 + if (ifx_atm_alloc_tx != NULL)
57 + return ifx_atm_alloc_tx(vcc, size);
59 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
60 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
61 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
64 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil
65 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
67 static const char *const class_name[] = {
68 - "off", "UBR", "CBR", "VBR", "ABR"};
69 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
70 static const char *const aal_name[] = {
71 "---", "1", "2", "3/4", /* 0- 3 */
72 "???", "5", "???", "???", /* 4- 7 */
74 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
76 +/******************************************************************************
78 +** FILE NAME : ifx_atm.h
82 +** DATE : 17 Jun 2009
84 +** DESCRIPTION : Global ATM driver header file
85 +** COPYRIGHT : Copyright (c) 2006
86 +** Infineon Technologies AG
87 +** Am Campeon 1-12, 85579 Neubiberg, Germany
89 +** This program is free software; you can redistribute it and/or modify
90 +** it under the terms of the GNU General Public License as published by
91 +** the Free Software Foundation; either version 2 of the License, or
92 +** (at your option) any later version.
95 +** $Date $Author $Comment
96 +** 07 JUL 2009 Xu Liang Init Version
97 +*******************************************************************************/
105 + \defgroup IFX_ATM UEIP Project - ATM driver module
106 + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
110 + \defgroup IFX_ATM_IOCTL IOCTL Commands
112 + \brief IOCTL Commands used by user application.
116 + \defgroup IFX_ATM_STRUCT Structures
118 + \brief Structures used by user application.
124 + \brief ATM driver header file
130 + * ####################################
132 + * ####################################
136 + \addtogroup IFX_ATM_STRUCT
145 + \struct atm_cell_ifEntry_t
146 + \brief Structure used for Cell Level MIB Counters.
148 + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
151 + __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
152 + __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
153 + __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
154 + __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
155 + __u32 ifInErrors; /*!< counter of error ingress cells */
156 + __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
157 + __u32 ifOutErrors; /*!< counter of error egress cells */
158 +} atm_cell_ifEntry_t;
161 + \struct atm_aal5_ifEntry_t
162 + \brief Structure used for AAL5 Frame Level MIB Counters.
164 + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
167 + __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
168 + __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
169 + __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
170 + __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
171 + __u32 ifInUcastPkts; /*!< counter of ingress packets */
172 + __u32 ifOutUcastPkts; /*!< counter of egress packets */
173 + __u32 ifInErrors; /*!< counter of error ingress packets */
174 + __u32 ifInDiscards; /*!< counter of dropped ingress packets */
175 + __u32 ifOutErros; /*!< counter of error egress packets */
176 + __u32 ifOutDiscards; /*!< counter of dropped egress packets */
177 +} atm_aal5_ifEntry_t;
180 + \struct atm_aal5_vcc_t
181 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
183 + This structure is a part of structure "atm_aal5_vcc_x_t".
186 + __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
187 + __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
188 + __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
192 + \struct atm_aal5_vcc_x_t
193 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
195 + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
198 + int vpi; /*!< VPI of the VCC to get MIB counters */
199 + int vci; /*!< VCI of the VCC to get MIB counters */
200 + atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
208 + * ####################################
210 + * ####################################
214 + \addtogroup IFX_ATM_IOCTL
222 + \brief ATM IOCTL Magic Number
224 +#define PPE_ATM_IOC_MAGIC 'o'
226 + \brief ATM IOCTL Command - Get Cell Level MIB Counters
228 + This command is obsolete. User can get cell level MIB from DSL API.
229 + This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
231 +#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
233 + \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
235 + Get AAL5 packet counters.
236 + This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
238 +#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
240 + \brief ATM IOCTL Command - Get Per PVC MIB Counters
242 + Get AAL5 packet counters for each PVC.
243 + This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
245 +#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
247 + \brief Total Number of ATM IOCTL Commands
249 +#define PPE_ATM_IOC_MAXNR 3
256 + * ####################################
258 + * ####################################
262 +struct port_cell_info {
263 + unsigned int port_num;
264 + unsigned int tx_link_rate[2];
273 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
275 +/******************************************************************************
277 +** FILE NAME : ifx_ptm.h
281 +** DATE : 17 Jun 2009
282 +** AUTHOR : Xu Liang
283 +** DESCRIPTION : Global PTM driver header file
284 +** COPYRIGHT : Copyright (c) 2006
285 +** Infineon Technologies AG
286 +** Am Campeon 1-12, 85579 Neubiberg, Germany
288 +** This program is free software; you can redistribute it and/or modify
289 +** it under the terms of the GNU General Public License as published by
290 +** the Free Software Foundation; either version 2 of the License, or
291 +** (at your option) any later version.
294 +** $Date $Author $Comment
295 +** 07 JUL 2009 Xu Liang Init Version
296 +*******************************************************************************/
304 + \defgroup IFX_PTM UEIP Project - PTM driver module
305 + \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
309 + \defgroup IFX_PTM_IOCTL IOCTL Commands
311 + \brief IOCTL Commands used by user application.
315 + \defgroup IFX_PTM_STRUCT Structures
317 + \brief Structures used by user application.
323 + \brief PTM driver header file
329 + * ####################################
331 + * ####################################
337 + * ####################################
339 + * ####################################
343 + \addtogroup IFX_PTM_IOCTL
351 + \brief PTM IOCTL Command - Get codeword MIB counters.
353 + This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
355 +#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
357 + \brief PTM IOCTL Command - Get packet MIB counters.
359 + This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
361 +#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
363 + \brief PTM IOCTL Command - Get firmware configuration (CRC).
365 + This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
367 +#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
369 + \brief PTM IOCTL Command - Set firmware configuration (CRC).
371 + This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
373 +#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
375 + \brief PTM IOCTL Command - Program priority value to TX queue mapping.
377 + This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
379 +#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
385 + \addtogroup IFX_PTM_STRUCT
394 + \typedef PTM_CW_IF_ENTRY_T
395 + \brief Wrapping of structure "ptm_cw_ifEntry_t".
398 + \struct ptm_cw_ifEntry_t
399 + \brief Structure used for CodeWord level MIB counters.
401 +typedef struct ptm_cw_ifEntry_t {
402 + uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
403 + uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
404 + uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
405 + uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
406 + uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
407 +} PTM_CW_IF_ENTRY_T;
410 + \typedef PTM_FRAME_MIB_T
411 + \brief Wrapping of structure "ptm_frame_mib_t".
414 + \struct ptm_frame_mib_t
415 + \brief Structure used for packet level MIB counters.
417 +typedef struct ptm_frame_mib_t {
418 + uint32_t RxCorrect; /*!< output, number of ingress packet */
419 + uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
420 + uint32_t RxDropped; /*!< output, number of dropped ingress packet */
421 + uint32_t TxSend; /*!< output, number of egress packet */
425 + \typedef IFX_PTM_CFG_T
426 + \brief Wrapping of structure "ptm_cfg_t".
430 + \brief Structure used for ETH/TC CRC configuration.
432 +typedef struct ptm_cfg_t {
433 + uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
434 + uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
435 + uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
436 + uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
437 + uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
438 + uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
439 + uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
443 + \typedef IFX_PTM_PRIO_Q_MAP_T
444 + \brief Wrapping of structure "ppe_prio_q_map".
447 + \struct ppe_prio_q_map
448 + \brief Structure used for Priority Value to TX Queue mapping.
450 +typedef struct ppe_prio_q_map {
453 + int vpi; // ignored in eth interface
454 + int vci; // ignored in eth interface
455 +} IFX_PTM_PRIO_Q_MAP_T;
462 + * ####################################
464 + * ####################################
468 +struct port_cell_info {
469 + unsigned int port_num;
470 + unsigned int tx_link_rate[2];
478 --- a/include/uapi/linux/atm.h
479 +++ b/include/uapi/linux/atm.h
482 #define ATM_ANYCLASS 5 /* compatible with everything */
484 +#define ATM_VBR_NRT ATM_VBR
485 +#define ATM_VBR_RT 6
486 +#define ATM_UBR_PLUS 7
489 #define ATM_MAX_PCR -1 /* maximum available PCR */
493 unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
494 int max_pcr; /* maximum PCR in cells per second */