target/linux/lantiq/patches-3.8/0019-MIPS-lantiq-rework-external-irq-code.patch

   1 From d8f6bf3fb606ee8fdd5b7aff4aedb54e30792b84 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sat, 19 Jan 2013 08:54:27 +0000
   4 Subject: [PATCH 19/40] MIPS: lantiq: rework external irq code
   5
   6 This code makes the irqs used by the EIU loadable from the DT. Additionally we
   7 add a helper that allows the pinctrl layer to map external irqs to real irq
   8 numbers.
   9
  10 Signed-off-by: John Crispin <blogic@openwrt.org>
  11 Patchwork: http://patchwork.linux-mips.org/patch/4818/
  12 ---
  13  arch/mips/include/asm/mach-lantiq/lantiq.h |    1 +
  14  arch/mips/lantiq/irq.c                     |  105 +++++++++++++++++++---------
  15  2 files changed, 74 insertions(+), 32 deletions(-)
  16
  17 --- a/arch/mips/include/asm/mach-lantiq/lantiq.h
  18 +++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
  19 @@ -34,6 +34,7 @@ extern spinlock_t ebu_lock;
  20  extern void ltq_disable_irq(struct irq_data *data);
  21  extern void ltq_mask_and_ack_irq(struct irq_data *data);
  22  extern void ltq_enable_irq(struct irq_data *data);
  23 +extern int ltq_eiu_get_irq(int exin);
  24
  25  /* clock handling */
  26  extern int clk_activate(struct clk *clk);
  27 --- a/arch/mips/lantiq/irq.c
  28 +++ b/arch/mips/lantiq/irq.c
  29 @@ -33,17 +33,10 @@
  30  /* register definitions - external irqs */
  31  #define LTQ_EIU_EXIN_C         0x0000
  32  #define LTQ_EIU_EXIN_INIC      0x0004
  33 +#define LTQ_EIU_EXIN_INC       0x0008
  34  #define LTQ_EIU_EXIN_INEN      0x000C
  35
  36 -/* irq numbers used by the external interrupt unit (EIU) */
  37 -#define LTQ_EIU_IR0            (INT_NUM_IM4_IRL0 + 30)
  38 -#define LTQ_EIU_IR1            (INT_NUM_IM3_IRL0 + 31)
  39 -#define LTQ_EIU_IR2            (INT_NUM_IM1_IRL0 + 26)
  40 -#define LTQ_EIU_IR3            INT_NUM_IM1_IRL0
  41 -#define LTQ_EIU_IR4            (INT_NUM_IM1_IRL0 + 1)
  42 -#define LTQ_EIU_IR5            (INT_NUM_IM1_IRL0 + 2)
  43 -#define LTQ_EIU_IR6            (INT_NUM_IM2_IRL0 + 30)
  44 -#define XWAY_EXIN_COUNT                3
  45 +/* number of external interrupts */
  46  #define MAX_EIU                        6
  47
  48  /* the performance counter */
  49 @@ -72,20 +65,19 @@
  50  int gic_present;
  51  #endif
  52
  53 -static unsigned short ltq_eiu_irq[MAX_EIU] = {
  54 -       LTQ_EIU_IR0,
  55 -       LTQ_EIU_IR1,
  56 -       LTQ_EIU_IR2,
  57 -       LTQ_EIU_IR3,
  58 -       LTQ_EIU_IR4,
  59 -       LTQ_EIU_IR5,
  60 -};
  61 -
  62  static int exin_avail;
  63 +static struct resource ltq_eiu_irq[MAX_EIU];
  64  static void __iomem *ltq_icu_membase[MAX_IM];
  65  static void __iomem *ltq_eiu_membase;
  66  static struct irq_domain *ltq_domain;
  67
  68 +int ltq_eiu_get_irq(int exin)
  69 +{
  70 +       if (exin < exin_avail)
  71 +               return ltq_eiu_irq[exin].start;
  72 +       return -1;
  73 +}
  74 +
  75  void ltq_disable_irq(struct irq_data *d)
  76  {
  77         u32 ier = LTQ_ICU_IM0_IER;
  78 @@ -128,19 +120,65 @@ void ltq_enable_irq(struct irq_data *d)
  79         ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
  80  }
  81
  82 +static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
  83 +{
  84 +       int i;
  85 +
  86 +       for (i = 0; i < MAX_EIU; i++) {
  87 +               if (d->hwirq == ltq_eiu_irq[i].start) {
  88 +                       int val = 0;
  89 +                       int edge = 0;
  90 +
  91 +                       switch (type) {
  92 +                       case IRQF_TRIGGER_NONE:
  93 +                               break;
  94 +                       case IRQF_TRIGGER_RISING:
  95 +                               val = 1;
  96 +                               edge = 1;
  97 +                               break;
  98 +                       case IRQF_TRIGGER_FALLING:
  99 +                               val = 2;
 100 +                               edge = 1;
 101 +                               break;
 102 +                       case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
 103 +                               val = 3;
 104 +                               edge = 1;
 105 +                               break;
 106 +                       case IRQF_TRIGGER_HIGH:
 107 +                               val = 5;
 108 +                               break;
 109 +                       case IRQF_TRIGGER_LOW:
 110 +                               val = 6;
 111 +                               break;
 112 +                       default:
 113 +                               pr_err("invalid type %d for irq %ld\n",
 114 +                                       type, d->hwirq);
 115 +                               return -EINVAL;
 116 +                       }
 117 +
 118 +                       if (edge)
 119 +                               irq_set_handler(d->hwirq, handle_edge_irq);
 120 +
 121 +                       ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
 122 +                               (val << (i * 4)), LTQ_EIU_EXIN_C);
 123 +               }
 124 +       }
 125 +
 126 +       return 0;
 127 +}
 128 +
 129  static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
 130  {
 131         int i;
 132
 133         ltq_enable_irq(d);
 134         for (i = 0; i < MAX_EIU; i++) {
 135 -               if (d->hwirq == ltq_eiu_irq[i]) {
 136 -                       /* low level - we should really handle set_type */
 137 -                       ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
 138 -                               (0x6 << (i * 4)), LTQ_EIU_EXIN_C);
 139 +               if (d->hwirq == ltq_eiu_irq[i].start) {
 140 +                       /* by default we are low level triggered */
 141 +                       ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
 142                         /* clear all pending */
 143 -                       ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
 144 -                               LTQ_EIU_EXIN_INIC);
 145 +                       ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
 146 +                               LTQ_EIU_EXIN_INC);
 147                         /* enable */
 148                         ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
 149                                 LTQ_EIU_EXIN_INEN);
 150 @@ -157,7 +195,7 @@ static void ltq_shutdown_eiu_irq(struct
 151
 152         ltq_disable_irq(d);
 153         for (i = 0; i < MAX_EIU; i++) {
 154 -               if (d->hwirq == ltq_eiu_irq[i]) {
 155 +               if (d->hwirq == ltq_eiu_irq[i].start) {
 156                         /* disable */
 157                         ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
 158                                 LTQ_EIU_EXIN_INEN);
 159 @@ -186,6 +224,7 @@ static struct irq_chip ltq_eiu_type = {
 160         .irq_ack = ltq_ack_irq,
 161         .irq_mask = ltq_disable_irq,
 162         .irq_mask_ack = ltq_mask_and_ack_irq,
 163 +       .irq_set_type = ltq_eiu_settype,
 164  };
 165
 166  static void ltq_hw_irqdispatch(int module)
 167 @@ -301,7 +340,7 @@ static int icu_map(struct irq_domain *d,
 168                 return 0;
 169
 170         for (i = 0; i < exin_avail; i++)
 171 -               if (hw == ltq_eiu_irq[i])
 172 +               if (hw == ltq_eiu_irq[i].start)
 173                         chip = &ltq_eiu_type;
 174
 175         irq_set_chip_and_handler(hw, chip, handle_level_irq);
 176 @@ -323,7 +362,7 @@ int __init icu_of_init(struct device_nod
 177  {
 178         struct device_node *eiu_node;
 179         struct resource res;
 180 -       int i;
 181 +       int i, ret;
 182
 183         for (i = 0; i < MAX_IM; i++) {
 184                 if (of_address_to_resource(node, i, &res))
 185 @@ -340,17 +379,19 @@ int __init icu_of_init(struct device_nod
 186         }
 187
 188         /* the external interrupts are optional and xway only */
 189 -       eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
 190 +       eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
 191         if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
 192                 /* find out how many external irq sources we have */
 193 -               const __be32 *count = of_get_property(node,
 194 -                                                       "lantiq,count", NULL);
 195 +               exin_avail = of_irq_count(eiu_node);
 196
 197 -               if (count)
 198 -                       exin_avail = *count;
 199                 if (exin_avail > MAX_EIU)
 200                         exin_avail = MAX_EIU;
 201
 202 +               ret = of_irq_to_resource_table(eiu_node,
 203 +                                               ltq_eiu_irq, exin_avail);
 204 +               if (ret != exin_avail)
 205 +                       panic("failed to load external irq resources\n");
 206 +
 207                 if (request_mem_region(res.start, resource_size(&res),
 208                                                         res.name) < 0)
 209                         pr_err("Failed to request eiu memory");