1 From 0c11f1ffaa2015a791e925741b0cdb38a2ef7e97 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 23 Jun 2012 15:32:33 +0200
4 Subject: [PATCH 03/22] GPIO: MIPS: add gpio driver for falcon SoC
6 Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
7 up to 32 pads. The GPIO blocks have a per pin IRQs.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
11 Cc: linux-kernel@vger.kernel.org
13 drivers/gpio/Kconfig | 5 +
14 drivers/gpio/Makefile | 1 +
15 drivers/gpio/gpio-falcon.c | 349 ++++++++++++++++++++++++++++++++++++++++++++
16 3 files changed, 355 insertions(+)
17 create mode 100644 drivers/gpio/gpio-falcon.c
19 --- a/drivers/gpio/Kconfig
20 +++ b/drivers/gpio/Kconfig
21 @@ -136,6 +136,11 @@ config GPIO_EP93XX
22 depends on ARCH_EP93XX
27 + depends on MIPS && SOC_FALCON
31 bool "Lantiq Memory mapped GPIOs"
32 depends on LANTIQ && SOC_XWAY
33 --- a/drivers/gpio/Makefile
34 +++ b/drivers/gpio/Makefile
35 @@ -24,6 +24,7 @@ obj-$(CONFIG_GPIO_DA9055) += gpio-da9055
36 obj-$(CONFIG_ARCH_DAVINCI) += gpio-davinci.o
37 obj-$(CONFIG_GPIO_EM) += gpio-em.o
38 obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
39 +obj-$(CONFIG_GPIO_FALCON) += gpio-falcon.o
40 obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o
41 obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
42 obj-$(CONFIG_GPIO_IT8761E) += gpio-it8761e.o
44 +++ b/drivers/gpio/gpio-falcon.c
47 + * This program is free software; you can redistribute it and/or modify it
48 + * under the terms of the GNU General Public License version 2 as published
49 + * by the Free Software Foundation.
51 + * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
52 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
55 +#include <linux/gpio.h>
56 +#include <linux/interrupt.h>
57 +#include <linux/slab.h>
58 +#include <linux/export.h>
59 +#include <linux/err.h>
60 +#include <linux/module.h>
61 +#include <linux/of.h>
62 +#include <linux/of_irq.h>
63 +#include <linux/pinctrl/pinctrl.h>
64 +#include <linux/pinctrl/consumer.h>
65 +#include <linux/platform_device.h>
67 +#include <lantiq_soc.h>
69 +/* Data Output Register */
70 +#define GPIO_OUT 0x00000000
71 +/* Data Input Register */
72 +#define GPIO_IN 0x00000004
73 +/* Direction Register */
74 +#define GPIO_DIR 0x00000008
75 +/* External Interrupt Control Register 0 */
76 +#define GPIO_EXINTCR0 0x00000018
77 +/* External Interrupt Control Register 1 */
78 +#define GPIO_EXINTCR1 0x0000001C
79 +/* IRN Capture Register */
80 +#define GPIO_IRNCR 0x00000020
81 +/* IRN Interrupt Configuration Register */
82 +#define GPIO_IRNCFG 0x0000002C
83 +/* IRN Interrupt Enable Set Register */
84 +#define GPIO_IRNRNSET 0x00000030
85 +/* IRN Interrupt Enable Clear Register */
86 +#define GPIO_IRNENCLR 0x00000034
87 +/* Output Set Register */
88 +#define GPIO_OUTSET 0x00000040
89 +/* Output Cler Register */
90 +#define GPIO_OUTCLR 0x00000044
91 +/* Direction Clear Register */
92 +#define GPIO_DIRSET 0x00000048
93 +/* Direction Set Register */
94 +#define GPIO_DIRCLR 0x0000004C
96 +/* turn a gpio_chip into a falcon_gpio_port */
97 +#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
98 +/* turn a irq_data into a falcon_gpio_port */
99 +#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
101 +#define port_r32(p, reg) ltq_r32(p->port + reg)
102 +#define port_w32(p, val, reg) ltq_w32(val, p->port + reg)
103 +#define port_w32_mask(p, clear, set, reg) \
104 + port_w32(p, (port_r32(p, reg) & ~(clear)) | (set), reg)
107 +#define PINS_PER_PORT 32
109 +struct falcon_gpio_port {
110 + struct gpio_chip gpio_chip;
111 + void __iomem *port;
112 + unsigned int irq_base;
113 + unsigned int chained_irq;
118 +static int falcon_gpio_direction_input(struct gpio_chip *chip,
119 + unsigned int offset)
121 + port_w32(ctop(chip), 1 << offset, GPIO_DIRCLR);
126 +static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset,
130 + port_w32(ctop(chip), 1 << offset, GPIO_OUTSET);
132 + port_w32(ctop(chip), 1 << offset, GPIO_OUTCLR);
135 +static int falcon_gpio_direction_output(struct gpio_chip *chip,
136 + unsigned int offset, int value)
138 + falcon_gpio_set(chip, offset, value);
139 + port_w32(ctop(chip), 1 << offset, GPIO_DIRSET);
144 +static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
146 + if ((port_r32(ctop(chip), GPIO_DIR) >> offset) & 1)
147 + return (port_r32(ctop(chip), GPIO_OUT) >> offset) & 1;
149 + return (port_r32(ctop(chip), GPIO_IN) >> offset) & 1;
152 +static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
154 + int gpio = chip->base + offset;
156 + return pinctrl_request_gpio(gpio);
159 +static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
161 + int gpio = chip->base + offset;
163 + pinctrl_free_gpio(gpio);
166 +static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
168 + return ctop(chip)->irq_base + offset;
171 +static void falcon_gpio_disable_irq(struct irq_data *d)
173 + unsigned int offset = d->irq - itop(d)->irq_base;
175 + port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
178 +static void falcon_gpio_enable_irq(struct irq_data *d)
180 + unsigned int offset = d->irq - itop(d)->irq_base;
182 + port_w32(itop(d), 1 << offset, GPIO_IRNRNSET);
185 +static void falcon_gpio_ack_irq(struct irq_data *d)
187 + unsigned int offset = d->irq - itop(d)->irq_base;
189 + port_w32(itop(d), 1 << offset, GPIO_IRNCR);
192 +static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
194 + unsigned int offset = d->irq - itop(d)->irq_base;
196 + port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
197 + port_w32(itop(d), 1 << offset, GPIO_IRNCR);
200 +static struct irq_chip falcon_gpio_irq_chip;
201 +static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
203 + unsigned int offset = d->irq - itop(d)->irq_base;
204 + unsigned int mask = 1 << offset;
206 + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
209 + if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
210 + /* level triggered */
211 + port_w32_mask(itop(d), 0, mask, GPIO_IRNCFG);
212 + irq_set_chip_and_handler_name(d->irq,
213 + &falcon_gpio_irq_chip, handle_level_irq, "mux");
215 + /* edge triggered */
216 + port_w32_mask(itop(d), mask, 0, GPIO_IRNCFG);
217 + irq_set_chip_and_handler_name(d->irq,
218 + &falcon_gpio_irq_chip, handle_simple_irq, "mux");
221 + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
222 + port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
223 + port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR1);
225 + if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
226 + /* positive logic: rising edge, high level */
227 + port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
229 + /* negative logic: falling edge, low level */
230 + port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR0);
231 + port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR1);
234 + return gpio_direction_input(itop(d)->gpio_chip.base + offset);
237 +static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
239 + struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
240 + unsigned long irncr;
243 + /* acknowledge interrupt */
244 + irncr = port_r32(gpio_port, GPIO_IRNCR);
245 + port_w32(gpio_port, irncr, GPIO_IRNCR);
247 + desc->irq_data.chip->irq_ack(&desc->irq_data);
249 + for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
250 + generic_handle_irq(gpio_port->irq_base + offset);
253 +static int falcon_gpio_irq_map(struct irq_domain *d, unsigned int irq,
254 + irq_hw_number_t hw)
256 + struct falcon_gpio_port *port = d->host_data;
258 + irq_set_chip_and_handler_name(irq, &falcon_gpio_irq_chip,
259 + handle_simple_irq, "mux");
260 + irq_set_chip_data(irq, port);
262 + /* set to negative logic (falling edge, low level) */
263 + port_w32_mask(port, 0, 1 << hw, GPIO_EXINTCR0);
267 +static struct irq_chip falcon_gpio_irq_chip = {
268 + .name = "gpio_irq_mux",
269 + .irq_mask = falcon_gpio_disable_irq,
270 + .irq_unmask = falcon_gpio_enable_irq,
271 + .irq_ack = falcon_gpio_ack_irq,
272 + .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
273 + .irq_set_type = falcon_gpio_irq_type,
276 +static const struct irq_domain_ops irq_domain_ops = {
277 + .xlate = irq_domain_xlate_onetwocell,
278 + .map = falcon_gpio_irq_map,
281 +static struct irqaction gpio_cascade = {
282 + .handler = no_action,
283 + .flags = IRQF_DISABLED,
284 + .name = "gpio_cascade",
287 +static int falcon_gpio_probe(struct platform_device *pdev)
289 + struct pinctrl_gpio_range *gpio_range;
290 + struct device_node *node = pdev->dev.of_node;
291 + const __be32 *bank = of_get_property(node, "lantiq,bank", NULL);
292 + struct falcon_gpio_port *gpio_port;
293 + struct resource *gpiores, irqres;
296 + if (!bank || *bank >= MAX_PORTS)
299 + size = pinctrl_falcon_get_range_size(*bank);
301 + dev_err(&pdev->dev, "pad not loaded for bank %d\n", *bank);
305 + gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
309 + gpio_range = devm_kzalloc(&pdev->dev, sizeof(struct pinctrl_gpio_range),
314 + gpio_port = devm_kzalloc(&pdev->dev, sizeof(struct falcon_gpio_port),
318 + snprintf(gpio_port->name, 6, "gpio%d", *bank);
319 + gpio_port->gpio_chip.label = gpio_port->name;
320 + gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
321 + gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
322 + gpio_port->gpio_chip.get = falcon_gpio_get;
323 + gpio_port->gpio_chip.set = falcon_gpio_set;
324 + gpio_port->gpio_chip.request = falcon_gpio_request;
325 + gpio_port->gpio_chip.free = falcon_gpio_free;
326 + gpio_port->gpio_chip.base = -1;
327 + gpio_port->gpio_chip.ngpio = size;
328 + gpio_port->gpio_chip.dev = &pdev->dev;
330 + gpio_port->port = devm_request_and_ioremap(&pdev->dev, gpiores);
331 + if (!gpio_port->port) {
332 + dev_err(&pdev->dev, "Could not map io ranges\n");
336 + gpio_port->clk = clk_get(&pdev->dev, NULL);
337 + if (IS_ERR(gpio_port->clk)) {
338 + dev_err(&pdev->dev, "Could not get clock\n");
339 + return PTR_ERR(gpio_port->clk);
341 + clk_enable(gpio_port->clk);
343 + if (of_irq_to_resource_table(node, &irqres, 1) == 1) {
344 + gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * *bank);
345 + gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
346 + gpio_port->chained_irq = irqres.start;
347 + irq_domain_add_legacy(node, size, gpio_port->irq_base, 0,
348 + &irq_domain_ops, gpio_port);
349 + setup_irq(irqres.start, &gpio_cascade);
350 + irq_set_handler_data(irqres.start, gpio_port);
351 + irq_set_chained_handler(irqres.start, falcon_gpio_irq_handler);
354 + ret = gpiochip_add(&gpio_port->gpio_chip);
356 + platform_set_drvdata(pdev, gpio_port);
358 + gpio_range->name = "FALCON GPIO";
359 + gpio_range->id = *bank;
360 + gpio_range->base = gpio_port->gpio_chip.base;
361 + gpio_range->npins = gpio_port->gpio_chip.ngpio;
362 + gpio_range->gc = &gpio_port->gpio_chip;
363 + pinctrl_falcon_add_gpio_range(gpio_range);
368 +static const struct of_device_id falcon_gpio_match[] = {
369 + { .compatible = "lantiq,gpio-falcon" },
372 +MODULE_DEVICE_TABLE(of, falcon_gpio_match);
374 +static struct platform_driver falcon_gpio_driver = {
375 + .probe = falcon_gpio_probe,
377 + .name = "gpio-falcon",
378 + .owner = THIS_MODULE,
379 + .of_match_table = falcon_gpio_match,
383 +int __init falcon_gpio_init(void)
387 + pr_info("FALC(tm) ON GPIO Driver, (C) 2012 Lantiq Deutschland Gmbh\n");
388 + ret = platform_driver_register(&falcon_gpio_driver);
390 + pr_err("falcon_gpio: Error registering platform driver!");
394 +subsys_initcall(falcon_gpio_init);