1 From 51130632baa3dfabca87ce5d5b57376a7927b7d3 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Fri, 3 Aug 2012 10:27:25 +0200
4 Subject: [PATCH 21/22] owrt: lantiq: add atm hack
7 arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
8 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
9 arch/mips/lantiq/irq.c | 2 +
10 arch/mips/mm/cache.c | 2 +
11 include/uapi/linux/atm.h | 6 +
12 net/atm/common.c | 6 +
14 7 files changed, 416 insertions(+), 1 deletion(-)
15 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
16 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
18 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_atm.h b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
20 index 0000000..bf045a9
22 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
24 +/******************************************************************************
26 +** FILE NAME : ifx_atm.h
30 +** DATE : 17 Jun 2009
32 +** DESCRIPTION : Global ATM driver header file
33 +** COPYRIGHT : Copyright (c) 2006
34 +** Infineon Technologies AG
35 +** Am Campeon 1-12, 85579 Neubiberg, Germany
37 +** This program is free software; you can redistribute it and/or modify
38 +** it under the terms of the GNU General Public License as published by
39 +** the Free Software Foundation; either version 2 of the License, or
40 +** (at your option) any later version.
43 +** $Date $Author $Comment
44 +** 07 JUL 2009 Xu Liang Init Version
45 +*******************************************************************************/
53 + \defgroup IFX_ATM UEIP Project - ATM driver module
54 + \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
58 + \defgroup IFX_ATM_IOCTL IOCTL Commands
60 + \brief IOCTL Commands used by user application.
64 + \defgroup IFX_ATM_STRUCT Structures
66 + \brief Structures used by user application.
72 + \brief ATM driver header file
78 + * ####################################
80 + * ####################################
84 + \addtogroup IFX_ATM_STRUCT
93 + \struct atm_cell_ifEntry_t
94 + \brief Structure used for Cell Level MIB Counters.
96 + User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
99 + __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
100 + __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
101 + __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
102 + __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
103 + __u32 ifInErrors; /*!< counter of error ingress cells */
104 + __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
105 + __u32 ifOutErrors; /*!< counter of error egress cells */
106 +} atm_cell_ifEntry_t;
109 + \struct atm_aal5_ifEntry_t
110 + \brief Structure used for AAL5 Frame Level MIB Counters.
112 + User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
115 + __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
116 + __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
117 + __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
118 + __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
119 + __u32 ifInUcastPkts; /*!< counter of ingress packets */
120 + __u32 ifOutUcastPkts; /*!< counter of egress packets */
121 + __u32 ifInErrors; /*!< counter of error ingress packets */
122 + __u32 ifInDiscards; /*!< counter of dropped ingress packets */
123 + __u32 ifOutErros; /*!< counter of error egress packets */
124 + __u32 ifOutDiscards; /*!< counter of dropped egress packets */
125 +} atm_aal5_ifEntry_t;
128 + \struct atm_aal5_vcc_t
129 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
131 + This structure is a part of structure "atm_aal5_vcc_x_t".
134 + __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
135 + __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
136 + __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
140 + \struct atm_aal5_vcc_x_t
141 + \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
143 + User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
146 + int vpi; /*!< VPI of the VCC to get MIB counters */
147 + int vci; /*!< VCI of the VCC to get MIB counters */
148 + atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
156 + * ####################################
158 + * ####################################
162 + \addtogroup IFX_ATM_IOCTL
170 + \brief ATM IOCTL Magic Number
172 +#define PPE_ATM_IOC_MAGIC 'o'
174 + \brief ATM IOCTL Command - Get Cell Level MIB Counters
176 + This command is obsolete. User can get cell level MIB from DSL API.
177 + This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
179 +#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
181 + \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
183 + Get AAL5 packet counters.
184 + This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
186 +#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
188 + \brief ATM IOCTL Command - Get Per PVC MIB Counters
190 + Get AAL5 packet counters for each PVC.
191 + This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
193 +#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
195 + \brief Total Number of ATM IOCTL Commands
197 +#define PPE_ATM_IOC_MAXNR 3
204 + * ####################################
206 + * ####################################
210 +struct port_cell_info {
211 + unsigned int port_num;
212 + unsigned int tx_link_rate[2];
220 diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
222 index 0000000..698e5c3
224 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
226 +/******************************************************************************
228 +** FILE NAME : ifx_ptm.h
232 +** DATE : 17 Jun 2009
233 +** AUTHOR : Xu Liang
234 +** DESCRIPTION : Global PTM driver header file
235 +** COPYRIGHT : Copyright (c) 2006
236 +** Infineon Technologies AG
237 +** Am Campeon 1-12, 85579 Neubiberg, Germany
239 +** This program is free software; you can redistribute it and/or modify
240 +** it under the terms of the GNU General Public License as published by
241 +** the Free Software Foundation; either version 2 of the License, or
242 +** (at your option) any later version.
245 +** $Date $Author $Comment
246 +** 07 JUL 2009 Xu Liang Init Version
247 +*******************************************************************************/
255 + \defgroup IFX_PTM UEIP Project - PTM driver module
256 + \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
260 + \defgroup IFX_PTM_IOCTL IOCTL Commands
262 + \brief IOCTL Commands used by user application.
266 + \defgroup IFX_PTM_STRUCT Structures
268 + \brief Structures used by user application.
274 + \brief PTM driver header file
280 + * ####################################
282 + * ####################################
288 + * ####################################
290 + * ####################################
294 + \addtogroup IFX_PTM_IOCTL
302 + \brief PTM IOCTL Command - Get codeword MIB counters.
304 + This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
306 +#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
308 + \brief PTM IOCTL Command - Get packet MIB counters.
310 + This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
312 +#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
314 + \brief PTM IOCTL Command - Get firmware configuration (CRC).
316 + This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
318 +#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
320 + \brief PTM IOCTL Command - Set firmware configuration (CRC).
322 + This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
324 +#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
326 + \brief PTM IOCTL Command - Program priority value to TX queue mapping.
328 + This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
330 +#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
336 + \addtogroup IFX_PTM_STRUCT
345 + \typedef PTM_CW_IF_ENTRY_T
346 + \brief Wrapping of structure "ptm_cw_ifEntry_t".
349 + \struct ptm_cw_ifEntry_t
350 + \brief Structure used for CodeWord level MIB counters.
352 +typedef struct ptm_cw_ifEntry_t {
353 + uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
354 + uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
355 + uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
356 + uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
357 + uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
358 +} PTM_CW_IF_ENTRY_T;
361 + \typedef PTM_FRAME_MIB_T
362 + \brief Wrapping of structure "ptm_frame_mib_t".
365 + \struct ptm_frame_mib_t
366 + \brief Structure used for packet level MIB counters.
368 +typedef struct ptm_frame_mib_t {
369 + uint32_t RxCorrect; /*!< output, number of ingress packet */
370 + uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
371 + uint32_t RxDropped; /*!< output, number of dropped ingress packet */
372 + uint32_t TxSend; /*!< output, number of egress packet */
376 + \typedef IFX_PTM_CFG_T
377 + \brief Wrapping of structure "ptm_cfg_t".
381 + \brief Structure used for ETH/TC CRC configuration.
383 +typedef struct ptm_cfg_t {
384 + uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
385 + uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
386 + uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
387 + uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
388 + uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
389 + uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
390 + uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
394 + \typedef IFX_PTM_PRIO_Q_MAP_T
395 + \brief Wrapping of structure "ppe_prio_q_map".
398 + \struct ppe_prio_q_map
399 + \brief Structure used for Priority Value to TX Queue mapping.
401 +typedef struct ppe_prio_q_map {
404 + int vpi; // ignored in eth interface
405 + int vci; // ignored in eth interface
406 +} IFX_PTM_PRIO_Q_MAP_T;
413 + * ####################################
415 + * ####################################
419 +struct port_cell_info {
420 + unsigned int port_num;
421 + unsigned int tx_link_rate[2];
429 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
430 index 5119487..6d2c486 100644
431 --- a/arch/mips/lantiq/irq.c
432 +++ b/arch/mips/lantiq/irq.c
434 #include <linux/of_platform.h>
435 #include <linux/of_address.h>
436 #include <linux/of_irq.h>
437 +#include <linux/module.h>
439 #include <asm/bootinfo.h>
440 #include <asm/irq_cpu.h>
441 @@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
442 ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
443 ltq_icu_w32(im, BIT(offset), isr);
445 +EXPORT_SYMBOL(ltq_mask_and_ack_irq);
447 static void ltq_ack_irq(struct irq_data *d)
449 diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
450 index 07cec44..a3e3872 100644
451 --- a/arch/mips/mm/cache.c
452 +++ b/arch/mips/mm/cache.c
453 @@ -57,6 +57,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
454 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
456 EXPORT_SYMBOL(_dma_cache_wback_inv);
457 +EXPORT_SYMBOL(_dma_cache_wback);
458 +EXPORT_SYMBOL(_dma_cache_inv);
460 #endif /* CONFIG_DMA_NONCOHERENT */
462 diff --git a/include/uapi/linux/atm.h b/include/uapi/linux/atm.h
463 index 88399db..78c8bbc 100644
464 --- a/include/uapi/linux/atm.h
465 +++ b/include/uapi/linux/atm.h
468 #define ATM_ANYCLASS 5 /* compatible with everything */
470 +#define ATM_VBR_NRT ATM_VBR
471 +#define ATM_VBR_RT 6
472 +#define ATM_UBR_PLUS 7
475 #define ATM_MAX_PCR -1 /* maximum available PCR */
479 unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
480 int max_pcr; /* maximum PCR in cells per second */
481 diff --git a/net/atm/common.c b/net/atm/common.c
482 index 737bef5..959008d 100644
483 --- a/net/atm/common.c
484 +++ b/net/atm/common.c
485 @@ -62,11 +62,17 @@ static void vcc_remove_socket(struct sock *sk)
486 write_unlock_irq(&vcc_sklist_lock);
489 +struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
490 +EXPORT_SYMBOL(ifx_atm_alloc_tx);
492 static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
495 struct sock *sk = sk_atm(vcc);
497 + if (ifx_atm_alloc_tx != NULL)
498 + return ifx_atm_alloc_tx(vcc, size);
500 if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
501 pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
502 sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
503 diff --git a/net/atm/proc.c b/net/atm/proc.c
504 index 6ac35ff..3cea444 100644
507 @@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos)
508 static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
510 static const char *const class_name[] = {
511 - "off", "UBR", "CBR", "VBR", "ABR"};
512 + "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
513 static const char *const aal_name[] = {
514 "---", "1", "2", "3/4", /* 0- 3 */
515 "???", "5", "???", "???", /* 4- 7 */