1 From 997a8965db8417266bea3fbdcfa3e5655a1b52fa Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 9 Sep 2014 23:12:15 +0200
4 Subject: [PATCH 18/36] MTD: nand: lots of xrx200 fixes
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/mtd/nand/xway_nand.c | 63 ++++++++++++++++++++++++++++++++++++++++++
9 1 file changed, 63 insertions(+)
11 --- a/drivers/mtd/nand/xway_nand.c
12 +++ b/drivers/mtd/nand/xway_nand.c
14 #define NAND_CON_CSMUX (1 << 1)
15 #define NAND_CON_NANDM 1
17 +#define DANUBE_PCI_REG32( addr ) (*(volatile u32 *)(addr))
18 +#define PCI_CR_PR_OFFSET (KSEG1+0x1E105400)
19 +#define PCI_CR_PC_ARB (PCI_CR_PR_OFFSET + 0x0080)
21 static u32 xway_latchcmd;
24 + * req_mask provides a mechanism to prevent interference between
25 + * nand and pci (probably only relevant for the BT Home Hub 2B).
26 + * Setting it causes the corresponding pci req pins to be masked
27 + * during nand access, and also moves ebu locking from the read/write
28 + * functions to the chip select function to ensure that the whole
29 + * operation runs with interrupts disabled.
30 + * In addition it switches on some extra waiting in xway_cmd_ctrl().
31 + * This seems to be necessary if the ebu_cs1 pin has open-drain disabled,
32 + * which in turn seems to be necessary for the nor chip to be recognised
33 + * reliably, on a board (Home Hub 2B again) which has both nor and nand.
36 +static __be32 req_mask = 0;
38 static void xway_reset_chip(struct nand_chip *chip)
40 unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
41 @@ -86,12 +105,24 @@ static void xway_select_chip(struct mtd_
43 ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
44 ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
47 + /* Unmask all external PCI request */
48 + DANUBE_PCI_REG32(PCI_CR_PC_ARB) &= ~(req_mask << 16);
50 spin_unlock_irqrestore(&ebu_lock, csflags);
54 spin_lock_irqsave(&ebu_lock, csflags);
56 + /* Mask all external PCI request */
57 + DANUBE_PCI_REG32(PCI_CR_PC_ARB) |= (req_mask << 16);
60 ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
61 ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
66 @@ -103,6 +134,12 @@ static void xway_cmd_ctrl(struct mtd_inf
67 struct nand_chip *this = mtd->priv;
68 unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
71 + if (cmd != NAND_CMD_STATUS)
72 + ltq_ebu_w32(EBU_NAND_WAIT, 0); /* Clear nand ready */
76 if (ctrl & NAND_CTRL_CHANGE) {
78 xway_latchcmd = NAND_WRITE_CMD;
79 @@ -115,6 +152,24 @@ static void xway_cmd_ctrl(struct mtd_inf
80 while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
86 + * program and erase have their own busy handlers
87 + * status and sequential in needs no delay
90 + case NAND_CMD_ERASE1:
91 + case NAND_CMD_SEQIN:
92 + case NAND_CMD_STATUS:
93 + case NAND_CMD_READID:
97 + /* wait until command is processed */
98 + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD) == 0)
103 static int xway_dev_ready(struct mtd_info *mtd)
104 @@ -157,6 +212,8 @@ static int xway_nand_probe(struct platfo
106 struct nand_chip *this = platform_get_drvdata(pdev);
107 unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
108 + const __be32 *req_mask_ptr = of_get_property(pdev->dev.of_node,
110 const __be32 *cs = of_get_property(pdev->dev.of_node,
113 @@ -165,6 +222,12 @@ static int xway_nand_probe(struct platfo
114 if (cs && (*cs == 1))
115 cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
118 + * Load the PCI req lines to mask from the device tree. If the
119 + * property is not present, setting req_mask to 0 disables masking.
121 + req_mask = (req_mask_ptr ? *req_mask_ptr : 0);
123 /* setup the EBU to run in NAND mode on our base addr */
124 ltq_ebu_w32(CPHYSADDR(nandaddr)
125 | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);