1 From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 9 Sep 2014 22:45:34 +0200
4 Subject: [PATCH 28/36] NET: lantiq: various etop fixes
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
9 1 file changed, 389 insertions(+), 166 deletions(-)
11 --- a/drivers/net/ethernet/lantiq_etop.c
12 +++ b/drivers/net/ethernet/lantiq_etop.c
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
18 + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
21 #include <linux/kernel.h>
24 #include <linux/platform_device.h>
25 #include <linux/ethtool.h>
26 +#include <linux/if_vlan.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/module.h>
32 +#include <linux/clk.h>
33 +#include <linux/of_net.h>
34 +#include <linux/of_irq.h>
35 +#include <linux/of_platform.h>
37 #include <asm/checksum.h>
41 #include <lantiq_platform.h>
43 -#define LTQ_ETOP_MDIO 0x11804
44 +#define LTQ_ETOP_MDIO_ACC 0x11804
45 #define MDIO_REQUEST 0x80000000
46 #define MDIO_READ 0x40000000
47 #define MDIO_ADDR_MASK 0x1f
49 #define MDIO_REG_OFFSET 0x10
50 #define MDIO_VAL_MASK 0xffff
52 -#define PPE32_CGEN 0x800
53 -#define LQ_PPE32_ENET_MAC_CFG 0x1840
54 +#define LTQ_ETOP_MDIO_CFG 0x11800
55 +#define MDIO_CFG_MASK 0x6
57 +#define LTQ_ETOP_CFG 0x11808
58 +#define LTQ_ETOP_IGPLEN 0x11820
59 +#define LTQ_ETOP_MAC_CFG 0x11840
61 #define LTQ_ETOP_ENETS0 0x11850
62 #define LTQ_ETOP_MAC_DA0 0x1186C
63 #define LTQ_ETOP_MAC_DA1 0x11870
64 -#define LTQ_ETOP_CFG 0x16020
65 -#define LTQ_ETOP_IGPLEN 0x16080
67 +#define MAC_CFG_MASK 0xfff
68 +#define MAC_CFG_CGEN (1 << 11)
69 +#define MAC_CFG_DUPLEX (1 << 2)
70 +#define MAC_CFG_SPEED (1 << 1)
71 +#define MAC_CFG_LINK (1 << 0)
73 #define MAX_DMA_CHAN 0x8
74 #define MAX_DMA_CRC_LEN 0x4
75 #define MAX_DMA_DATA_LEN 0x600
77 #define ETOP_FTCU BIT(28)
78 -#define ETOP_MII_MASK 0xf
79 -#define ETOP_MII_NORMAL 0xd
80 -#define ETOP_MII_REVERSE 0xe
81 #define ETOP_PLEN_UNDER 0x40
82 -#define ETOP_CGEN 0x800
83 +#define ETOP_CFG_MII0 0x01
85 -/* use 2 static channels for TX/RX */
86 -#define LTQ_ETOP_TX_CHANNEL 1
87 -#define LTQ_ETOP_RX_CHANNEL 6
88 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
89 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
90 +#define ETOP_CFG_MASK 0xfff
91 +#define ETOP_CFG_FEN0 (1 << 8)
92 +#define ETOP_CFG_SEN0 (1 << 6)
93 +#define ETOP_CFG_OFF1 (1 << 3)
94 +#define ETOP_CFG_REMII0 (1 << 1)
95 +#define ETOP_CFG_OFF0 (1 << 0)
97 +#define LTQ_GBIT_MDIO_CTL 0xCC
98 +#define LTQ_GBIT_MDIO_DATA 0xd0
99 +#define LTQ_GBIT_GCTL0 0x68
100 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c
101 +#define LTQ_GBIT_P0_CTL 0x4
102 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8
103 +#define LTQ_GBIT_RGMII_CTL 0x78
105 +#define PMAC_HD_CTL_AS (1 << 19)
106 +#define PMAC_HD_CTL_RXSH (1 << 22)
108 +/* Switch Enable (0=disable, 1=enable) */
109 +#define GCTL0_SE 0x80000000
110 +/* Disable MDIO auto polling (0=disable, 1=enable) */
111 +#define PX_CTL_DMDIO 0x00400000
113 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
114 +#define MDC_CLOCK_MASK 0xff000000
115 +#define MDC_CLOCK_OFFSET 24
117 +/* register information for the gbit's MDIO bus */
118 +#define MDIO_XR9_REQUEST 0x00008000
119 +#define MDIO_XR9_READ 0x00000800
120 +#define MDIO_XR9_WRITE 0x00000400
121 +#define MDIO_XR9_REG_MASK 0x1f
122 +#define MDIO_XR9_ADDR_MASK 0x1f
123 +#define MDIO_XR9_RD_MASK 0xffff
124 +#define MDIO_XR9_REG_OFFSET 0
125 +#define MDIO_XR9_ADDR_OFFSET 5
126 +#define MDIO_XR9_WR_OFFSET 16
128 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
129 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
131 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
132 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
133 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
134 #define ltq_etop_w32_mask(x, y, z) \
135 ltq_w32_mask(x, y, ltq_etop_membase + (z))
137 -#define DRV_VERSION "1.0"
138 +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
139 +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
140 +#define ltq_gbit_w32_mask(x, y, z) \
141 + ltq_w32_mask(x, y, ltq_gbit_membase + (z))
143 +#define DRV_VERSION "1.2"
145 static void __iomem *ltq_etop_membase;
146 +static void __iomem *ltq_gbit_membase;
148 struct ltq_etop_chan {
152 struct net_device *netdev;
153 struct napi_struct napi;
154 struct ltq_dma_channel dma;
155 @@ -98,22 +150,35 @@ struct ltq_etop_chan {
156 struct ltq_etop_priv {
157 struct net_device *netdev;
158 struct platform_device *pdev;
159 - struct ltq_eth_data *pldata;
160 struct resource *res;
162 struct mii_bus *mii_bus;
163 struct phy_device *phydev;
165 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
166 - int tx_free[MAX_DMA_CHAN >> 1];
167 + struct ltq_etop_chan txch;
168 + struct ltq_etop_chan rxch;
178 + struct clk *clk_ppe;
179 + struct clk *clk_switch;
180 + struct clk *clk_ephy;
181 + struct clk *clk_ephycgu;
184 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
185 + int phy_reg, u16 phy_data);
188 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
190 - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
191 + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
192 if (!ch->skb[ch->dma.desc])
194 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
195 @@ -148,8 +213,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan
196 spin_unlock_irqrestore(&priv->lock, flags);
199 + skb->dev = ch->netdev;
200 skb->protocol = eth_type_trans(skb, ch->netdev);
201 netif_receive_skb(skb);
202 + ch->netdev->stats.rx_packets++;
203 + ch->netdev->stats.rx_bytes += len;
207 @@ -157,8 +225,10 @@ ltq_etop_poll_rx(struct napi_struct *nap
209 struct ltq_etop_chan *ch = container_of(napi,
210 struct ltq_etop_chan, napi);
211 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
214 + unsigned long flags;
216 while ((rx < budget) && !complete) {
217 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
218 @@ -172,7 +242,9 @@ ltq_etop_poll_rx(struct napi_struct *nap
220 if (complete || !rx) {
221 napi_complete(&ch->napi);
222 + spin_lock_irqsave(&priv->lock, flags);
223 ltq_dma_ack_irq(&ch->dma);
224 + spin_unlock_irqrestore(&priv->lock, flags);
228 @@ -184,12 +256,14 @@ ltq_etop_poll_tx(struct napi_struct *nap
229 container_of(napi, struct ltq_etop_chan, napi);
230 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
231 struct netdev_queue *txq =
232 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
233 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
236 spin_lock_irqsave(&priv->lock, flags);
237 while ((ch->dma.desc_base[ch->tx_free].ctl &
238 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
239 + ch->netdev->stats.tx_packets++;
240 + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
241 dev_kfree_skb_any(ch->skb[ch->tx_free]);
242 ch->skb[ch->tx_free] = NULL;
243 memset(&ch->dma.desc_base[ch->tx_free], 0,
244 @@ -202,7 +276,9 @@ ltq_etop_poll_tx(struct napi_struct *nap
245 if (netif_tx_queue_stopped(txq))
246 netif_tx_start_queue(txq);
247 napi_complete(&ch->napi);
248 + spin_lock_irqsave(&priv->lock, flags);
249 ltq_dma_ack_irq(&ch->dma);
250 + spin_unlock_irqrestore(&priv->lock, flags);
254 @@ -210,9 +286,10 @@ static irqreturn_t
255 ltq_etop_dma_irq(int irq, void *_priv)
257 struct ltq_etop_priv *priv = _priv;
258 - int ch = irq - LTQ_DMA_CH0_INT;
260 - napi_schedule(&priv->ch[ch].napi);
261 + if (irq == priv->txch.dma.irq)
262 + napi_schedule(&priv->txch.napi);
264 + napi_schedule(&priv->rxch.napi);
268 @@ -224,7 +301,7 @@ ltq_etop_free_channel(struct net_device
269 ltq_dma_free(&ch->dma);
271 free_irq(ch->dma.irq, priv);
272 - if (IS_RX(ch->idx)) {
273 + if (ch == &priv->txch) {
275 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
276 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
277 @@ -235,65 +312,133 @@ static void
278 ltq_etop_hw_exit(struct net_device *dev)
280 struct ltq_etop_priv *priv = netdev_priv(dev);
283 - ltq_pmu_disable(PMU_PPE);
284 - for (i = 0; i < MAX_DMA_CHAN; i++)
285 - if (IS_TX(i) || IS_RX(i))
286 - ltq_etop_free_channel(dev, &priv->ch[i]);
287 + clk_disable(priv->clk_ppe);
289 + if (of_machine_is_compatible("lantiq,ar9"))
290 + clk_disable(priv->clk_switch);
292 + if (of_machine_is_compatible("lantiq,ase")) {
293 + clk_disable(priv->clk_ephy);
294 + clk_disable(priv->clk_ephycgu);
297 + ltq_etop_free_channel(dev, &priv->txch);
298 + ltq_etop_free_channel(dev, &priv->rxch);
302 +ltq_etop_gbit_init(struct net_device *dev)
304 + struct ltq_etop_priv *priv = netdev_priv(dev);
306 + clk_enable(priv->clk_switch);
308 + /* enable gbit port0 on the SoC */
309 + ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
311 + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
312 + /* disable MDIO auto polling mode */
313 + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
314 + /* set 1522 packet size */
315 + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
316 + /* disable pmac & dmac headers */
317 + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
318 + LTQ_GBIT_PMAC_HD_CTL);
319 + /* Due to traffic halt when burst length 8,
320 + replace default IPG value with 0x3B */
321 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
322 + /* set mdc clock to 2.5 MHz */
323 + ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
324 + LTQ_GBIT_RGMII_CTL);
328 ltq_etop_hw_init(struct net_device *dev)
330 struct ltq_etop_priv *priv = netdev_priv(dev);
332 + int mii_mode = priv->mii_mode;
334 - ltq_pmu_enable(PMU_PPE);
335 + clk_enable(priv->clk_ppe);
337 + if (of_machine_is_compatible("lantiq,ar9")) {
338 + ltq_etop_gbit_init(dev);
339 + /* force the etops link to the gbit to MII */
340 + mii_mode = PHY_INTERFACE_MODE_MII;
342 + ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
343 + ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
344 + MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
346 - switch (priv->pldata->mii_mode) {
347 + switch (mii_mode) {
348 case PHY_INTERFACE_MODE_RMII:
349 - ltq_etop_w32_mask(ETOP_MII_MASK,
350 - ETOP_MII_REVERSE, LTQ_ETOP_CFG);
351 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
352 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
355 case PHY_INTERFACE_MODE_MII:
356 - ltq_etop_w32_mask(ETOP_MII_MASK,
357 - ETOP_MII_NORMAL, LTQ_ETOP_CFG);
358 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
359 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
363 + if (of_machine_is_compatible("lantiq,ase")) {
364 + clk_enable(priv->clk_ephy);
365 + /* disable external MII */
366 + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
367 + /* enable clock for internal PHY */
368 + clk_enable(priv->clk_ephycgu);
369 + /* we need to write this magic to the internal phy to
371 + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
372 + pr_info("Selected EPHY mode\n");
375 netdev_err(dev, "unknown mii mode %d\n",
376 - priv->pldata->mii_mode);
381 - /* enable crc generation */
382 - ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
387 +ltq_etop_dma_init(struct net_device *dev)
389 + struct ltq_etop_priv *priv = netdev_priv(dev);
390 + int tx = priv->tx_irq - LTQ_DMA_ETOP;
391 + int rx = priv->rx_irq - LTQ_DMA_ETOP;
394 ltq_dma_init_port(DMA_PORT_ETOP);
396 - for (i = 0; i < MAX_DMA_CHAN; i++) {
397 - int irq = LTQ_DMA_CH0_INT + i;
398 - struct ltq_etop_chan *ch = &priv->ch[i];
400 - ch->idx = ch->dma.nr = i;
403 - ltq_dma_alloc_tx(&ch->dma);
404 - request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
405 - } else if (IS_RX(i)) {
406 - ltq_dma_alloc_rx(&ch->dma);
407 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
409 - if (ltq_etop_alloc_skb(ch))
412 - request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
413 + priv->txch.dma.nr = tx;
414 + ltq_dma_alloc_tx(&priv->txch.dma);
415 + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
417 + netdev_err(dev, "failed to allocate tx irq\n");
420 + priv->txch.dma.irq = priv->tx_irq;
422 + priv->rxch.dma.nr = rx;
423 + ltq_dma_alloc_rx(&priv->rxch.dma);
424 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
425 + priv->rxch.dma.desc++) {
426 + if (ltq_etop_alloc_skb(&priv->rxch)) {
427 + netdev_err(dev, "failed to allocate skbs\n");
434 + priv->rxch.dma.desc = 0;
435 + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
437 + netdev_err(dev, "failed to allocate rx irq\n");
439 + priv->rxch.dma.irq = priv->rx_irq;
445 @@ -309,7 +454,10 @@ ltq_etop_get_settings(struct net_device
447 struct ltq_etop_priv *priv = netdev_priv(dev);
449 - return phy_ethtool_gset(priv->phydev, cmd);
451 + return phy_ethtool_gset(priv->phydev, cmd);
457 @@ -317,7 +465,10 @@ ltq_etop_set_settings(struct net_device
459 struct ltq_etop_priv *priv = netdev_priv(dev);
461 - return phy_ethtool_sset(priv->phydev, cmd);
463 + return phy_ethtool_sset(priv->phydev, cmd);
469 @@ -325,7 +476,10 @@ ltq_etop_nway_reset(struct net_device *d
471 struct ltq_etop_priv *priv = netdev_priv(dev);
473 - return phy_start_aneg(priv->phydev);
475 + return phy_start_aneg(priv->phydev);
480 static const struct ethtool_ops ltq_etop_ethtool_ops = {
481 @@ -336,6 +490,39 @@ static const struct ethtool_ops ltq_etop
485 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
486 + int phy_reg, u16 phy_data)
488 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
489 + (phy_data << MDIO_XR9_WR_OFFSET) |
490 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
491 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
493 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
495 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
496 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
502 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
504 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
505 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
506 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
508 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
510 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
511 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
513 + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
518 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
520 u32 val = MDIO_REQUEST |
521 @@ -343,9 +530,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
522 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
525 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
526 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
528 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
529 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
533 @@ -356,12 +543,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
534 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
535 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
537 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
538 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
540 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
541 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
542 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
543 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
545 - val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
546 + val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
550 @@ -376,14 +563,18 @@ ltq_etop_mdio_probe(struct net_device *d
552 struct ltq_etop_priv *priv = netdev_priv(dev);
553 struct phy_device *phydev = NULL;
555 + u32 phy_supported = (SUPPORTED_10baseT_Half
556 + | SUPPORTED_10baseT_Full
557 + | SUPPORTED_100baseT_Half
558 + | SUPPORTED_100baseT_Full
559 + | SUPPORTED_Autoneg
563 - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
564 - if (priv->mii_bus->phy_map[phy_addr]) {
565 - phydev = priv->mii_bus->phy_map[phy_addr];
569 + if (of_machine_is_compatible("lantiq,ase"))
570 + phydev = priv->mii_bus->phy_map[8];
572 + phydev = priv->mii_bus->phy_map[0];
575 netdev_err(dev, "no PHY found\n");
576 @@ -391,21 +582,18 @@ ltq_etop_mdio_probe(struct net_device *d
579 phydev = phy_connect(dev, dev_name(&phydev->dev),
580 - <q_etop_mdio_link, priv->pldata->mii_mode);
581 + <q_etop_mdio_link, priv->mii_mode);
583 if (IS_ERR(phydev)) {
584 netdev_err(dev, "Could not attach to PHY\n");
585 return PTR_ERR(phydev);
588 - phydev->supported &= (SUPPORTED_10baseT_Half
589 - | SUPPORTED_10baseT_Full
590 - | SUPPORTED_100baseT_Half
591 - | SUPPORTED_100baseT_Full
592 - | SUPPORTED_Autoneg
595 + if (of_machine_is_compatible("lantiq,ar9"))
596 + phy_supported |= SUPPORTED_1000baseT_Half
597 + | SUPPORTED_1000baseT_Full;
599 + phydev->supported &= phy_supported;
600 phydev->advertising = phydev->supported;
601 priv->phydev = phydev;
602 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
603 @@ -430,8 +618,13 @@ ltq_etop_mdio_init(struct net_device *de
606 priv->mii_bus->priv = dev;
607 - priv->mii_bus->read = ltq_etop_mdio_rd;
608 - priv->mii_bus->write = ltq_etop_mdio_wr;
609 + if (of_machine_is_compatible("lantiq,ar9")) {
610 + priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
611 + priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
613 + priv->mii_bus->read = ltq_etop_mdio_rd;
614 + priv->mii_bus->write = ltq_etop_mdio_wr;
616 priv->mii_bus->name = "ltq_mii";
617 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
618 priv->pdev->name, priv->pdev->id);
619 @@ -480,17 +673,19 @@ static int
620 ltq_etop_open(struct net_device *dev)
622 struct ltq_etop_priv *priv = netdev_priv(dev);
624 + unsigned long flags;
626 - for (i = 0; i < MAX_DMA_CHAN; i++) {
627 - struct ltq_etop_chan *ch = &priv->ch[i];
628 + napi_enable(&priv->txch.napi);
629 + napi_enable(&priv->rxch.napi);
631 + spin_lock_irqsave(&priv->lock, flags);
632 + ltq_dma_open(&priv->txch.dma);
633 + ltq_dma_open(&priv->rxch.dma);
634 + spin_unlock_irqrestore(&priv->lock, flags);
637 + phy_start(priv->phydev);
639 - if (!IS_TX(i) && (!IS_RX(i)))
641 - ltq_dma_open(&ch->dma);
642 - napi_enable(&ch->napi);
644 - phy_start(priv->phydev);
645 netif_tx_start_all_queues(dev);
648 @@ -499,18 +694,19 @@ static int
649 ltq_etop_stop(struct net_device *dev)
651 struct ltq_etop_priv *priv = netdev_priv(dev);
653 + unsigned long flags;
655 netif_tx_stop_all_queues(dev);
656 - phy_stop(priv->phydev);
657 - for (i = 0; i < MAX_DMA_CHAN; i++) {
658 - struct ltq_etop_chan *ch = &priv->ch[i];
660 - if (!IS_RX(i) && !IS_TX(i))
662 - napi_disable(&ch->napi);
663 - ltq_dma_close(&ch->dma);
666 + phy_stop(priv->phydev);
667 + napi_disable(&priv->txch.napi);
668 + napi_disable(&priv->rxch.napi);
670 + spin_lock_irqsave(&priv->lock, flags);
671 + ltq_dma_close(&priv->txch.dma);
672 + ltq_dma_close(&priv->rxch.dma);
673 + spin_unlock_irqrestore(&priv->lock, flags);
678 @@ -520,16 +716,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
679 int queue = skb_get_queue_mapping(skb);
680 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
681 struct ltq_etop_priv *priv = netdev_priv(dev);
682 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
683 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
685 + struct ltq_dma_desc *desc =
686 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
691 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
693 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
694 - dev_kfree_skb_any(skb);
695 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
696 + priv->txch.skb[priv->txch.dma.desc]) {
697 netdev_err(dev, "tx ring full\n");
698 netif_tx_stop_queue(txq);
699 return NETDEV_TX_BUSY;
700 @@ -537,7 +733,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
702 /* dma needs to start on a 16 byte aligned address */
703 byte_offset = CPHYSADDR(skb->data) % 16;
704 - ch->skb[ch->dma.desc] = skb;
705 + priv->txch.skb[priv->txch.dma.desc] = skb;
707 dev->trans_start = jiffies;
709 @@ -547,11 +743,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
711 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
712 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
714 - ch->dma.desc %= LTQ_DESC_NUM;
715 + priv->txch.dma.desc++;
716 + priv->txch.dma.desc %= LTQ_DESC_NUM;
717 spin_unlock_irqrestore(&priv->lock, flags);
719 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
720 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
721 netif_tx_stop_queue(txq);
724 @@ -566,8 +762,10 @@ ltq_etop_change_mtu(struct net_device *d
725 struct ltq_etop_priv *priv = netdev_priv(dev);
728 + int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
730 spin_lock_irqsave(&priv->lock, flags);
731 - ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
732 + ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max,
734 spin_unlock_irqrestore(&priv->lock, flags);
736 @@ -638,6 +836,9 @@ ltq_etop_init(struct net_device *dev)
739 ltq_etop_change_mtu(dev, 1500);
740 + err = ltq_etop_dma_init(dev);
744 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
745 if (!is_valid_ether_addr(mac.sa_data)) {
746 @@ -655,9 +856,10 @@ ltq_etop_init(struct net_device *dev)
747 dev->addr_assign_type = NET_ADDR_RANDOM;
749 ltq_etop_set_multicast_list(dev);
750 - err = ltq_etop_mdio_init(dev);
753 + if (!ltq_etop_mdio_init(dev))
754 + dev->ethtool_ops = <q_etop_ethtool_ops;
756 + pr_warn("etop: mdio probe failed\n");;
760 @@ -677,6 +879,9 @@ ltq_etop_tx_timeout(struct net_device *d
761 err = ltq_etop_hw_init(dev);
764 + err = ltq_etop_dma_init(dev);
767 dev->trans_start = jiffies;
768 netif_wake_queue(dev);
770 @@ -700,14 +905,18 @@ static const struct net_device_ops ltq_e
771 .ndo_tx_timeout = ltq_etop_tx_timeout,
775 -ltq_etop_probe(struct platform_device *pdev)
776 +static int ltq_etop_probe(struct platform_device *pdev)
778 struct net_device *dev;
779 struct ltq_etop_priv *priv;
780 - struct resource *res;
781 + struct resource *res, *gbit_res, irqres[2];
785 + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
787 + dev_err(&pdev->dev, "failed to get etop irqs\n");
791 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
793 @@ -733,30 +942,58 @@ ltq_etop_probe(struct platform_device *p
797 - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
801 + if (of_machine_is_compatible("lantiq,ar9")) {
802 + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
804 + dev_err(&pdev->dev, "failed to get gbit resource\n");
808 + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
809 + gbit_res->start, resource_size(gbit_res));
810 + if (!ltq_gbit_membase) {
811 + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
818 + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
819 strcpy(dev->name, "eth%d");
820 dev->netdev_ops = <q_eth_netdev_ops;
821 - dev->ethtool_ops = <q_etop_ethtool_ops;
822 priv = netdev_priv(dev);
825 - priv->pldata = dev_get_platdata(&pdev->dev);
827 + priv->tx_irq = irqres[0].start;
828 + priv->rx_irq = irqres[1].start;
829 + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
830 + of_get_mac_address_mtd(pdev->dev.of_node, priv->mac);
832 + priv->clk_ppe = clk_get(&pdev->dev, NULL);
833 + if (IS_ERR(priv->clk_ppe))
834 + return PTR_ERR(priv->clk_ppe);
835 + if (of_machine_is_compatible("lantiq,ar9")) {
836 + priv->clk_switch = clk_get(&pdev->dev, "switch");
837 + if (IS_ERR(priv->clk_switch))
838 + return PTR_ERR(priv->clk_switch);
840 + if (of_machine_is_compatible("lantiq,ase")) {
841 + priv->clk_ephy = clk_get(&pdev->dev, "ephy");
842 + if (IS_ERR(priv->clk_ephy))
843 + return PTR_ERR(priv->clk_ephy);
844 + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
845 + if (IS_ERR(priv->clk_ephycgu))
846 + return PTR_ERR(priv->clk_ephycgu);
849 spin_lock_init(&priv->lock);
851 - for (i = 0; i < MAX_DMA_CHAN; i++) {
853 - netif_napi_add(dev, &priv->ch[i].napi,
854 - ltq_etop_poll_tx, 8);
856 - netif_napi_add(dev, &priv->ch[i].napi,
857 - ltq_etop_poll_rx, 32);
858 - priv->ch[i].netdev = dev;
860 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
861 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
862 + priv->txch.netdev = dev;
863 + priv->rxch.netdev = dev;
865 err = register_netdev(dev);
867 @@ -785,31 +1022,22 @@ ltq_etop_remove(struct platform_device *
871 +static const struct of_device_id ltq_etop_match[] = {
872 + { .compatible = "lantiq,etop-xway" },
875 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
877 static struct platform_driver ltq_mii_driver = {
878 + .probe = ltq_etop_probe,
879 .remove = ltq_etop_remove,
882 + .of_match_table = ltq_etop_match,
889 - int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
892 - pr_err("ltq_etop: Error registering platform driver!");
899 - platform_driver_unregister(<q_mii_driver);
902 -module_init(init_ltq_etop);
903 -module_exit(exit_ltq_etop);
904 +module_platform_driver(ltq_mii_driver);
906 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
907 MODULE_DESCRIPTION("Lantiq SoC ETOP");