1 From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 7 Aug 2014 18:30:56 +0200
4 Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++
9 arch/mips/lantiq/xway/Makefile | 2 +-
10 arch/mips/lantiq/xway/timer.c | 845 ++++++++++++++++++++++
11 3 files changed, 1001 insertions(+), 1 deletion(-)
12 create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
13 create mode 100644 arch/mips/lantiq/xway/timer.c
16 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
18 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
19 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
22 +/******************************************************************************
23 + Copyright (c) 2002, Infineon Technologies. All rights reserved.
26 + Because the program is licensed free of charge, there is no warranty for
27 + the program, to the extent permitted by applicable law. Except when
28 + otherwise stated in writing the copyright holders and/or other parties
29 + provide the program "as is" without warranty of any kind, either
30 + expressed or implied, including, but not limited to, the implied
31 + warranties of merchantability and fitness for a particular purpose. The
32 + entire risk as to the quality and performance of the program is with
33 + you. should the program prove defective, you assume the cost of all
34 + necessary servicing, repair or correction.
36 + In no event unless required by applicable law or agreed to in writing
37 + will any copyright holder, or any other party who may modify and/or
38 + redistribute the program as permitted above, be liable to you for
39 + damages, including any general, special, incidental or consequential
40 + damages arising out of the use or inability to use the program
41 + (including but not limited to loss of data or data being rendered
42 + inaccurate or losses sustained by you or third parties or a failure of
43 + the program to operate with any other programs), even if such holder or
44 + other party has been advised of the possibility of such damages.
45 +******************************************************************************/
49 + * ####################################
51 + * ####################################
55 + * Available Timer/Counter Index
57 +#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
58 +#define TIMER_ANY 0x00
59 +#define TIMER1A TIMER(1, 0)
60 +#define TIMER1B TIMER(1, 1)
61 +#define TIMER2A TIMER(2, 0)
62 +#define TIMER2B TIMER(2, 1)
63 +#define TIMER3A TIMER(3, 0)
64 +#define TIMER3B TIMER(3, 1)
67 + * Flag of Timer/Counter
68 + * These flags specify the way in which timer is configured.
70 +/* Bit size of timer/counter. */
71 +#define TIMER_FLAG_16BIT 0x0000
72 +#define TIMER_FLAG_32BIT 0x0001
73 +/* Switch between timer and counter. */
74 +#define TIMER_FLAG_TIMER 0x0000
75 +#define TIMER_FLAG_COUNTER 0x0002
76 +/* Stop or continue when overflowing/underflowing. */
77 +#define TIMER_FLAG_ONCE 0x0000
78 +#define TIMER_FLAG_CYCLIC 0x0004
79 +/* Count up or counter down. */
80 +#define TIMER_FLAG_UP 0x0000
81 +#define TIMER_FLAG_DOWN 0x0008
82 +/* Count on specific level or edge. */
83 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
84 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
85 +#define TIMER_FLAG_RISE_EDGE 0x0010
86 +#define TIMER_FLAG_FALL_EDGE 0x0020
87 +#define TIMER_FLAG_ANY_EDGE 0x0030
88 +/* Signal is syncronous to module clock or not. */
89 +#define TIMER_FLAG_UNSYNC 0x0000
90 +#define TIMER_FLAG_SYNC 0x0080
91 +/* Different interrupt handle type. */
92 +#define TIMER_FLAG_NO_HANDLE 0x0000
93 +#if defined(__KERNEL__)
94 + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
95 +#endif // defined(__KERNEL__)
96 +#define TIMER_FLAG_SIGNAL 0x0300
97 +/* Internal clock source or external clock source */
98 +#define TIMER_FLAG_INT_SRC 0x0000
99 +#define TIMER_FLAG_EXT_SRC 0x1000
105 +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
106 +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
107 +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
108 +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
109 +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
110 +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
111 +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
112 +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
115 + * Data Type Used to Call ioctl
117 +struct gptu_ioctl_param {
118 + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
119 + * GPTU_SET_COUNTER, this field is ID of expected *
120 + * timer/counter. If it's zero, a timer/counter would *
121 + * be dynamically allocated and ID would be stored in *
123 + * In command GPTU_GET_COUNT_VALUE, this field is *
125 + * In other command, this field is ID of timer/counter *
127 + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
128 + * GPTU_SET_COUNTER, this field contains flags to *
129 + * specify how to configure timer/counter. *
130 + * In command GPTU_START_TIMER, zero indicate start *
131 + * and non-zero indicate resume timer/counter. *
132 + * In other command, this field is ignored. */
133 + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
134 + * init/reload value. *
135 + * In command GPTU_SET_TIMER, this field contains *
136 + * frequency (0.001Hz) of timer. *
137 + * In command GPTU_GET_COUNT_VALUE, current count *
138 + * value would be stored in this field. *
139 + * In command GPTU_CALCULATE_DIVIDER, this field *
140 + * contains frequency wanted, and after calculation, *
141 + * divider would be stored in this field to overwrite *
143 + * In other command, this field is ignored. */
144 + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
145 + * if signal is required, this field contains process *
146 + * ID to which signal would be sent. *
147 + * In other command, this field is ignored. */
148 + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
149 + * if signal is required, this field contains signal *
150 + * number which would be sent. *
151 + * In other command, this field is ignored. */
155 + * ####################################
157 + * ####################################
159 +typedef void (*timer_callback)(unsigned long arg);
161 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
162 +extern int lq_free_timer(unsigned int);
163 +extern int lq_start_timer(unsigned int, int);
164 +extern int lq_stop_timer(unsigned int);
165 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
166 +extern int lq_get_count_value(unsigned int, unsigned long *);
167 +extern u32 lq_cal_divider(unsigned long);
168 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
169 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
170 + u32 reload, unsigned long arg1, unsigned long arg2);
172 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
173 --- a/arch/mips/lantiq/xway/Makefile
174 +++ b/arch/mips/lantiq/xway/Makefile
176 -obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
177 +obj-y := prom.o sysctrl.o clk.o reset.o dma.o dcdc.o
179 +ifdef CONFIG_SOC_AMAZON_SE
188 +++ b/arch/mips/lantiq/xway/timer.c
190 +#ifndef CONFIG_SOC_AMAZON_SE
192 +#include <linux/kernel.h>
193 +#include <linux/module.h>
194 +#include <linux/version.h>
195 +#include <linux/types.h>
196 +#include <linux/fs.h>
197 +#include <linux/miscdevice.h>
198 +#include <linux/init.h>
199 +#include <linux/uaccess.h>
200 +#include <linux/unistd.h>
201 +#include <linux/errno.h>
202 +#include <linux/interrupt.h>
203 +#include <linux/sched.h>
205 +#include <asm/irq.h>
206 +#include <asm/div64.h>
209 +#include <lantiq_soc.h>
210 +#include <lantiq_irq.h>
211 +#include <lantiq_timer.h>
213 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
216 +#define FIRST_TIMER TIMER1A
218 +#define FIRST_TIMER 2
222 + * GPTC divider is set or not.
224 +#define GPTU_CLC_RMC_IS_SET 0
227 + * Timer Interrupt (IRQ)
229 +/* Must be adjusted when ICU driver is available */
230 +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
235 +#define GET_BITS(x, msb, lsb) \
236 + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
237 +#define SET_BITS(x, msb, lsb, value) \
238 + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
239 + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
242 + * GPTU Register Mapping
244 +#define LQ_GPTU (KSEG1 + 0x1E100A00)
245 +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
246 +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
247 +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
248 +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
249 +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
250 +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
251 +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
252 +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
253 +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
256 + * Clock Control Register
258 +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
259 +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
260 +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
261 +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
262 +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
263 +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
264 +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
266 +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
267 +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
268 +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
269 +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
270 +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
271 +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
272 +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
277 +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
278 +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
279 +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
282 + * Control Register of Timer/Counter nX
283 + * n is the index of block (1 based index)
284 + * X is either A or B
286 +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
287 +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
288 +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
289 +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
290 +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
291 +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
292 +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
293 +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
294 +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
295 +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
297 +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
298 +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
299 +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
300 +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
301 +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
302 +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
303 +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
304 +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
305 +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
307 +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
308 +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
309 +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
311 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
312 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
314 +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
315 +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
316 +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
317 +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
318 +#define TIMER_FLAG_NONE_EDGE 0x0000
319 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
320 +#define TIMER_FLAG_REAL 0x0000
321 +#define TIMER_FLAG_INVERT 0x0040
322 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
323 +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
324 +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
325 +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
326 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
327 +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
329 +struct timer_dev_timer {
330 + unsigned int f_irq_on;
333 + unsigned long arg1;
334 + unsigned long arg2;
338 + struct mutex gptu_mutex;
339 + unsigned int number_of_timers;
340 + unsigned int occupation;
341 + unsigned int f_gptu_on;
342 + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
346 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
347 + struct clk *clk = clk_get_fpi();
348 + return clk_get_rate(clk);
352 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
353 +static int gptu_open(struct inode *, struct file *);
354 +static int gptu_release(struct inode *, struct file *);
356 +static struct file_operations gptu_fops = {
357 + .owner = THIS_MODULE,
358 + .unlocked_ioctl = gptu_ioctl,
360 + .release = gptu_release
363 +static struct miscdevice gptu_miscdev = {
364 + .minor = MISC_DYNAMIC_MINOR,
366 + .fops = &gptu_fops,
369 +static struct timer_dev timer_dev;
371 +static irqreturn_t timer_irq_handler(int irq, void *p)
373 + unsigned int timer;
375 + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
377 + timer = irq - TIMER_INTERRUPT;
378 + if (timer < timer_dev.number_of_timers
379 + && dev_timer == &timer_dev.timer[timer]) {
380 + /* Clear interrupt. */
381 + ltq_w32(1 << timer, LQ_GPTU_IRNCR);
383 + /* Call user hanler or signal. */
384 + flag = dev_timer->flag;
385 + if (!(timer & 0x01)
386 + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
387 + /* 16-bit timer or timer A of 32-bit timer */
388 + switch (TIMER_FLAG_MASK_HANDLE(flag)) {
389 + case TIMER_FLAG_CALLBACK_IN_IRQ:
390 + case TIMER_FLAG_CALLBACK_IN_HB:
391 + if (dev_timer->arg1)
392 + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
394 + case TIMER_FLAG_SIGNAL:
395 + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
400 + return IRQ_HANDLED;
403 +static inline void lq_enable_gptu(void)
405 + struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
408 + //ltq_pmu_enable(PMU_GPT);
410 + /* Set divider as 1, disable write protection for SPEN, enable module. */
412 + GPTU_CLC_SMC_SET(0x00) |
413 + GPTU_CLC_RMC_SET(0x01) |
414 + GPTU_CLC_FSOE_SET(0) |
415 + GPTU_CLC_SBWE_SET(1) |
416 + GPTU_CLC_EDIS_SET(0) |
417 + GPTU_CLC_SPEN_SET(0) |
418 + GPTU_CLC_DISR_SET(0);
421 +static inline void lq_disable_gptu(void)
423 + struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
424 + ltq_w32(0x00, LQ_GPTU_IRNEN);
425 + ltq_w32(0xfff, LQ_GPTU_IRNCR);
427 + /* Set divider as 0, enable write protection for SPEN, disable module. */
429 + GPTU_CLC_SMC_SET(0x00) |
430 + GPTU_CLC_RMC_SET(0x00) |
431 + GPTU_CLC_FSOE_SET(0) |
432 + GPTU_CLC_SBWE_SET(0) |
433 + GPTU_CLC_EDIS_SET(0) |
434 + GPTU_CLC_SPEN_SET(0) |
435 + GPTU_CLC_DISR_SET(1);
440 +int lq_request_timer(unsigned int timer, unsigned int flag,
441 + unsigned long value, unsigned long arg1, unsigned long arg2)
444 + unsigned int con_reg, irnen_reg;
447 + if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
450 + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
451 + timer, flag, value);
453 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
458 + mutex_lock(&timer_dev.gptu_mutex);
463 + if (timer < FIRST_TIMER) {
465 + unsigned int shift;
466 + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
467 + unsigned int offset = TIMER2A;
470 + * Pick up a free timer.
472 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
473 + mask = 1 << offset;
476 + mask = 3 << offset;
479 + for (timer = offset;
480 + timer < offset + timer_dev.number_of_timers;
481 + timer += shift, mask <<= shift)
482 + if (!(timer_dev.occupation & mask)) {
483 + timer_dev.occupation |= mask;
486 + if (timer >= offset + timer_dev.number_of_timers) {
487 + printk("failed![%d]\n", __LINE__);
488 + mutex_unlock(&timer_dev.gptu_mutex);
493 + register unsigned int mask;
496 + * Check if the requested timer is free.
498 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
499 + if ((timer_dev.occupation & mask)) {
500 + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
501 + __LINE__, mask, timer_dev.occupation);
502 + mutex_unlock(&timer_dev.gptu_mutex);
505 + timer_dev.occupation |= mask;
511 + * Prepare control register value.
513 + switch (TIMER_FLAG_MASK_EDGE(flag)) {
515 + case TIMER_FLAG_NONE_EDGE:
516 + con_reg = GPTU_CON_EDGE_SET(0x00);
518 + case TIMER_FLAG_RISE_EDGE:
519 + con_reg = GPTU_CON_EDGE_SET(0x01);
521 + case TIMER_FLAG_FALL_EDGE:
522 + con_reg = GPTU_CON_EDGE_SET(0x02);
524 + case TIMER_FLAG_ANY_EDGE:
525 + con_reg = GPTU_CON_EDGE_SET(0x03);
528 + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
530 + TIMER_FLAG_MASK_SRC(flag) ==
531 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
532 + GPTU_CON_SRC_EXT_SET(0);
535 + TIMER_FLAG_MASK_SRC(flag) ==
536 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
537 + GPTU_CON_SRC_EG_SET(0);
539 + TIMER_FLAG_MASK_SYNC(flag) ==
540 + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
541 + GPTU_CON_SYNC_SET(1);
543 + TIMER_FLAG_MASK_INVERT(flag) ==
544 + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
546 + TIMER_FLAG_MASK_SIZE(flag) ==
547 + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
548 + GPTU_CON_EXT_SET(1);
550 + TIMER_FLAG_MASK_STOP(flag) ==
551 + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
553 + TIMER_FLAG_MASK_TYPE(flag) ==
554 + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
555 + GPTU_CON_CNT_SET(1);
557 + TIMER_FLAG_MASK_DIR(flag) ==
558 + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
561 + * Fill up running data.
563 + timer_dev.timer[timer - FIRST_TIMER].flag = flag;
564 + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
565 + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
566 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
567 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
570 + * Enable GPTU module.
572 + if (!timer_dev.f_gptu_on) {
574 + timer_dev.f_gptu_on = 1;
580 + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
581 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
582 + timer_dev.timer[timer - FIRST_TIMER].arg1 =
583 + (unsigned long) find_task_by_vpid((int) arg1);
585 + irnen_reg = 1 << (timer - FIRST_TIMER);
587 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
588 + || (TIMER_FLAG_MASK_HANDLE(flag) ==
589 + TIMER_FLAG_CALLBACK_IN_IRQ
590 + && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
591 + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
592 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
598 + * Write config register, reload value and enable interrupt.
602 + *LQ_GPTU_CON(n, X) = con_reg;
603 + *LQ_GPTU_RELOAD(n, X) = value;
604 + /* printk("reload value = %d\n", (u32)value); */
605 + *LQ_GPTU_IRNEN |= irnen_reg;
607 + mutex_unlock(&timer_dev.gptu_mutex);
608 + printk("successful!\n");
611 +EXPORT_SYMBOL(lq_request_timer);
613 +int lq_free_timer(unsigned int timer)
619 + if (!timer_dev.f_gptu_on)
622 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
625 + mutex_lock(&timer_dev.gptu_mutex);
627 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
628 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
631 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
632 + if (((timer_dev.occupation & mask) ^ mask)) {
633 + mutex_unlock(&timer_dev.gptu_mutex);
640 + if (GPTU_CON_EN(n, X))
641 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
643 + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
644 + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
646 + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
647 + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
648 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
651 + timer_dev.occupation &= ~mask;
652 + if (!timer_dev.occupation && timer_dev.f_gptu_on) {
654 + timer_dev.f_gptu_on = 0;
657 + mutex_unlock(&timer_dev.gptu_mutex);
661 +EXPORT_SYMBOL(lq_free_timer);
663 +int lq_start_timer(unsigned int timer, int is_resume)
669 + if (!timer_dev.f_gptu_on)
672 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
675 + mutex_lock(&timer_dev.gptu_mutex);
677 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
678 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
681 + mask = (TIMER_FLAG_MASK_SIZE(flag) ==
682 + TIMER_FLAG_16BIT ? 1 : 3) << timer;
683 + if (((timer_dev.occupation & mask) ^ mask)) {
684 + mutex_unlock(&timer_dev.gptu_mutex);
691 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
694 + mutex_unlock(&timer_dev.gptu_mutex);
698 +EXPORT_SYMBOL(lq_start_timer);
700 +int lq_stop_timer(unsigned int timer)
706 + if (!timer_dev.f_gptu_on)
709 + if (timer < FIRST_TIMER
710 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
713 + mutex_lock(&timer_dev.gptu_mutex);
715 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
716 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
719 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
720 + if (((timer_dev.occupation & mask) ^ mask)) {
721 + mutex_unlock(&timer_dev.gptu_mutex);
728 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
730 + mutex_unlock(&timer_dev.gptu_mutex);
734 +EXPORT_SYMBOL(lq_stop_timer);
736 +int lq_reset_counter_flags(u32 timer, u32 flags)
738 + unsigned int oflag;
739 + unsigned int mask, con_reg;
742 + if (!timer_dev.f_gptu_on)
745 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
748 + mutex_lock(&timer_dev.gptu_mutex);
750 + oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
751 + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
754 + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
755 + if (((timer_dev.occupation & mask) ^ mask)) {
756 + mutex_unlock(&timer_dev.gptu_mutex);
760 + switch (TIMER_FLAG_MASK_EDGE(flags)) {
762 + case TIMER_FLAG_NONE_EDGE:
763 + con_reg = GPTU_CON_EDGE_SET(0x00);
765 + case TIMER_FLAG_RISE_EDGE:
766 + con_reg = GPTU_CON_EDGE_SET(0x01);
768 + case TIMER_FLAG_FALL_EDGE:
769 + con_reg = GPTU_CON_EDGE_SET(0x02);
771 + case TIMER_FLAG_ANY_EDGE:
772 + con_reg = GPTU_CON_EDGE_SET(0x03);
775 + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
776 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
778 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
779 + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
780 + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
781 + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
782 + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
783 + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
784 + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
786 + timer_dev.timer[timer - FIRST_TIMER].flag = flags;
787 + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
788 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
793 + *LQ_GPTU_CON(n, X) = con_reg;
795 + mutex_unlock(&timer_dev.gptu_mutex);
798 +EXPORT_SYMBOL(lq_reset_counter_flags);
800 +int lq_get_count_value(unsigned int timer, unsigned long *value)
806 + if (!timer_dev.f_gptu_on)
809 + if (timer < FIRST_TIMER
810 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
813 + mutex_lock(&timer_dev.gptu_mutex);
815 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
816 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
819 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
820 + if (((timer_dev.occupation & mask) ^ mask)) {
821 + mutex_unlock(&timer_dev.gptu_mutex);
828 + *value = *LQ_GPTU_COUNT(n, X);
831 + mutex_unlock(&timer_dev.gptu_mutex);
835 +EXPORT_SYMBOL(lq_get_count_value);
837 +u32 lq_cal_divider(unsigned long freq)
839 + u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
840 + u32 clock_divider = 1;
841 + module_freq = fpi * 1000;
842 + do_div(module_freq, clock_divider * freq);
843 + return module_freq;
845 +EXPORT_SYMBOL(lq_cal_divider);
847 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
848 + int is_ext_src, unsigned int handle_flag, unsigned long arg1,
849 + unsigned long arg2)
851 + unsigned long divider;
854 + divider = lq_cal_divider(freq);
857 + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
858 + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
859 + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
860 + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
861 + | TIMER_FLAG_MASK_HANDLE(handle_flag);
863 + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
864 + timer, freq, divider);
865 + return lq_request_timer(timer, flag, divider, arg1, arg2);
867 +EXPORT_SYMBOL(lq_set_timer);
869 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
870 + unsigned long arg1, unsigned long arg2)
872 + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
873 + return lq_request_timer(timer, flag, reload, arg1, arg2);
875 +EXPORT_SYMBOL(lq_set_counter);
877 +static long gptu_ioctl(struct file *file, unsigned int cmd,
881 + struct gptu_ioctl_param param;
883 + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
885 + copy_from_user(¶m, (void *) arg, sizeof(param));
887 + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
888 + || GPTU_SET_COUNTER) && param.timer < 2)
889 + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
890 + && !access_ok(VERIFY_WRITE, arg,
891 + sizeof(struct gptu_ioctl_param)))
895 + case GPTU_REQUEST_TIMER:
896 + ret = lq_request_timer(param.timer, param.flag, param.value,
897 + (unsigned long) param.pid,
898 + (unsigned long) param.sig);
900 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
901 + timer, &ret, sizeof(&ret));
905 + case GPTU_FREE_TIMER:
906 + ret = lq_free_timer(param.timer);
908 + case GPTU_START_TIMER:
909 + ret = lq_start_timer(param.timer, param.flag);
911 + case GPTU_STOP_TIMER:
912 + ret = lq_stop_timer(param.timer);
914 + case GPTU_GET_COUNT_VALUE:
915 + ret = lq_get_count_value(param.timer, ¶m.value);
917 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
918 + value, ¶m.value,
919 + sizeof(param.value));
921 + case GPTU_CALCULATE_DIVIDER:
922 + param.value = lq_cal_divider(param.value);
923 + if (param.value == 0)
926 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
927 + value, ¶m.value,
928 + sizeof(param.value));
932 + case GPTU_SET_TIMER:
933 + ret = lq_set_timer(param.timer, param.value,
934 + TIMER_FLAG_MASK_STOP(param.flag) !=
935 + TIMER_FLAG_ONCE ? 1 : 0,
936 + TIMER_FLAG_MASK_SRC(param.flag) ==
937 + TIMER_FLAG_EXT_SRC ? 1 : 0,
938 + TIMER_FLAG_MASK_HANDLE(param.flag) ==
939 + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
940 + TIMER_FLAG_NO_HANDLE,
941 + (unsigned long) param.pid,
942 + (unsigned long) param.sig);
944 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
945 + timer, &ret, sizeof(&ret));
949 + case GPTU_SET_COUNTER:
950 + lq_set_counter(param.timer, param.flag, param.value, 0, 0);
952 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
953 + timer, &ret, sizeof(&ret));
964 +static int gptu_open(struct inode *inode, struct file *file)
969 +static int gptu_release(struct inode *inode, struct file *file)
974 +int __init lq_gptu_init(void)
979 + ltq_w32(0, LQ_GPTU_IRNEN);
980 + ltq_w32(0xfff, LQ_GPTU_IRNCR);
982 + memset(&timer_dev, 0, sizeof(timer_dev));
983 + mutex_init(&timer_dev.gptu_mutex);
986 + timer_dev.number_of_timers = GPTU_ID_CFG * 2;
988 + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
989 + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
990 + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
992 + ret = misc_register(&gptu_miscdev);
994 + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
997 + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
1000 + for (i = 0; i < timer_dev.number_of_timers; i++) {
1001 + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
1003 + for (; i >= 0; i--)
1004 + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
1005 + misc_deregister(&gptu_miscdev);
1006 + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
1009 + timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
1010 + disable_irq(timer_dev.timer[i].irq);
1011 + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
1018 +void __exit lq_gptu_exit(void)
1022 + for (i = 0; i < timer_dev.number_of_timers; i++) {
1023 + if (timer_dev.timer[i].f_irq_on)
1024 + disable_irq(timer_dev.timer[i].irq);
1025 + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1027 + lq_disable_gptu();
1028 + misc_deregister(&gptu_miscdev);
1031 +module_init(lq_gptu_init);
1032 +module_exit(lq_gptu_exit);