2 +++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
4 +Lantiq Synchronous Serial Controller (SSC) SPI master driver
7 +- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
8 +- #address-cells: see spi-bus.txt
9 +- #size-cells: see spi-bus.txt
10 +- reg: address and length of the spi master registers
11 +- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
15 +- clocks: spi clock phandle
16 +- num-cs: see spi-bus.txt, set to 8 if unset
17 +- base-cs: the number of the first chip select, set to 1 if unset.
23 + compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
24 + reg = <0xE100800 0x100>;
25 + interrupt-parent = <&icu0>;
26 + interrupts = <22 23 24>;
27 + interrupt-names = "spi_rx", "spi_tx", "spi_err";
28 + #address-cells = <1>;
33 --- a/drivers/spi/Kconfig
34 +++ b/drivers/spi/Kconfig
35 @@ -403,6 +403,14 @@ config SPI_NUC900
37 SPI driver for Nuvoton NUC900 series ARM SoCs
39 +config SPI_LANTIQ_SSC
40 + tristate "Lantiq SSC SPI controller"
43 + This driver supports the Lantiq SSC SPI controller in master
44 + mode. This controller is found on Intel (former Lantiq) SoCs like
45 + the Danube, Falcon, xRX200, xRX300.
48 tristate "OpenCores tiny SPI"
49 depends on GPIOLIB || COMPILE_TEST
50 --- a/drivers/spi/Makefile
51 +++ b/drivers/spi/Makefile
52 @@ -47,6 +47,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-sp
53 obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
54 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
55 obj-$(CONFIG_SPI_IMX) += spi-imx.o
56 +obj-$(CONFIG_SPI_LANTIQ_SSC) += spi-lantiq-ssc.o
57 obj-$(CONFIG_SPI_JCORE) += spi-jcore.o
58 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
59 obj-$(CONFIG_SPI_LP8841_RTC) += spi-lp8841-rtc.o
61 +++ b/drivers/spi/spi-lantiq-ssc.c
64 + * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
65 + * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
67 + * This program is free software; you can distribute it and/or modify it
68 + * under the terms of the GNU General Public License (Version 2) as
69 + * published by the Free Software Foundation.
72 +#include <linux/kernel.h>
73 +#include <linux/module.h>
74 +#include <linux/of_device.h>
75 +#include <linux/clk.h>
76 +#include <linux/io.h>
77 +#include <linux/delay.h>
78 +#include <linux/interrupt.h>
79 +#include <linux/sched.h>
80 +#include <linux/completion.h>
81 +#include <linux/spinlock.h>
82 +#include <linux/err.h>
83 +#include <linux/gpio.h>
84 +#include <linux/pm_runtime.h>
85 +#include <linux/spi/spi.h>
87 +#include <lantiq_soc.h>
89 +#define SPI_RX_IRQ_NAME "spi_rx"
90 +#define SPI_TX_IRQ_NAME "spi_tx"
91 +#define SPI_ERR_IRQ_NAME "spi_err"
92 +#define SPI_FRM_IRQ_NAME "spi_frm"
95 +#define SPI_PISEL 0x04
98 +#define SPI_STAT 0x14
99 +#define SPI_WHBSTATE 0x18
102 +#define SPI_RXFCON 0x30
103 +#define SPI_TXFCON 0x34
104 +#define SPI_FSTAT 0x38
105 +#define SPI_BRT 0x40
106 +#define SPI_BRSTAT 0x44
107 +#define SPI_SFCON 0x60
108 +#define SPI_SFSTAT 0x64
109 +#define SPI_GPOCON 0x70
110 +#define SPI_GPOSTAT 0x74
111 +#define SPI_FPGO 0x78
112 +#define SPI_RXREQ 0x80
113 +#define SPI_RXCNT 0x84
114 +#define SPI_DMACON 0xec
115 +#define SPI_IRNEN 0xf4
116 +#define SPI_IRNICR 0xf8
117 +#define SPI_IRNCR 0xfc
119 +#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
120 +#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S)
121 +#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
122 +#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S)
123 +#define SPI_CLC_DISS BIT(1) /* Disable status bit */
124 +#define SPI_CLC_DISR BIT(0) /* Disable request bit */
126 +#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
127 +#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S)
128 +#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
129 +#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S)
130 +#define SPI_ID_MOD_S 8 /* Module ID */
131 +#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S)
132 +#define SPI_ID_CFG_S 5 /* DMA interface support */
133 +#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S)
134 +#define SPI_ID_REV_M 0x1F /* Hardware revision number */
136 +#define SPI_CON_BM_S 16 /* Data width selection */
137 +#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S)
138 +#define SPI_CON_EM BIT(24) /* Echo mode */
139 +#define SPI_CON_IDLE BIT(23) /* Idle bit value */
140 +#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */
141 +#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
142 +#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
143 +#define SPI_CON_AEN BIT(10) /* Abort error enable */
144 +#define SPI_CON_REN BIT(9) /* Receive overflow error enable */
145 +#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
146 +#define SPI_CON_LB BIT(7) /* Loopback control */
147 +#define SPI_CON_PO BIT(6) /* Clock polarity control */
148 +#define SPI_CON_PH BIT(5) /* Clock phase control */
149 +#define SPI_CON_HB BIT(4) /* Heading control */
150 +#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */
151 +#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
153 +#define SPI_STAT_RXBV_S 28
154 +#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S)
155 +#define SPI_STAT_BSY BIT(13) /* Busy flag */
156 +#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
157 +#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
158 +#define SPI_STAT_AE BIT(10) /* Abort error flag */
159 +#define SPI_STAT_RE BIT(9) /* Receive error flag */
160 +#define SPI_STAT_TE BIT(8) /* Transmit error flag */
161 +#define SPI_STAT_ME BIT(7) /* Mode error flag */
162 +#define SPI_STAT_MS BIT(1) /* Master/slave select bit */
163 +#define SPI_STAT_EN BIT(0) /* Enable bit */
164 +#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \
165 + SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE)
167 +#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
168 +#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
169 +#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
170 +#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
171 +#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
172 +#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
173 +#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
174 +#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
175 +#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
176 +#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
177 +#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
178 +#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
179 +#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
180 +#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
181 +#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
182 +#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
183 +#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \
184 + SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \
185 + SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE)
187 +#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
188 +#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S)
189 +#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
190 +#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
192 +#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
193 +#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S)
194 +#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
195 +#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
197 +#define SPI_FSTAT_RXFFL_S 0
198 +#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S)
199 +#define SPI_FSTAT_TXFFL_S 8
200 +#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S)
202 +#define SPI_GPOCON_ISCSBN_S 8
203 +#define SPI_GPOCON_INVOUTN_S 0
205 +#define SPI_FGPO_SETOUTN_S 8
206 +#define SPI_FGPO_CLROUTN_S 0
208 +#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
209 +#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
211 +#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
212 +#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
213 +#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */
214 +#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
215 +#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
216 +#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
217 +#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
218 +#define SPI_IRNEN_ALL 0x1F
220 +struct lantiq_ssc_hwcfg {
221 + unsigned int irnen_r;
222 + unsigned int irnen_t;
225 +struct lantiq_ssc_spi {
226 + struct spi_master *master;
227 + struct device *dev;
228 + void __iomem *regbase;
229 + struct clk *spi_clk;
230 + struct clk *fpi_clk;
231 + const struct lantiq_ssc_hwcfg *hwcfg;
237 + unsigned int tx_todo;
238 + unsigned int rx_todo;
239 + unsigned int bits_per_word;
240 + unsigned int speed_hz;
242 + unsigned int tx_fifo_size;
243 + unsigned int rx_fifo_size;
244 + unsigned int base_cs;
247 +static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
249 + return __raw_readl(spi->regbase + reg);
252 +static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
255 + __raw_writel(val, spi->regbase + reg);
258 +static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
261 + u32 val = __raw_readl(spi->regbase + reg);
265 + __raw_writel(val, spi->regbase + reg);
268 +static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
270 + u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
272 + return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S;
275 +static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
277 + u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
279 + return fstat & SPI_FSTAT_RXFFL_M;
282 +static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
284 + return spi->tx_fifo_size - tx_fifo_level(spi);
287 +static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
289 + u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S;
291 + val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU;
292 + lantiq_ssc_writel(spi, val, SPI_RXFCON);
295 +static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
297 + u32 val = 1 << SPI_TXFCON_TXFITL_S;
299 + val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU;
300 + lantiq_ssc_writel(spi, val, SPI_TXFCON);
303 +static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
305 + lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON);
308 +static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
310 + lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON);
313 +static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
315 + lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE);
318 +static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
320 + lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE);
323 +static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
324 + unsigned int max_speed_hz)
329 + * SPI module clock is derived from FPI bus clock dependent on
330 + * divider value in CLC.RMS which is always set to 1.
333 + * baudrate = --------------
336 + spi_clk = clk_get_rate(spi->fpi_clk) / 2;
338 + if (max_speed_hz > spi_clk)
341 + brt = spi_clk / max_speed_hz - 1;
346 + dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
347 + spi_clk, max_speed_hz, brt);
349 + lantiq_ssc_writel(spi, brt, SPI_BRT);
352 +static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
353 + unsigned int bits_per_word)
357 + /* CON.BM value = bits_per_word - 1 */
358 + bm = (bits_per_word - 1) << SPI_CON_BM_S;
360 + lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON);
363 +static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
366 + u32 con_set = 0, con_clr = 0;
369 + * SPI mode mapping in CON register:
370 + * Mode CPOL CPHA CON.PO CON.PH
376 + if (mode & SPI_CPHA)
377 + con_clr |= SPI_CON_PH;
379 + con_set |= SPI_CON_PH;
381 + if (mode & SPI_CPOL)
382 + con_set |= SPI_CON_PO | SPI_CON_IDLE;
384 + con_clr |= SPI_CON_PO | SPI_CON_IDLE;
386 + /* Set heading control */
387 + if (mode & SPI_LSB_FIRST)
388 + con_clr |= SPI_CON_HB;
390 + con_set |= SPI_CON_HB;
392 + /* Set loopback mode */
393 + if (mode & SPI_LOOP)
394 + con_set |= SPI_CON_LB;
396 + con_clr |= SPI_CON_LB;
398 + lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON);
401 +static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
403 + const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
406 + * Set clock divider for run mode to 1 to
407 + * run at same frequency as FPI bus
409 + lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC);
411 + /* Put controller into config mode */
412 + hw_enter_config_mode(spi);
414 + /* Clear error flags */
415 + lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
417 + /* Enable error checking, disable TX/RX */
418 + lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN |
419 + SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
421 + /* Setup default SPI mode */
422 + hw_setup_bits_per_word(spi, spi->bits_per_word);
423 + hw_setup_clock_mode(spi, SPI_MODE_0);
425 + /* Enable master mode and clear error flags */
426 + lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS,
429 + /* Reset GPIO/CS registers */
430 + lantiq_ssc_writel(spi, 0, SPI_GPOCON);
431 + lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO);
433 + /* Enable and flush FIFOs */
434 + rx_fifo_reset(spi);
435 + tx_fifo_reset(spi);
437 + /* Enable interrupts */
438 + lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E,
442 +static int lantiq_ssc_setup(struct spi_device *spidev)
444 + struct spi_master *master = spidev->master;
445 + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
446 + unsigned int cs = spidev->chip_select;
449 + /* GPIOs are used for CS */
450 + if (gpio_is_valid(spidev->cs_gpio))
453 + dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
455 + if (cs < spi->base_cs) {
457 + "chipselect %i too small (min %i)\n", cs, spi->base_cs);
461 + /* set GPO pin to CS mode */
462 + gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S);
464 + /* invert GPO pin */
465 + if (spidev->mode & SPI_CS_HIGH)
466 + gpocon |= 1 << (cs - spi->base_cs);
468 + lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON);
473 +static int lantiq_ssc_prepare_message(struct spi_master *master,
474 + struct spi_message *message)
476 + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
478 + hw_enter_config_mode(spi);
479 + hw_setup_clock_mode(spi, message->spi->mode);
480 + hw_enter_active_mode(spi);
485 +static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
486 + struct spi_device *spidev, struct spi_transfer *t)
488 + unsigned int speed_hz = t->speed_hz;
489 + unsigned int bits_per_word = t->bits_per_word;
492 + if (bits_per_word != spi->bits_per_word ||
493 + speed_hz != spi->speed_hz) {
494 + hw_enter_config_mode(spi);
495 + hw_setup_speed_hz(spi, speed_hz);
496 + hw_setup_bits_per_word(spi, bits_per_word);
497 + hw_enter_active_mode(spi);
499 + spi->speed_hz = speed_hz;
500 + spi->bits_per_word = bits_per_word;
503 + /* Configure transmitter and receiver */
504 + con = lantiq_ssc_readl(spi, SPI_CON);
506 + con &= ~SPI_CON_TXOFF;
508 + con |= SPI_CON_TXOFF;
511 + con &= ~SPI_CON_RXOFF;
513 + con |= SPI_CON_RXOFF;
515 + lantiq_ssc_writel(spi, con, SPI_CON);
518 +static int lantiq_ssc_unprepare_message(struct spi_master *master,
519 + struct spi_message *message)
521 + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
523 + /* Disable transmitter and receiver while idle */
524 + lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
529 +static void tx_fifo_write(struct lantiq_ssc_spi *spi)
535 + unsigned int tx_free = tx_fifo_free(spi);
537 + while (spi->tx_todo && tx_free) {
538 + switch (spi->bits_per_word) {
546 + tx16 = (u16 *) spi->tx;
552 + tx32 = (u32 *) spi->tx;
563 + lantiq_ssc_writel(spi, data, SPI_TB);
568 +static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
574 + unsigned int rx_fill = rx_fifo_level(spi);
577 + data = lantiq_ssc_readl(spi, SPI_RB);
579 + switch (spi->bits_per_word) {
587 + rx16 = (u16 *) spi->rx;
593 + rx32 = (u32 *) spi->rx;
607 +static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
611 + unsigned int rxbv, shift;
612 + unsigned int rx_fill = rx_fifo_level(spi);
615 + * In RX-only mode the bits per word value is ignored by HW. A value
616 + * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
617 + * If remaining RX bytes are less than 4, the FIFO must be read
618 + * differently. The amount of received and valid bytes is indicated
619 + * by STAT.RXBV register value.
622 + if (spi->rx_todo < 4) {
623 + rxbv = (lantiq_ssc_readl(spi, SPI_STAT) &
624 + SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S;
625 + data = lantiq_ssc_readl(spi, SPI_RB);
627 + shift = (rxbv - 1) * 8;
631 + *rx8++ = (data >> shift) & 0xFF;
638 + data = lantiq_ssc_readl(spi, SPI_RB);
639 + rx32 = (u32 *) spi->rx;
649 +static void rx_request(struct lantiq_ssc_spi *spi)
651 + unsigned int rxreq, rxreq_max;
654 + * To avoid receive overflows at high clocks it is better to request
655 + * only the amount of bytes that fits into all FIFOs. This value
656 + * depends on the FIFO size implemented in hardware.
658 + rxreq = spi->rx_todo;
659 + rxreq_max = spi->rx_fifo_size * 4;
660 + if (rxreq > rxreq_max)
663 + lantiq_ssc_writel(spi, rxreq, SPI_RXREQ);
666 +static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
668 + struct lantiq_ssc_spi *spi = data;
671 + if (spi->rx && spi->rx_todo)
672 + rx_fifo_read_full_duplex(spi);
675 + tx_fifo_write(spi);
676 + else if (!tx_fifo_level(spi))
678 + } else if (spi->rx) {
679 + if (spi->rx_todo) {
680 + rx_fifo_read_half_duplex(spi);
691 + return IRQ_HANDLED;
695 + spi_finalize_current_transfer(spi->master);
697 + return IRQ_HANDLED;
700 +static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
702 + struct lantiq_ssc_spi *spi = data;
703 + u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
705 + if (!(stat & SPI_STAT_ERRORS))
708 + if (stat & SPI_STAT_RUE)
709 + dev_err(spi->dev, "receive underflow error\n");
710 + if (stat & SPI_STAT_TUE)
711 + dev_err(spi->dev, "transmit underflow error\n");
712 + if (stat & SPI_STAT_AE)
713 + dev_err(spi->dev, "abort error\n");
714 + if (stat & SPI_STAT_RE)
715 + dev_err(spi->dev, "receive overflow error\n");
716 + if (stat & SPI_STAT_TE)
717 + dev_err(spi->dev, "transmit overflow error\n");
718 + if (stat & SPI_STAT_ME)
719 + dev_err(spi->dev, "mode error\n");
721 + /* Clear error flags */
722 + lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
724 + /* set bad status so it can be retried */
725 + spi->status = -EIO;
726 + spi_finalize_current_transfer(spi->master);
728 + return IRQ_HANDLED;
731 +static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
732 + struct spi_transfer *t)
734 + unsigned long flags;
736 + spin_lock_irqsave(&spi->lock, flags);
738 + spi->tx = t->tx_buf;
739 + spi->rx = t->rx_buf;
740 + spi->status = -EINPROGRESS;
743 + spi->tx_todo = t->len;
745 + /* initially fill TX FIFO */
746 + tx_fifo_write(spi);
750 + spi->rx_todo = t->len;
752 + /* start shift clock in RX-only mode */
757 + spin_unlock_irqrestore(&spi->lock, flags);
762 +static int lantiq_ssc_transfer_status(struct spi_master *master,
763 + unsigned long timeout)
765 + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
769 + * The driver only gets an interrupt when the FIFO is empty, but there
770 + * is an additional shift register from which the data is written to
771 + * the wire. We get the last interrupt when the controller starts to
772 + * write the last word to the wire, not when it is finished. Do busy
773 + * waiting till it finishes.
775 + end = jiffies + timeout;
777 + u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
779 + if (!(stat & SPI_STAT_BSY))
780 + return spi->status;
783 + } while (!time_after_eq(jiffies, end));
788 +static void lantiq_ssc_handle_err(struct spi_master *master,
789 + struct spi_message *message)
791 + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
793 + /* flush FIFOs on timeout */
794 + rx_fifo_flush(spi);
795 + tx_fifo_flush(spi);
798 +static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
800 + struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
801 + unsigned int cs = spidev->chip_select;
804 + if (!!(spidev->mode & SPI_CS_HIGH) == enable)
805 + fgpo = (1 << (cs - spi->base_cs));
807 + fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S));
809 + lantiq_ssc_writel(spi, fgpo, SPI_FPGO);
812 +static int lantiq_ssc_transfer_one(struct spi_master *master,
813 + struct spi_device *spidev,
814 + struct spi_transfer *t)
816 + struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
818 + hw_setup_transfer(spi, spidev, t);
820 + return transfer_start(spi, spidev, t);
823 +static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
824 + .irnen_r = SPI_IRNEN_R_XWAY,
825 + .irnen_t = SPI_IRNEN_T_XWAY,
828 +static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
829 + .irnen_r = SPI_IRNEN_R_XRX,
830 + .irnen_t = SPI_IRNEN_T_XRX,
833 +static const struct of_device_id lantiq_ssc_match[] = {
834 + { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
835 + { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
836 + { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
839 +MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
841 +static int lantiq_ssc_probe(struct platform_device *pdev)
843 + struct spi_master *master;
844 + struct resource *res;
845 + struct lantiq_ssc_spi *spi;
846 + const struct lantiq_ssc_hwcfg *hwcfg;
847 + const struct of_device_id *match;
848 + int err, rx_irq, tx_irq, err_irq;
849 + u32 id, supports_dma, revision;
850 + unsigned int num_cs;
852 + match = of_match_device(lantiq_ssc_match, &pdev->dev);
854 + dev_err(&pdev->dev, "no device match\n");
857 + hwcfg = match->data;
859 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
861 + dev_err(&pdev->dev, "failed to get resources\n");
865 + rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME);
867 + dev_err(&pdev->dev, "failed to get %s\n", SPI_RX_IRQ_NAME);
871 + tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME);
873 + dev_err(&pdev->dev, "failed to get %s\n", SPI_TX_IRQ_NAME);
877 + err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME);
879 + dev_err(&pdev->dev, "failed to get %s\n", SPI_ERR_IRQ_NAME);
883 + master = spi_alloc_master(&pdev->dev, sizeof(struct lantiq_ssc_spi));
887 + spi = spi_master_get_devdata(master);
888 + spi->master = master;
889 + spi->dev = &pdev->dev;
890 + spi->hwcfg = hwcfg;
891 + platform_set_drvdata(pdev, spi);
893 + spi->regbase = devm_ioremap_resource(&pdev->dev, res);
894 + if (IS_ERR(spi->regbase)) {
895 + err = PTR_ERR(spi->regbase);
896 + goto err_master_put;
899 + err = devm_request_irq(&pdev->dev, rx_irq, lantiq_ssc_xmit_interrupt,
900 + 0, SPI_RX_IRQ_NAME, spi);
902 + goto err_master_put;
904 + err = devm_request_irq(&pdev->dev, tx_irq, lantiq_ssc_xmit_interrupt,
905 + 0, SPI_TX_IRQ_NAME, spi);
907 + goto err_master_put;
909 + err = devm_request_irq(&pdev->dev, err_irq, lantiq_ssc_err_interrupt,
910 + 0, SPI_ERR_IRQ_NAME, spi);
912 + goto err_master_put;
914 + spi->spi_clk = devm_clk_get(&pdev->dev, NULL);
915 + if (IS_ERR(spi->spi_clk)) {
916 + err = PTR_ERR(spi->spi_clk);
917 + goto err_master_put;
919 + err = clk_prepare_enable(spi->spi_clk);
921 + goto err_master_put;
923 + spi->fpi_clk = clk_get_fpi();
924 + if (IS_ERR(spi->fpi_clk)) {
925 + err = PTR_ERR(spi->fpi_clk);
926 + goto err_clk_disable;
930 + of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
933 + of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
935 + spin_lock_init(&spi->lock);
936 + spi->bits_per_word = 8;
939 + master->dev.of_node = pdev->dev.of_node;
940 + master->num_chipselect = num_cs;
941 + master->setup = lantiq_ssc_setup;
942 + master->set_cs = lantiq_ssc_set_cs;
943 + master->handle_err = lantiq_ssc_handle_err;
944 + master->prepare_message = lantiq_ssc_prepare_message;
945 + master->unprepare_message = lantiq_ssc_unprepare_message;
946 + master->transfer_one = lantiq_ssc_transfer_one;
947 + master->transfer_status = lantiq_ssc_transfer_status;
948 + master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
950 + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
951 + SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
953 + id = lantiq_ssc_readl(spi, SPI_ID);
954 + spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S;
955 + spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S;
956 + supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S;
957 + revision = id & SPI_ID_REV_M;
959 + lantiq_ssc_hw_init(spi);
961 + dev_info(&pdev->dev,
962 + "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
963 + revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
965 + err = devm_spi_register_master(&pdev->dev, master);
967 + dev_err(&pdev->dev, "failed to register spi_master\n");
974 + clk_put(spi->fpi_clk);
976 + clk_disable_unprepare(spi->spi_clk);
978 + spi_master_put(master);
983 +static int lantiq_ssc_remove(struct platform_device *pdev)
985 + struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
987 + lantiq_ssc_writel(spi, 0, SPI_IRNEN);
988 + lantiq_ssc_writel(spi, 0, SPI_CLC);
989 + rx_fifo_flush(spi);
990 + tx_fifo_flush(spi);
991 + hw_enter_config_mode(spi);
993 + clk_disable_unprepare(spi->spi_clk);
994 + clk_put(spi->fpi_clk);
999 +static struct platform_driver lantiq_ssc_driver = {
1000 + .probe = lantiq_ssc_probe,
1001 + .remove = lantiq_ssc_remove,
1003 + .name = "spi-lantiq-ssc",
1004 + .owner = THIS_MODULE,
1005 + .of_match_table = lantiq_ssc_match,
1008 +module_platform_driver(lantiq_ssc_driver);
1010 +MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
1011 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
1012 +MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
1013 +MODULE_LICENSE("GPL");
1014 +MODULE_ALIAS("platform:spi-lantiq-ssc");