target/linux/lantiq/patches-6.1/0008-MIPS-lantiq-backport-old-timer-code.patch

   1 From 94800350cb8d2f29dda2206b5e9a3772024ee168 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 7 Aug 2014 18:30:56 +0200
   4 Subject: [PATCH 08/36] MIPS: lantiq: backport old timer code
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
   9  arch/mips/lantiq/xway/Makefile                   |    2 +-
  10  arch/mips/lantiq/xway/timer.c                    |  845 ++++++++++++++++++++++
  11  3 files changed, 1001 insertions(+), 1 deletion(-)
  12  create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  13  create mode 100644 arch/mips/lantiq/xway/timer.c
  14
  15 --- /dev/null
  16 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
  17 @@ -0,0 +1,155 @@
  18 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  19 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
  20 +
  21 +
  22 +/******************************************************************************
  23 +       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
  24 +
  25 +                               No Warranty
  26 +   Because the program is licensed free of charge, there is no warranty for
  27 +   the program, to the extent permitted by applicable law.  Except when
  28 +   otherwise stated in writing the copyright holders and/or other parties
  29 +   provide the program "as is" without warranty of any kind, either
  30 +   expressed or implied, including, but not limited to, the implied
  31 +   warranties of merchantability and fitness for a particular purpose. The
  32 +   entire risk as to the quality and performance of the program is with
  33 +   you.  should the program prove defective, you assume the cost of all
  34 +   necessary servicing, repair or correction.
  35 +
  36 +   In no event unless required by applicable law or agreed to in writing
  37 +   will any copyright holder, or any other party who may modify and/or
  38 +   redistribute the program as permitted above, be liable to you for
  39 +   damages, including any general, special, incidental or consequential
  40 +   damages arising out of the use or inability to use the program
  41 +   (including but not limited to loss of data or data being rendered
  42 +   inaccurate or losses sustained by you or third parties or a failure of
  43 +   the program to operate with any other programs), even if such holder or
  44 +   other party has been advised of the possibility of such damages.
  45 +******************************************************************************/
  46 +
  47 +
  48 +/*
  49 + * ####################################
  50 + *              Definition
  51 + * ####################################
  52 + */
  53 +
  54 +/*
  55 + *  Available Timer/Counter Index
  56 + */
  57 +#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
  58 +#define TIMER_ANY                       0x00
  59 +#define TIMER1A                         TIMER(1, 0)
  60 +#define TIMER1B                         TIMER(1, 1)
  61 +#define TIMER2A                         TIMER(2, 0)
  62 +#define TIMER2B                         TIMER(2, 1)
  63 +#define TIMER3A                         TIMER(3, 0)
  64 +#define TIMER3B                         TIMER(3, 1)
  65 +
  66 +/*
  67 + *  Flag of Timer/Counter
  68 + *  These flags specify the way in which timer is configured.
  69 + */
  70 +/*  Bit size of timer/counter.                      */
  71 +#define TIMER_FLAG_16BIT                0x0000
  72 +#define TIMER_FLAG_32BIT                0x0001
  73 +/*  Switch between timer and counter.               */
  74 +#define TIMER_FLAG_TIMER                0x0000
  75 +#define TIMER_FLAG_COUNTER              0x0002
  76 +/*  Stop or continue when overflowing/underflowing. */
  77 +#define TIMER_FLAG_ONCE                 0x0000
  78 +#define TIMER_FLAG_CYCLIC               0x0004
  79 +/*  Count up or counter down.                       */
  80 +#define TIMER_FLAG_UP                   0x0000
  81 +#define TIMER_FLAG_DOWN                 0x0008
  82 +/*  Count on specific level or edge.                */
  83 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
  84 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
  85 +#define TIMER_FLAG_RISE_EDGE            0x0010
  86 +#define TIMER_FLAG_FALL_EDGE            0x0020
  87 +#define TIMER_FLAG_ANY_EDGE             0x0030
  88 +/*  Signal is syncronous to module clock or not.    */
  89 +#define TIMER_FLAG_UNSYNC               0x0000
  90 +#define TIMER_FLAG_SYNC                 0x0080
  91 +/*  Different interrupt handle type.                */
  92 +#define TIMER_FLAG_NO_HANDLE            0x0000
  93 +#if defined(__KERNEL__)
  94 +    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
  95 +#endif  //  defined(__KERNEL__)
  96 +#define TIMER_FLAG_SIGNAL               0x0300
  97 +/*  Internal clock source or external clock source  */
  98 +#define TIMER_FLAG_INT_SRC              0x0000
  99 +#define TIMER_FLAG_EXT_SRC              0x1000
 100 +
 101 +
 102 +/*
 103 + *  ioctl Command
 104 + */
 105 +#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
 106 +#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
 107 +#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
 108 +#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
 109 +#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
 110 +#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
 111 +#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
 112 +#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
 113 +
 114 +/*
 115 + *  Data Type Used to Call ioctl
 116 + */
 117 +struct gptu_ioctl_param {
 118 +    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 119 +                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
 120 +                                                 *  timer/counter. If it's zero, a timer/counter would  *
 121 +                                                 *  be dynamically allocated and ID would be stored in  *
 122 +                                                 *  this field.                                         *
 123 +                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
 124 +                                                 *  ignored.                                            *
 125 +                                                 *  In other command, this field is ID of timer/counter *
 126 +                                                 *  allocated.                                          */
 127 +    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
 128 +                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
 129 +                                                 *  specify how to configure timer/counter.             *
 130 +                                                 *  In command GPTU_START_TIMER, zero indicate start    *
 131 +                                                 *  and non-zero indicate resume timer/counter.         *
 132 +                                                 *  In other command, this field is ignored.            */
 133 +    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
 134 +                                                 *  init/reload value.                                  *
 135 +                                                 *  In command GPTU_SET_TIMER, this field contains      *
 136 +                                                 *  frequency (0.001Hz) of timer.                       *
 137 +                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
 138 +                                                 *  value would be stored in this field.                *
 139 +                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
 140 +                                                 *  contains frequency wanted, and after calculation,   *
 141 +                                                 *  divider would be stored in this field to overwrite  *
 142 +                                                 *  the frequency.                                      *
 143 +                                                 *  In other command, this field is ignored.            */
 144 +    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 145 +                                                 *  if signal is required, this field contains process  *
 146 +                                                 *  ID to which signal would be sent.                   *
 147 +                                                 *  In other command, this field is ignored.            */
 148 +    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
 149 +                                                 *  if signal is required, this field contains signal   *
 150 +                                                 *  number which would be sent.                         *
 151 +                                                 *  In other command, this field is ignored.            */
 152 +};
 153 +
 154 +/*
 155 + * ####################################
 156 + *              Data Type
 157 + * ####################################
 158 + */
 159 +typedef void (*timer_callback)(unsigned long arg);
 160 +
 161 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
 162 +extern int lq_free_timer(unsigned int);
 163 +extern int lq_start_timer(unsigned int, int);
 164 +extern int lq_stop_timer(unsigned int);
 165 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
 166 +extern int lq_get_count_value(unsigned int, unsigned long *);
 167 +extern u32 lq_cal_divider(unsigned long);
 168 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
 169 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
 170 +       u32 reload, unsigned long arg1, unsigned long arg2);
 171 +
 172 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
 173 --- a/arch/mips/lantiq/xway/Makefile
 174 +++ b/arch/mips/lantiq/xway/Makefile
 175 @@ -1,4 +1,10 @@
 176  # SPDX-License-Identifier: GPL-2.0-only
 177 -obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
 178 +obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o
 179 +
 180 +ifdef CONFIG_SOC_AMAZON_SE
 181 +obj-y += gptu.o
 182 +else
 183 +obj-y += timer.o
 184 +endif
 185
 186  obj-y += vmmc.o
 187 --- /dev/null
 188 +++ b/arch/mips/lantiq/xway/timer.c
 189 @@ -0,0 +1,887 @@
 190 +#ifndef CONFIG_SOC_AMAZON_SE
 191 +
 192 +#include <linux/kernel.h>
 193 +#include <linux/module.h>
 194 +#include <linux/version.h>
 195 +#include <linux/types.h>
 196 +#include <linux/fs.h>
 197 +#include <linux/miscdevice.h>
 198 +#include <linux/init.h>
 199 +#include <linux/uaccess.h>
 200 +#include <linux/unistd.h>
 201 +#include <linux/errno.h>
 202 +#include <linux/interrupt.h>
 203 +#include <linux/sched.h>
 204 +#include <linux/sched/signal.h>
 205 +
 206 +#include <linux/of_platform.h>
 207 +
 208 +#include <asm/irq.h>
 209 +#include <asm/div64.h>
 210 +#include "../clk.h"
 211 +
 212 +#include <lantiq_soc.h>
 213 +#include <lantiq_irq.h>
 214 +#include <lantiq_timer.h>
 215 +
 216 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS  6
 217 +
 218 +#ifdef TIMER1A
 219 +#define FIRST_TIMER                    TIMER1A
 220 +#else
 221 +#define FIRST_TIMER                    2
 222 +#endif
 223 +
 224 +/*
 225 + *  GPTC divider is set or not.
 226 + */
 227 +#define GPTU_CLC_RMC_IS_SET            0
 228 +
 229 +/*
 230 + *  Timer Interrupt (IRQ)
 231 + */
 232 +/*  Must be adjusted when ICU driver is available */
 233 +#define TIMER_INTERRUPT                        (INT_NUM_IM3_IRL0 + 22)
 234 +
 235 +/*
 236 + *  Bits Operation
 237 + */
 238 +#define GET_BITS(x, msb, lsb)          \
 239 +       (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
 240 +#define SET_BITS(x, msb, lsb, value)   \
 241 +       (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
 242 +       (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
 243 +
 244 +/*
 245 + *  GPTU Register Mapping
 246 + */
 247 +#define LQ_GPTU                        (KSEG1 + 0x1E100A00)
 248 +#define LQ_GPTU_CLC            ((volatile u32 *)(LQ_GPTU + 0x0000))
 249 +#define LQ_GPTU_ID                     ((volatile u32 *)(LQ_GPTU + 0x0008))
 250 +#define LQ_GPTU_CON(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 251 +#define LQ_GPTU_RUN(n, X)              ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 252 +#define LQ_GPTU_RELOAD(n, X)   ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 253 +#define LQ_GPTU_COUNT(n, X)    ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020))   /* X must be either A or B */
 254 +#define LQ_GPTU_IRNEN          ((volatile u32 *)(LQ_GPTU + 0x00F4))
 255 +#define LQ_GPTU_IRNICR         ((volatile u32 *)(LQ_GPTU + 0x00F8))
 256 +#define LQ_GPTU_IRNCR          ((volatile u32 *)(LQ_GPTU + 0x00FC))
 257 +
 258 +/*
 259 + *  Clock Control Register
 260 + */
 261 +#define GPTU_CLC_SMC                   GET_BITS(*LQ_GPTU_CLC, 23, 16)
 262 +#define GPTU_CLC_RMC                   GET_BITS(*LQ_GPTU_CLC, 15, 8)
 263 +#define GPTU_CLC_FSOE                  (*LQ_GPTU_CLC & (1 << 5))
 264 +#define GPTU_CLC_EDIS                  (*LQ_GPTU_CLC & (1 << 3))
 265 +#define GPTU_CLC_SPEN                  (*LQ_GPTU_CLC & (1 << 2))
 266 +#define GPTU_CLC_DISS                  (*LQ_GPTU_CLC & (1 << 1))
 267 +#define GPTU_CLC_DISR                  (*LQ_GPTU_CLC & (1 << 0))
 268 +
 269 +#define GPTU_CLC_SMC_SET(value)                SET_BITS(0, 23, 16, (value))
 270 +#define GPTU_CLC_RMC_SET(value)                SET_BITS(0, 15, 8, (value))
 271 +#define GPTU_CLC_FSOE_SET(value)       ((value) ? (1 << 5) : 0)
 272 +#define GPTU_CLC_SBWE_SET(value)       ((value) ? (1 << 4) : 0)
 273 +#define GPTU_CLC_EDIS_SET(value)       ((value) ? (1 << 3) : 0)
 274 +#define GPTU_CLC_SPEN_SET(value)       ((value) ? (1 << 2) : 0)
 275 +#define GPTU_CLC_DISR_SET(value)       ((value) ? (1 << 0) : 0)
 276 +
 277 +/*
 278 + *  ID Register
 279 + */
 280 +#define GPTU_ID_ID                     GET_BITS(*LQ_GPTU_ID, 15, 8)
 281 +#define GPTU_ID_CFG                    GET_BITS(*LQ_GPTU_ID, 7, 5)
 282 +#define GPTU_ID_REV                    GET_BITS(*LQ_GPTU_ID, 4, 0)
 283 +
 284 +/*
 285 + *  Control Register of Timer/Counter nX
 286 + *    n is the index of block (1 based index)
 287 + *    X is either A or B
 288 + */
 289 +#define GPTU_CON_SRC_EG(n, X)          (*LQ_GPTU_CON(n, X) & (1 << 10))
 290 +#define GPTU_CON_SRC_EXT(n, X)         (*LQ_GPTU_CON(n, X) & (1 << 9))
 291 +#define GPTU_CON_SYNC(n, X)            (*LQ_GPTU_CON(n, X) & (1 << 8))
 292 +#define GPTU_CON_EDGE(n, X)            GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
 293 +#define GPTU_CON_INV(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 5))
 294 +#define GPTU_CON_EXT(n, X)             (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
 295 +#define GPTU_CON_STP(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 3))
 296 +#define GPTU_CON_CNT(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 2))
 297 +#define GPTU_CON_DIR(n, X)             (*LQ_GPTU_CON(n, X) & (1 << 1))
 298 +#define GPTU_CON_EN(n, X)              (*LQ_GPTU_CON(n, X) & (1 << 0))
 299 +
 300 +#define GPTU_CON_SRC_EG_SET(value)     ((value) ? 0 : (1 << 10))
 301 +#define GPTU_CON_SRC_EXT_SET(value)    ((value) ? (1 << 9) : 0)
 302 +#define GPTU_CON_SYNC_SET(value)       ((value) ? (1 << 8) : 0)
 303 +#define GPTU_CON_EDGE_SET(value)       SET_BITS(0, 7, 6, (value))
 304 +#define GPTU_CON_INV_SET(value)                ((value) ? (1 << 5) : 0)
 305 +#define GPTU_CON_EXT_SET(value)                ((value) ? (1 << 4) : 0)
 306 +#define GPTU_CON_STP_SET(value)                ((value) ? (1 << 3) : 0)
 307 +#define GPTU_CON_CNT_SET(value)                ((value) ? (1 << 2) : 0)
 308 +#define GPTU_CON_DIR_SET(value)                ((value) ? (1 << 1) : 0)
 309 +
 310 +#define GPTU_RUN_RL_SET(value)         ((value) ? (1 << 2) : 0)
 311 +#define GPTU_RUN_CEN_SET(value)                ((value) ? (1 << 1) : 0)
 312 +#define GPTU_RUN_SEN_SET(value)                ((value) ? (1 << 0) : 0)
 313 +
 314 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 315 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
 316 +
 317 +#define TIMER_FLAG_MASK_SIZE(x)                (x & 0x0001)
 318 +#define TIMER_FLAG_MASK_TYPE(x)                (x & 0x0002)
 319 +#define TIMER_FLAG_MASK_STOP(x)                (x & 0x0004)
 320 +#define TIMER_FLAG_MASK_DIR(x)         (x & 0x0008)
 321 +#define TIMER_FLAG_NONE_EDGE           0x0000
 322 +#define TIMER_FLAG_MASK_EDGE(x)                (x & 0x0030)
 323 +#define TIMER_FLAG_REAL                        0x0000
 324 +#define TIMER_FLAG_INVERT              0x0040
 325 +#define TIMER_FLAG_MASK_INVERT(x)      (x & 0x0040)
 326 +#define TIMER_FLAG_MASK_TRIGGER(x)     (x & 0x0070)
 327 +#define TIMER_FLAG_MASK_SYNC(x)                (x & 0x0080)
 328 +#define TIMER_FLAG_CALLBACK_IN_HB      0x0200
 329 +#define TIMER_FLAG_MASK_HANDLE(x)      (x & 0x0300)
 330 +#define TIMER_FLAG_MASK_SRC(x)         (x & 0x1000)
 331 +
 332 +struct timer_dev_timer {
 333 +       unsigned int f_irq_on;
 334 +       unsigned int irq;
 335 +       unsigned int flag;
 336 +       unsigned long arg1;
 337 +       unsigned long arg2;
 338 +};
 339 +
 340 +struct timer_dev {
 341 +       struct mutex gptu_mutex;
 342 +       unsigned int number_of_timers;
 343 +       unsigned int occupation;
 344 +       unsigned int f_gptu_on;
 345 +       struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
 346 +};
 347 +
 348 +
 349 +unsigned int ltq_get_fpi_bus_clock(int fpi) {
 350 +       struct clk *clk = clk_get_fpi();
 351 +       return clk_get_rate(clk);
 352 +}
 353 +
 354 +
 355 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
 356 +static int gptu_open(struct inode *, struct file *);
 357 +static int gptu_release(struct inode *, struct file *);
 358 +
 359 +static struct file_operations gptu_fops = {
 360 +       .owner = THIS_MODULE,
 361 +       .unlocked_ioctl = gptu_ioctl,
 362 +       .open = gptu_open,
 363 +       .release = gptu_release
 364 +};
 365 +
 366 +static struct miscdevice gptu_miscdev = {
 367 +       .minor = MISC_DYNAMIC_MINOR,
 368 +       .name = "gptu",
 369 +       .fops = &gptu_fops,
 370 +};
 371 +
 372 +static struct timer_dev timer_dev;
 373 +
 374 +static irqreturn_t timer_irq_handler(int irq, void *p)
 375 +{
 376 +       unsigned int timer;
 377 +       unsigned int flag;
 378 +       struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
 379 +
 380 +       timer = irq - TIMER_INTERRUPT;
 381 +       if (timer < timer_dev.number_of_timers
 382 +               && dev_timer == &timer_dev.timer[timer]) {
 383 +               /*  Clear interrupt.    */
 384 +               ltq_w32(1 << timer, LQ_GPTU_IRNCR);
 385 +
 386 +               /*  Call user hanler or signal. */
 387 +               flag = dev_timer->flag;
 388 +               if (!(timer & 0x01)
 389 +                       || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 390 +                       /* 16-bit timer or timer A of 32-bit timer  */
 391 +                       switch (TIMER_FLAG_MASK_HANDLE(flag)) {
 392 +                       case TIMER_FLAG_CALLBACK_IN_IRQ:
 393 +                       case TIMER_FLAG_CALLBACK_IN_HB:
 394 +                               if (dev_timer->arg1)
 395 +                                       (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
 396 +                               break;
 397 +                       case TIMER_FLAG_SIGNAL:
 398 +                               send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
 399 +                               break;
 400 +                       }
 401 +               }
 402 +       }
 403 +       return IRQ_HANDLED;
 404 +}
 405 +
 406 +static inline void lq_enable_gptu(void)
 407 +{
 408 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 409 +       clk_enable(clk);
 410 +
 411 +       //ltq_pmu_enable(PMU_GPT);
 412 +
 413 +       /*  Set divider as 1, disable write protection for SPEN, enable module. */
 414 +       *LQ_GPTU_CLC =
 415 +               GPTU_CLC_SMC_SET(0x00) |
 416 +               GPTU_CLC_RMC_SET(0x01) |
 417 +               GPTU_CLC_FSOE_SET(0) |
 418 +               GPTU_CLC_SBWE_SET(1) |
 419 +               GPTU_CLC_EDIS_SET(0) |
 420 +               GPTU_CLC_SPEN_SET(0) |
 421 +               GPTU_CLC_DISR_SET(0);
 422 +}
 423 +
 424 +static inline void lq_disable_gptu(void)
 425 +{
 426 +       struct clk *clk = clk_get_sys("1e100a00.gptu", NULL);
 427 +       ltq_w32(0x00, LQ_GPTU_IRNEN);
 428 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 429 +
 430 +       /*  Set divider as 0, enable write protection for SPEN, disable module. */
 431 +       *LQ_GPTU_CLC =
 432 +               GPTU_CLC_SMC_SET(0x00) |
 433 +               GPTU_CLC_RMC_SET(0x00) |
 434 +               GPTU_CLC_FSOE_SET(0) |
 435 +               GPTU_CLC_SBWE_SET(0) |
 436 +               GPTU_CLC_EDIS_SET(0) |
 437 +               GPTU_CLC_SPEN_SET(0) |
 438 +               GPTU_CLC_DISR_SET(1);
 439 +
 440 +       clk_enable(clk);
 441 +}
 442 +
 443 +int lq_request_timer(unsigned int timer, unsigned int flag,
 444 +       unsigned long value, unsigned long arg1, unsigned long arg2)
 445 +{
 446 +       int ret = 0;
 447 +       unsigned int con_reg, irnen_reg;
 448 +       int n, X;
 449 +
 450 +       if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
 451 +               return -EINVAL;
 452 +
 453 +       printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
 454 +               timer, flag, value);
 455 +
 456 +       if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
 457 +               value &= 0xFFFF;
 458 +       else
 459 +               timer &= ~0x01;
 460 +
 461 +       mutex_lock(&timer_dev.gptu_mutex);
 462 +
 463 +       /*
 464 +        *  Allocate timer.
 465 +        */
 466 +       if (timer < FIRST_TIMER) {
 467 +               unsigned int mask;
 468 +               unsigned int shift;
 469 +               /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
 470 +               unsigned int offset = TIMER2A;
 471 +
 472 +               /*
 473 +                *  Pick up a free timer.
 474 +                */
 475 +               if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
 476 +                       mask = 1 << offset;
 477 +                       shift = 1;
 478 +               } else {
 479 +                       mask = 3 << offset;
 480 +                       shift = 2;
 481 +               }
 482 +               for (timer = offset;
 483 +                    timer < offset + timer_dev.number_of_timers;
 484 +                    timer += shift, mask <<= shift)
 485 +                       if (!(timer_dev.occupation & mask)) {
 486 +                               timer_dev.occupation |= mask;
 487 +                               break;
 488 +                       }
 489 +               if (timer >= offset + timer_dev.number_of_timers) {
 490 +                       printk("failed![%d]\n", __LINE__);
 491 +                       mutex_unlock(&timer_dev.gptu_mutex);
 492 +                       return -EINVAL;
 493 +               } else
 494 +                       ret = timer;
 495 +       } else {
 496 +               register unsigned int mask;
 497 +
 498 +               /*
 499 +                *  Check if the requested timer is free.
 500 +                */
 501 +               mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 502 +               if ((timer_dev.occupation & mask)) {
 503 +                       printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
 504 +                               __LINE__, mask, timer_dev.occupation);
 505 +                       mutex_unlock(&timer_dev.gptu_mutex);
 506 +                       return -EBUSY;
 507 +               } else {
 508 +                       timer_dev.occupation |= mask;
 509 +                       ret = 0;
 510 +               }
 511 +       }
 512 +
 513 +       /*
 514 +        *  Prepare control register value.
 515 +        */
 516 +       switch (TIMER_FLAG_MASK_EDGE(flag)) {
 517 +       default:
 518 +       case TIMER_FLAG_NONE_EDGE:
 519 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 520 +               break;
 521 +       case TIMER_FLAG_RISE_EDGE:
 522 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 523 +               break;
 524 +       case TIMER_FLAG_FALL_EDGE:
 525 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 526 +               break;
 527 +       case TIMER_FLAG_ANY_EDGE:
 528 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 529 +               break;
 530 +       }
 531 +       if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
 532 +               con_reg |=
 533 +                       TIMER_FLAG_MASK_SRC(flag) ==
 534 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
 535 +                       GPTU_CON_SRC_EXT_SET(0);
 536 +       else
 537 +               con_reg |=
 538 +                       TIMER_FLAG_MASK_SRC(flag) ==
 539 +                       TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
 540 +                       GPTU_CON_SRC_EG_SET(0);
 541 +       con_reg |=
 542 +               TIMER_FLAG_MASK_SYNC(flag) ==
 543 +               TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
 544 +               GPTU_CON_SYNC_SET(1);
 545 +       con_reg |=
 546 +               TIMER_FLAG_MASK_INVERT(flag) ==
 547 +               TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 548 +       con_reg |=
 549 +               TIMER_FLAG_MASK_SIZE(flag) ==
 550 +               TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
 551 +               GPTU_CON_EXT_SET(1);
 552 +       con_reg |=
 553 +               TIMER_FLAG_MASK_STOP(flag) ==
 554 +               TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 555 +       con_reg |=
 556 +               TIMER_FLAG_MASK_TYPE(flag) ==
 557 +               TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
 558 +               GPTU_CON_CNT_SET(1);
 559 +       con_reg |=
 560 +               TIMER_FLAG_MASK_DIR(flag) ==
 561 +               TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 562 +
 563 +       /*
 564 +        *  Fill up running data.
 565 +        */
 566 +       timer_dev.timer[timer - FIRST_TIMER].flag = flag;
 567 +       timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
 568 +       timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
 569 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 570 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
 571 +
 572 +       /*
 573 +        *  Enable GPTU module.
 574 +        */
 575 +       if (!timer_dev.f_gptu_on) {
 576 +               lq_enable_gptu();
 577 +               timer_dev.f_gptu_on = 1;
 578 +       }
 579 +
 580 +       /*
 581 +        *  Enable IRQ.
 582 +        */
 583 +       if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
 584 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
 585 +                       timer_dev.timer[timer - FIRST_TIMER].arg1 =
 586 +                               (unsigned long) find_task_by_vpid((int) arg1);
 587 +
 588 +               irnen_reg = 1 << (timer - FIRST_TIMER);
 589 +
 590 +               if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
 591 +                   || (TIMER_FLAG_MASK_HANDLE(flag) ==
 592 +                       TIMER_FLAG_CALLBACK_IN_IRQ
 593 +                       && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
 594 +                       enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 595 +                       timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
 596 +               }
 597 +       } else
 598 +               irnen_reg = 0;
 599 +
 600 +       /*
 601 +        *  Write config register, reload value and enable interrupt.
 602 +        */
 603 +       n = timer >> 1;
 604 +       X = timer & 0x01;
 605 +       *LQ_GPTU_CON(n, X) = con_reg;
 606 +       *LQ_GPTU_RELOAD(n, X) = value;
 607 +       /* printk("reload value = %d\n", (u32)value); */
 608 +       *LQ_GPTU_IRNEN |= irnen_reg;
 609 +
 610 +       mutex_unlock(&timer_dev.gptu_mutex);
 611 +       printk("successful!\n");
 612 +       return ret;
 613 +}
 614 +EXPORT_SYMBOL(lq_request_timer);
 615 +
 616 +int lq_free_timer(unsigned int timer)
 617 +{
 618 +       unsigned int flag;
 619 +       unsigned int mask;
 620 +       int n, X;
 621 +
 622 +       if (!timer_dev.f_gptu_on)
 623 +               return -EINVAL;
 624 +
 625 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 626 +               return -EINVAL;
 627 +
 628 +       mutex_lock(&timer_dev.gptu_mutex);
 629 +
 630 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 631 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 632 +               timer &= ~0x01;
 633 +
 634 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 635 +       if (((timer_dev.occupation & mask) ^ mask)) {
 636 +               mutex_unlock(&timer_dev.gptu_mutex);
 637 +               return -EINVAL;
 638 +       }
 639 +
 640 +       n = timer >> 1;
 641 +       X = timer & 0x01;
 642 +
 643 +       if (GPTU_CON_EN(n, X))
 644 +               *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 645 +
 646 +       *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
 647 +       *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
 648 +
 649 +       if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
 650 +               disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
 651 +               timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
 652 +       }
 653 +
 654 +       timer_dev.occupation &= ~mask;
 655 +       if (!timer_dev.occupation && timer_dev.f_gptu_on) {
 656 +               lq_disable_gptu();
 657 +               timer_dev.f_gptu_on = 0;
 658 +       }
 659 +
 660 +       mutex_unlock(&timer_dev.gptu_mutex);
 661 +
 662 +       return 0;
 663 +}
 664 +EXPORT_SYMBOL(lq_free_timer);
 665 +
 666 +int lq_start_timer(unsigned int timer, int is_resume)
 667 +{
 668 +       unsigned int flag;
 669 +       unsigned int mask;
 670 +       int n, X;
 671 +
 672 +       if (!timer_dev.f_gptu_on)
 673 +               return -EINVAL;
 674 +
 675 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 676 +               return -EINVAL;
 677 +
 678 +       mutex_lock(&timer_dev.gptu_mutex);
 679 +
 680 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 681 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 682 +               timer &= ~0x01;
 683 +
 684 +       mask = (TIMER_FLAG_MASK_SIZE(flag) ==
 685 +       TIMER_FLAG_16BIT ? 1 : 3) << timer;
 686 +       if (((timer_dev.occupation & mask) ^ mask)) {
 687 +               mutex_unlock(&timer_dev.gptu_mutex);
 688 +               return -EINVAL;
 689 +       }
 690 +
 691 +       n = timer >> 1;
 692 +       X = timer & 0x01;
 693 +
 694 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
 695 +
 696 +
 697 +       mutex_unlock(&timer_dev.gptu_mutex);
 698 +
 699 +       return 0;
 700 +}
 701 +EXPORT_SYMBOL(lq_start_timer);
 702 +
 703 +int lq_stop_timer(unsigned int timer)
 704 +{
 705 +       unsigned int flag;
 706 +       unsigned int mask;
 707 +       int n, X;
 708 +
 709 +       if (!timer_dev.f_gptu_on)
 710 +               return -EINVAL;
 711 +
 712 +       if (timer < FIRST_TIMER
 713 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 714 +               return -EINVAL;
 715 +
 716 +       mutex_lock(&timer_dev.gptu_mutex);
 717 +
 718 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 719 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 720 +               timer &= ~0x01;
 721 +
 722 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 723 +       if (((timer_dev.occupation & mask) ^ mask)) {
 724 +               mutex_unlock(&timer_dev.gptu_mutex);
 725 +               return -EINVAL;
 726 +       }
 727 +
 728 +       n = timer >> 1;
 729 +       X = timer & 0x01;
 730 +
 731 +       *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
 732 +
 733 +       mutex_unlock(&timer_dev.gptu_mutex);
 734 +
 735 +       return 0;
 736 +}
 737 +EXPORT_SYMBOL(lq_stop_timer);
 738 +
 739 +int lq_reset_counter_flags(u32 timer, u32 flags)
 740 +{
 741 +       unsigned int oflag;
 742 +       unsigned int mask, con_reg;
 743 +       int n, X;
 744 +
 745 +       if (!timer_dev.f_gptu_on)
 746 +               return -EINVAL;
 747 +
 748 +       if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 749 +               return -EINVAL;
 750 +
 751 +       mutex_lock(&timer_dev.gptu_mutex);
 752 +
 753 +       oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
 754 +       if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
 755 +               timer &= ~0x01;
 756 +
 757 +       mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 758 +       if (((timer_dev.occupation & mask) ^ mask)) {
 759 +               mutex_unlock(&timer_dev.gptu_mutex);
 760 +               return -EINVAL;
 761 +       }
 762 +
 763 +       switch (TIMER_FLAG_MASK_EDGE(flags)) {
 764 +       default:
 765 +       case TIMER_FLAG_NONE_EDGE:
 766 +               con_reg = GPTU_CON_EDGE_SET(0x00);
 767 +               break;
 768 +       case TIMER_FLAG_RISE_EDGE:
 769 +               con_reg = GPTU_CON_EDGE_SET(0x01);
 770 +               break;
 771 +       case TIMER_FLAG_FALL_EDGE:
 772 +               con_reg = GPTU_CON_EDGE_SET(0x02);
 773 +               break;
 774 +       case TIMER_FLAG_ANY_EDGE:
 775 +               con_reg = GPTU_CON_EDGE_SET(0x03);
 776 +               break;
 777 +       }
 778 +       if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
 779 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
 780 +       else
 781 +               con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
 782 +       con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
 783 +       con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
 784 +       con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
 785 +       con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
 786 +       con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
 787 +       con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
 788 +
 789 +       timer_dev.timer[timer - FIRST_TIMER].flag = flags;
 790 +       if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
 791 +               timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
 792 +
 793 +       n = timer >> 1;
 794 +       X = timer & 0x01;
 795 +
 796 +       *LQ_GPTU_CON(n, X) = con_reg;
 797 +       smp_wmb();
 798 +       mutex_unlock(&timer_dev.gptu_mutex);
 799 +       return 0;
 800 +}
 801 +EXPORT_SYMBOL(lq_reset_counter_flags);
 802 +
 803 +int lq_get_count_value(unsigned int timer, unsigned long *value)
 804 +{
 805 +       unsigned int flag;
 806 +       unsigned int mask;
 807 +       int n, X;
 808 +
 809 +       if (!timer_dev.f_gptu_on)
 810 +               return -EINVAL;
 811 +
 812 +       if (timer < FIRST_TIMER
 813 +           || timer >= FIRST_TIMER + timer_dev.number_of_timers)
 814 +               return -EINVAL;
 815 +
 816 +       mutex_lock(&timer_dev.gptu_mutex);
 817 +
 818 +       flag = timer_dev.timer[timer - FIRST_TIMER].flag;
 819 +       if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
 820 +               timer &= ~0x01;
 821 +
 822 +       mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
 823 +       if (((timer_dev.occupation & mask) ^ mask)) {
 824 +               mutex_unlock(&timer_dev.gptu_mutex);
 825 +               return -EINVAL;
 826 +       }
 827 +
 828 +       n = timer >> 1;
 829 +       X = timer & 0x01;
 830 +
 831 +       *value = *LQ_GPTU_COUNT(n, X);
 832 +
 833 +
 834 +       mutex_unlock(&timer_dev.gptu_mutex);
 835 +
 836 +       return 0;
 837 +}
 838 +EXPORT_SYMBOL(lq_get_count_value);
 839 +
 840 +u32 lq_cal_divider(unsigned long freq)
 841 +{
 842 +       u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
 843 +       u32 clock_divider = 1;
 844 +       module_freq = fpi * 1000;
 845 +       do_div(module_freq, clock_divider * freq);
 846 +       return module_freq;
 847 +}
 848 +EXPORT_SYMBOL(lq_cal_divider);
 849 +
 850 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
 851 +       int is_ext_src, unsigned int handle_flag, unsigned long arg1,
 852 +       unsigned long arg2)
 853 +{
 854 +       unsigned long divider;
 855 +       unsigned int flag;
 856 +
 857 +       divider = lq_cal_divider(freq);
 858 +       if (divider == 0)
 859 +               return -EINVAL;
 860 +       flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
 861 +               | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
 862 +               | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
 863 +               | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
 864 +               | TIMER_FLAG_MASK_HANDLE(handle_flag);
 865 +
 866 +       printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
 867 +               timer, freq, divider);
 868 +       return lq_request_timer(timer, flag, divider, arg1, arg2);
 869 +}
 870 +EXPORT_SYMBOL(lq_set_timer);
 871 +
 872 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
 873 +       unsigned long arg1, unsigned long arg2)
 874 +{
 875 +       printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
 876 +       return lq_request_timer(timer, flag, reload, arg1, arg2);
 877 +}
 878 +EXPORT_SYMBOL(lq_set_counter);
 879 +
 880 +static long gptu_ioctl(struct file *file, unsigned int cmd,
 881 +       unsigned long arg)
 882 +{
 883 +       int ret;
 884 +       struct gptu_ioctl_param param;
 885 +
 886 +       if (!access_ok((void __user *)arg, sizeof(struct gptu_ioctl_param)))
 887 +               return -EFAULT;
 888 +       if (copy_from_user(&param, (void __user *)arg, sizeof(param)))
 889 +               return -EFAULT;
 890 +
 891 +       if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
 892 +              || GPTU_SET_COUNTER) && param.timer < 2)
 893 +            || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
 894 +           && !access_ok((void __user *)arg,
 895 +                          sizeof(struct gptu_ioctl_param)))
 896 +               return -EFAULT;
 897 +
 898 +       switch (cmd) {
 899 +       case GPTU_REQUEST_TIMER:
 900 +               ret = lq_request_timer(param.timer, param.flag, param.value,
 901 +                                    (unsigned long) param.pid,
 902 +                                    (unsigned long) param.sig);
 903 +               if (ret > 0) {
 904 +                       if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
 905 +                                        timer, &ret, sizeof(&ret)))
 906 +                               ret = -EFAULT;
 907 +                       else
 908 +                               ret = 0;
 909 +               }
 910 +               break;
 911 +       case GPTU_FREE_TIMER:
 912 +               ret = lq_free_timer(param.timer);
 913 +               break;
 914 +       case GPTU_START_TIMER:
 915 +               ret = lq_start_timer(param.timer, param.flag);
 916 +               break;
 917 +       case GPTU_STOP_TIMER:
 918 +               ret = lq_stop_timer(param.timer);
 919 +               break;
 920 +       case GPTU_GET_COUNT_VALUE:
 921 +               ret = lq_get_count_value(param.timer, &param.value);
 922 +               if (!ret && copy_to_user(&((struct gptu_ioctl_param *) arg)->
 923 +                   value, &param.value,sizeof(param.value)))
 924 +                       ret = -EFAULT;
 925 +               break;
 926 +       case GPTU_CALCULATE_DIVIDER:
 927 +               param.value = lq_cal_divider(param.value);
 928 +               if (param.value == 0)
 929 +                       ret = -EINVAL;
 930 +               else if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
 931 +                                     value, &param.value,
 932 +                                     sizeof(param.value)))
 933 +                       ret = -EFAULT;
 934 +               else
 935 +                       ret = 0;
 936 +               break;
 937 +       case GPTU_SET_TIMER:
 938 +               ret = lq_set_timer(param.timer, param.value,
 939 +                                TIMER_FLAG_MASK_STOP(param.flag) !=
 940 +                                TIMER_FLAG_ONCE ? 1 : 0,
 941 +                                TIMER_FLAG_MASK_SRC(param.flag) ==
 942 +                                TIMER_FLAG_EXT_SRC ? 1 : 0,
 943 +                                TIMER_FLAG_MASK_HANDLE(param.flag) ==
 944 +                                TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
 945 +                                TIMER_FLAG_NO_HANDLE,
 946 +                                (unsigned long) param.pid,
 947 +                                (unsigned long) param.sig);
 948 +               if (ret > 0) {
 949 +                       if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
 950 +                                        timer, &ret, sizeof(&ret)))
 951 +                               ret = -EFAULT;
 952 +                       else
 953 +                               ret = 0;
 954 +               }
 955 +               break;
 956 +       case GPTU_SET_COUNTER:
 957 +               lq_set_counter(param.timer, param.flag, param.value, 0, 0);
 958 +               if (ret > 0) {
 959 +                       if (copy_to_user(&((struct gptu_ioctl_param *) arg)->
 960 +                                        timer, &ret, sizeof(&ret)))
 961 +                               ret = -EFAULT;
 962 +                       else
 963 +                               ret = 0;
 964 +               }
 965 +               break;
 966 +       default:
 967 +               ret = -ENOTTY;
 968 +       }
 969 +
 970 +       return ret;
 971 +}
 972 +
 973 +static int gptu_open(struct inode *inode, struct file *file)
 974 +{
 975 +       return 0;
 976 +}
 977 +
 978 +static int gptu_release(struct inode *inode, struct file *file)
 979 +{
 980 +       return 0;
 981 +}
 982 +
 983 +static int gptu_probe(struct platform_device *pdev)
 984 +{
 985 +       int ret;
 986 +       int i;
 987 +
 988 +       ltq_w32(0, LQ_GPTU_IRNEN);
 989 +       ltq_w32(0xfff, LQ_GPTU_IRNCR);
 990 +
 991 +       memset(&timer_dev, 0, sizeof(timer_dev));
 992 +       mutex_init(&timer_dev.gptu_mutex);
 993 +
 994 +       lq_enable_gptu();
 995 +       timer_dev.number_of_timers = GPTU_ID_CFG * 2;
 996 +       lq_disable_gptu();
 997 +       if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
 998 +               timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
 999 +       printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
1000 +
1001 +       ret = misc_register(&gptu_miscdev);
1002 +       if (ret) {
1003 +               printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
1004 +               return ret;
1005 +       } else {
1006 +               printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
1007 +       }
1008 +
1009 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1010 +               int irq = platform_get_irq(pdev, i);
1011 +               if (irq < 0) {
1012 +                       printk(KERN_ERR "gptu: failed in getting irq (%d), get error %d\n", i, irq);
1013 +                       for (i--; i >= 0; i--)
1014 +                               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1015 +                       misc_deregister(&gptu_miscdev);
1016 +                       return irq;
1017 +               }
1018 +
1019 +               ret = request_irq(irq, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
1020 +               if (ret) {
1021 +                       printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
1022 +                       for (i--; i >= 0; i--)
1023 +                               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1024 +                       misc_deregister(&gptu_miscdev);
1025 +                       return ret;
1026 +               } else {
1027 +                       timer_dev.timer[i].irq = irq;
1028 +                       disable_irq(timer_dev.timer[i].irq);
1029 +                       printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
1030 +               }
1031 +       }
1032 +
1033 +       return 0;
1034 +}
1035 +
1036 +static const struct of_device_id gptu_match[] = {
1037 +       { .compatible = "lantiq,gptu-xway" },
1038 +       {},
1039 +};
1040 +MODULE_DEVICE_TABLE(of, gptu_match);
1041 +
1042 +static struct platform_driver gptu_driver = {
1043 +       .probe = gptu_probe,
1044 +       .driver = {
1045 +               .name = "gptu-xway",
1046 +               .owner = THIS_MODULE,
1047 +               .of_match_table = gptu_match,
1048 +       },
1049 +};
1050 +
1051 +int __init lq_gptu_init(void)
1052 +{
1053 +       int ret = platform_driver_register(&gptu_driver);
1054 +
1055 +       if (ret)
1056 +               pr_info("gptu: Error registering platform driver\n");
1057 +       return ret;
1058 +}
1059 +
1060 +void __exit lq_gptu_exit(void)
1061 +{
1062 +       unsigned int i;
1063 +
1064 +       for (i = 0; i < timer_dev.number_of_timers; i++) {
1065 +               if (timer_dev.timer[i].f_irq_on)
1066 +                       disable_irq(timer_dev.timer[i].irq);
1067 +               free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
1068 +       }
1069 +       lq_disable_gptu();
1070 +       misc_deregister(&gptu_miscdev);
1071 +}
1072 +
1073 +module_init(lq_gptu_init);
1074 +module_exit(lq_gptu_exit);
1075 +
1076 +#endif