1 From 62ac0c4fda3b40a8994f2abfdc52784ced80c83b Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Wed, 17 Apr 2019 18:58:51 +0800
4 Subject: [PATCH] pm: support layerscape
6 This is an integrated patch of pm for layerscape
8 Signed-off-by: Biwen Li <biwen.li@nxp.com>
9 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
10 Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
11 Signed-off-by: Li Yang <leoyang.li@nxp.com>
12 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
13 Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
14 Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
15 Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
17 drivers/firmware/psci.c | 16 ++-
18 drivers/soc/fsl/rcpm.c | 156 ++++++++++++++++++++
19 drivers/soc/fsl/sleep_fsm.c | 279 ++++++++++++++++++++++++++++++++++++
20 drivers/soc/fsl/sleep_fsm.h | 130 +++++++++++++++++
21 4 files changed, 579 insertions(+), 2 deletions(-)
22 create mode 100644 drivers/soc/fsl/rcpm.c
23 create mode 100644 drivers/soc/fsl/sleep_fsm.c
24 create mode 100644 drivers/soc/fsl/sleep_fsm.h
26 --- a/drivers/firmware/psci.c
27 +++ b/drivers/firmware/psci.c
28 @@ -437,8 +437,18 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
30 static int psci_system_suspend(unsigned long unused)
32 - return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
33 - __pa_symbol(cpu_resume), 0, 0);
35 + u32 ver = psci_get_version();
37 + if (PSCI_VERSION_MAJOR(ver) >= 1) {
38 + return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
39 + virt_to_phys(cpu_resume), 0, 0);
41 + state = ( 2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
42 + (1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
44 + return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
48 static int psci_system_suspend_enter(suspend_state_t state)
49 @@ -562,6 +572,8 @@ static void __init psci_0_2_set_function
50 arm_pm_restart = psci_sys_reset;
52 pm_power_off = psci_sys_poweroff;
54 + suspend_set_ops(&psci_suspend_ops);
59 +++ b/drivers/soc/fsl/rcpm.c
62 + * Run Control and Power Management (RCPM) driver
64 + * Copyright 2016 NXP
66 + * This program is free software; you can redistribute it and/or modify
67 + * it under the terms of the GNU General Public License as published by
68 + * the Free Software Foundation; either version 2 of the License, or
69 + * (at your option) any later version.
71 + * This program is distributed in the hope that it will be useful,
72 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
73 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
74 + * GNU General Public License for more details.
77 +#define pr_fmt(fmt) "RCPM: %s: " fmt, __func__
79 +#include <linux/kernel.h>
80 +#include <linux/io.h>
81 +#include <linux/of_platform.h>
82 +#include <linux/of_address.h>
83 +#include <linux/suspend.h>
85 +/* RCPM register offset */
86 +#define RCPM_IPPDEXPCR0 0x140
88 +#define RCPM_WAKEUP_CELL_SIZE 2
92 + int ippdexpcr_offset;
94 + void *rcpm_reg_base;
97 +static struct rcpm_config *rcpm;
99 +static inline void rcpm_reg_write(u32 offset, u32 value)
101 + iowrite32be(value, rcpm->rcpm_reg_base + offset);
104 +static inline u32 rcpm_reg_read(u32 offset)
106 + return ioread32be(rcpm->rcpm_reg_base + offset);
109 +static void rcpm_wakeup_fixup(struct device *dev, void *data)
111 + struct device_node *node = dev ? dev->of_node : NULL;
112 + u32 value[RCPM_WAKEUP_CELL_SIZE];
115 + if (!dev || !node || !device_may_wakeup(dev))
119 + * Get the values in the "rcpm-wakeup" property.
120 + * Three values are:
121 + * The first is a pointer to the RCPM node.
122 + * The second is the value of the ippdexpcr0 register.
123 + * The third is the value of the ippdexpcr1 register.
125 + ret = of_property_read_u32_array(node, "fsl,rcpm-wakeup",
126 + value, RCPM_WAKEUP_CELL_SIZE);
130 + pr_debug("wakeup source: the device %s\n", node->full_name);
132 + for (i = 0; i < rcpm->ipp_num; i++)
133 + rcpm->ippdexpcr[i] |= value[i + 1];
136 +static int rcpm_suspend_prepare(void)
143 + for (i = 0; i < rcpm->ipp_num; i++)
144 + rcpm->ippdexpcr[i] = 0;
146 + dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
148 + for (i = 0; i < rcpm->ipp_num; i++) {
149 + if (rcpm->ippdexpcr[i]) {
150 + val = rcpm_reg_read(rcpm->ippdexpcr_offset + 4 * i);
151 + rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
152 + val | rcpm->ippdexpcr[i]);
153 + pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
160 +static int rcpm_suspend_notifier_call(struct notifier_block *bl,
161 + unsigned long state,
165 + case PM_SUSPEND_PREPARE:
166 + rcpm_suspend_prepare();
170 + return NOTIFY_DONE;
173 +static struct rcpm_config rcpm_default_config = {
175 + .ippdexpcr_offset = RCPM_IPPDEXPCR0,
178 +static const struct of_device_id rcpm_matches[] = {
180 + .compatible = "fsl,qoriq-rcpm-2.1",
181 + .data = &rcpm_default_config,
186 +static struct notifier_block rcpm_suspend_notifier = {
187 + .notifier_call = rcpm_suspend_notifier_call,
190 +static int __init layerscape_rcpm_init(void)
192 + const struct of_device_id *match;
193 + struct device_node *np;
195 + np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
200 + rcpm = (struct rcpm_config *)match->data;
204 + rcpm->rcpm_reg_base = of_iomap(np, 0);
206 + if (!rcpm->rcpm_reg_base)
209 + register_pm_notifier(&rcpm_suspend_notifier);
211 + pr_info("The RCPM driver initialized.\n");
216 +subsys_initcall(layerscape_rcpm_init);
218 +++ b/drivers/soc/fsl/sleep_fsm.c
221 + * deep sleep FSM (finite-state machine) configuration
223 + * Copyright 2018 NXP
225 + * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
226 + * Chenhui Zhao <chenhui.zhao@freescale.com>
228 + * Redistribution and use in source and binary forms, with or without
229 + * modification, are permitted provided that the following conditions are met:
230 + * * Redistributions of source code must retain the above copyright
231 + * notice, this list of conditions and the following disclaimer.
232 + * * Redistributions in binary form must reproduce the above copyright
233 + * notice, this list of conditions and the following disclaimer in the
234 + * documentation and/or other materials provided with the distribution.
235 + * * Neither the name of the above-listed copyright holders nor the
236 + * names of any contributors may be used to endorse or promote products
237 + * derived from this software without specific prior written permission.
239 + * ALTERNATIVELY, this software may be distributed under the terms of the
240 + * GNU General Public License ("GPL") as published by the Free Software
241 + * Foundation, either version 2 of that License or (at your option) any
244 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
245 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
246 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
247 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
248 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
249 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
250 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
251 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
252 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
253 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
254 + * POSSIBILITY OF SUCH DAMAGE.
257 +#include <linux/kernel.h>
258 +#include <linux/io.h>
259 +#include <linux/types.h>
261 +#include "sleep_fsm.h"
263 + * These values are from chip's reference manual. For example,
264 + * the values for T1040 can be found in "8.4.3.8 Programming
265 + * supporting deep sleep mode" of Chapter 8 "Run Control and
266 + * Power Management (RCPM)".
267 + * The default value can be applied to T104x, LS1021.
269 +struct fsm_reg_vals epu_default_val[] = {
270 + /* EPGCR (Event Processor Global Control Register) */
272 + /* EPECR (Event Processor Event Control Registers) */
273 + {EPECR0 + EPECR_STRIDE * 0, 0},
274 + {EPECR0 + EPECR_STRIDE * 1, 0},
275 + {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
276 + {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
277 + {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
278 + {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
279 + {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
280 + {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
281 + {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
282 + {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
283 + {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
284 + {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
285 + {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
286 + {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
287 + {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
288 + {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
290 + * EPEVTCR (Event Processor EVT Pin Control Registers)
291 + * SCU8 triger EVT2, and SCU11 triger EVT9
293 + {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
294 + {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
295 + {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
296 + {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
297 + {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
298 + {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
299 + {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
300 + {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
301 + {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
302 + {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
303 + /* EPCMPR (Event Processor Counter Compare Registers) */
304 + {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
305 + {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
306 + {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
307 + {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
308 + {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
309 + {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
310 + {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
311 + {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
312 + {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
313 + {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
314 + {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
315 + {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
316 + {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
317 + {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
318 + {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
319 + {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
320 + /* EPCCR (Event Processor Counter Control Registers) */
321 + {EPCCR0 + EPCCR_STRIDE * 0, 0},
322 + {EPCCR0 + EPCCR_STRIDE * 1, 0},
323 + {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
324 + {EPCCR0 + EPCCR_STRIDE * 3, 0},
325 + {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
326 + {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
327 + {EPCCR0 + EPCCR_STRIDE * 6, 0},
328 + {EPCCR0 + EPCCR_STRIDE * 7, 0},
329 + {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
330 + {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
331 + {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
332 + {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
333 + {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
334 + {EPCCR0 + EPCCR_STRIDE * 13, 0},
335 + {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
336 + {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
337 + /* EPSMCR (Event Processor SCU Mux Control Registers) */
338 + {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
339 + {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
340 + {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
341 + {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
342 + {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
343 + {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
344 + {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
345 + {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
346 + {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
347 + {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
348 + {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
349 + {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
350 + {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
351 + {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
352 + {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
353 + {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
354 + /* EPACR (Event Processor Action Control Registers) */
355 + {EPACR0 + EPACR_STRIDE * 0, 0},
356 + {EPACR0 + EPACR_STRIDE * 1, 0},
357 + {EPACR0 + EPACR_STRIDE * 2, 0},
358 + {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
359 + {EPACR0 + EPACR_STRIDE * 4, 0},
360 + {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
361 + {EPACR0 + EPACR_STRIDE * 6, 0},
362 + {EPACR0 + EPACR_STRIDE * 7, 0},
363 + {EPACR0 + EPACR_STRIDE * 8, 0},
364 + {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
365 + {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
366 + {EPACR0 + EPACR_STRIDE * 11, 0},
367 + {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
368 + {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
369 + {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
370 + {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
371 + /* EPIMCR (Event Processor Input Mux Control Registers) */
372 + {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
373 + {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
374 + {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
375 + {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
376 + {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
377 + {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
378 + {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
379 + {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
380 + {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
381 + {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
382 + {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
383 + {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
384 + {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
385 + {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
386 + {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
387 + {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
388 + {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
389 + {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
390 + {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
391 + {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
392 + {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
393 + {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
394 + {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
395 + {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
396 + {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
397 + {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
398 + {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
399 + {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
400 + {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
401 + {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
402 + {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
403 + {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
404 + /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
405 + {EPXTRIGCR, 0x0000FFDF},
410 +struct fsm_reg_vals npc_default_val[] = {
411 + /* NPC triggered Memory-Mapped Access Registers */
422 + {MCSR3, 0x80000000},
423 + {MMAR3LO, 0x000E2130},
424 + {MMAR3HI, 0x00030000},
425 + {MMDR3, 0x00020000},
431 + * fsl_fsm_setup - Configure EPU's FSM registers
432 + * @base: the base address of registers
433 + * @val: Pointer to address-value pairs for FSM registers
435 +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
437 + struct fsm_reg_vals *data = val;
439 + WARN_ON(!base || !data);
440 + while (data->offset != FSM_END_FLAG) {
441 + iowrite32be(data->value, base + data->offset);
446 +void fsl_epu_setup_default(void __iomem *epu_base)
448 + fsl_fsm_setup(epu_base, epu_default_val);
451 +void fsl_npc_setup_default(void __iomem *npc_base)
453 + fsl_fsm_setup(npc_base, npc_default_val);
456 +void fsl_epu_clean_default(void __iomem *epu_base)
460 + /* follow the exact sequence to clear the registers */
462 + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
463 + iowrite32be(0, epu_base + offset);
465 + /* Clear EPEVTCRn */
466 + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
467 + iowrite32be(0, epu_base + offset);
470 + iowrite32be(0, epu_base + EPGCR);
472 + /* Clear EPSMCRn */
473 + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
474 + iowrite32be(0, epu_base + offset);
477 + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
478 + iowrite32be(0, epu_base + offset);
480 + /* Clear EPCMPRn */
481 + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
482 + iowrite32be(0, epu_base + offset);
485 + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
486 + iowrite32be(0, epu_base + offset);
488 + /* Clear EPIMCRn */
489 + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
490 + iowrite32be(0, epu_base + offset);
492 + /* Clear EPXTRIGCRn */
493 + iowrite32be(0, epu_base + EPXTRIGCR);
496 + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
497 + iowrite32be(0, epu_base + offset);
500 +++ b/drivers/soc/fsl/sleep_fsm.h
503 + * deep sleep FSM (finite-state machine) configuration
505 + * Copyright 2018 NXP
507 + * Redistribution and use in source and binary forms, with or without
508 + * modification, are permitted provided that the following conditions are met:
509 + * * Redistributions of source code must retain the above copyright
510 + * notice, this list of conditions and the following disclaimer.
511 + * * Redistributions in binary form must reproduce the above copyright
512 + * notice, this list of conditions and the following disclaimer in the
513 + * documentation and/or other materials provided with the distribution.
514 + * * Neither the name of the above-listed copyright holders nor the
515 + * names of any contributors may be used to endorse or promote products
516 + * derived from this software without specific prior written permission.
519 + * ALTERNATIVELY, this software may be distributed under the terms of the
520 + * GNU General Public License ("GPL") as published by the Free Software
521 + * Foundation, either version 2 of that License or (at your option) any
524 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
525 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
526 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
527 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
528 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
529 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
530 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
531 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
532 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
533 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
534 + * POSSIBILITY OF SUCH DAMAGE.
537 +#ifndef _FSL_SLEEP_FSM_H
538 +#define _FSL_SLEEP_FSM_H
540 +#define FSL_STRIDE_4B 4
541 +#define FSL_STRIDE_8B 8
544 +#define FSM_END_FLAG 0xFFFFFFFFUL
547 +#define RCPM_BLOCK_OFFSET 0x00022000
548 +#define EPU_BLOCK_OFFSET 0x00000000
549 +#define NPC_BLOCK_OFFSET 0x00001000
551 +/* EPGCR (Event Processor Global Control Register) */
554 +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
555 +#define EPEVTCR0 0x050
556 +#define EPEVTCR9 0x074
557 +#define EPEVTCR_STRIDE FSL_STRIDE_4B
559 +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
560 +#define EPXTRIGCR 0x090
562 +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
563 +#define EPIMCR0 0x100
564 +#define EPIMCR31 0x17C
565 +#define EPIMCR_STRIDE FSL_STRIDE_4B
567 +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
568 +#define EPSMCR0 0x200
569 +#define EPSMCR15 0x278
570 +#define EPSMCR_STRIDE FSL_STRIDE_8B
572 +/* EPECR0-15 (Event Processor Event Control Registers) */
573 +#define EPECR0 0x300
574 +#define EPECR15 0x33C
575 +#define EPECR_STRIDE FSL_STRIDE_4B
577 +/* EPACR0-15 (Event Processor Action Control Registers) */
578 +#define EPACR0 0x400
579 +#define EPACR15 0x43C
580 +#define EPACR_STRIDE FSL_STRIDE_4B
582 +/* EPCCRi0-15 (Event Processor Counter Control Registers) */
583 +#define EPCCR0 0x800
584 +#define EPCCR15 0x83C
585 +#define EPCCR31 0x87C
586 +#define EPCCR_STRIDE FSL_STRIDE_4B
588 +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
589 +#define EPCMPR0 0x900
590 +#define EPCMPR15 0x93C
591 +#define EPCMPR31 0x97C
592 +#define EPCMPR_STRIDE FSL_STRIDE_4B
594 +/* EPCTR0-31 (Event Processor Counter Register) */
595 +#define EPCTR0 0xA00
596 +#define EPCTR31 0xA7C
597 +#define EPCTR_STRIDE FSL_STRIDE_4B
599 +/* NPC triggered Memory-Mapped Access Registers */
603 +#define MMAR1LO 0x0D4
604 +#define MMAR1HI 0x0D8
607 +#define MMAR2LO 0x0E4
608 +#define MMAR2HI 0x0E8
611 +#define MMAR3LO 0x0F4
612 +#define MMAR3HI 0x0F8
615 +/* RCPM Core State Action Control Register 0 */
616 +#define CSTTACR0 0xB00
618 +/* RCPM Core Group 1 Configuration Register 0 */
619 +#define CG1CR0 0x31C
621 +struct fsm_reg_vals {
626 +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
627 +void fsl_epu_setup_default(void __iomem *epu_base);
628 +void fsl_npc_setup_default(void __iomem *npc_base);
629 +void fsl_epu_clean_default(void __iomem *epu_base);
631 +#endif /* _FSL_SLEEP_FSM_H */