1 From bba7af6efb0aad1d52ee5e7d80f9e2ab59d85e20 Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Wed, 17 Apr 2019 18:58:52 +0800
4 Subject: [PATCH] ptp: support layerscape
6 This is an integrated patch of ptp for layerscape
8 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
10 Signed-off-by: David S. Miller <davem@davemloft.net>
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
13 drivers/net/ethernet/freescale/Makefile | 1 -
14 drivers/net/ethernet/freescale/gianfar_ptp.c | 572 ------------------
15 drivers/ptp/Makefile | 1 +
16 drivers/ptp/ptp_chardev.c | 4 +-
17 drivers/ptp/ptp_qoriq.c | 589 +++++++++++++++++++
18 include/linux/fsl/ptp_qoriq.h | 169 ++++++
19 6 files changed, 761 insertions(+), 575 deletions(-)
20 delete mode 100644 drivers/net/ethernet/freescale/gianfar_ptp.c
21 create mode 100644 drivers/ptp/ptp_qoriq.c
22 create mode 100644 include/linux/fsl/ptp_qoriq.h
24 --- a/drivers/net/ethernet/freescale/Makefile
25 +++ b/drivers/net/ethernet/freescale/Makefile
26 @@ -14,7 +14,6 @@ obj-$(CONFIG_FS_ENET) += fs_enet/
27 obj-$(CONFIG_FSL_PQ_MDIO) += fsl_pq_mdio.o
28 obj-$(CONFIG_FSL_XGMAC_MDIO) += xgmac_mdio.o
29 obj-$(CONFIG_GIANFAR) += gianfar_driver.o
30 -obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
31 gianfar_driver-objs := gianfar.o \
33 obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
34 --- a/drivers/net/ethernet/freescale/gianfar_ptp.c
38 - * PTP 1588 clock using the eTSEC
40 - * Copyright (C) 2010 OMICRON electronics GmbH
42 - * This program is free software; you can redistribute it and/or modify
43 - * it under the terms of the GNU General Public License as published by
44 - * the Free Software Foundation; either version 2 of the License, or
45 - * (at your option) any later version.
47 - * This program is distributed in the hope that it will be useful,
48 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
49 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50 - * GNU General Public License for more details.
52 - * You should have received a copy of the GNU General Public License
53 - * along with this program; if not, write to the Free Software
54 - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
57 -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
59 -#include <linux/device.h>
60 -#include <linux/hrtimer.h>
61 -#include <linux/interrupt.h>
62 -#include <linux/kernel.h>
63 -#include <linux/module.h>
64 -#include <linux/of.h>
65 -#include <linux/of_platform.h>
66 -#include <linux/timex.h>
67 -#include <linux/io.h>
69 -#include <linux/ptp_clock_kernel.h>
74 - * gianfar ptp registers
75 - * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
77 -struct gianfar_ptp_registers {
78 - u32 tmr_ctrl; /* Timer control register */
79 - u32 tmr_tevent; /* Timestamp event register */
80 - u32 tmr_temask; /* Timer event mask register */
81 - u32 tmr_pevent; /* Timestamp event register */
82 - u32 tmr_pemask; /* Timer event mask register */
83 - u32 tmr_stat; /* Timestamp status register */
84 - u32 tmr_cnt_h; /* Timer counter high register */
85 - u32 tmr_cnt_l; /* Timer counter low register */
86 - u32 tmr_add; /* Timer drift compensation addend register */
87 - u32 tmr_acc; /* Timer accumulator register */
88 - u32 tmr_prsc; /* Timer prescale */
90 - u32 tmroff_h; /* Timer offset high */
91 - u32 tmroff_l; /* Timer offset low */
93 - u32 tmr_alarm1_h; /* Timer alarm 1 high register */
94 - u32 tmr_alarm1_l; /* Timer alarm 1 high register */
95 - u32 tmr_alarm2_h; /* Timer alarm 2 high register */
96 - u32 tmr_alarm2_l; /* Timer alarm 2 high register */
98 - u32 tmr_fiper1; /* Timer fixed period interval */
99 - u32 tmr_fiper2; /* Timer fixed period interval */
100 - u32 tmr_fiper3; /* Timer fixed period interval */
102 - u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
103 - u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
104 - u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
105 - u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
108 -/* Bit definitions for the TMR_CTRL register */
109 -#define ALM1P (1<<31) /* Alarm1 output polarity */
110 -#define ALM2P (1<<30) /* Alarm2 output polarity */
111 -#define FIPERST (1<<28) /* FIPER start indication */
112 -#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
113 -#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
114 -#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
115 -#define TCLK_PERIOD_MASK (0x3ff)
116 -#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
117 -#define FRD (1<<14) /* FIPER Realignment Disable */
118 -#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
119 -#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
120 -#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
121 -#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
122 -#define COPH (1<<7) /* Generated clock output phase. */
123 -#define CIPH (1<<6) /* External oscillator input clock phase */
124 -#define TMSR (1<<5) /* Timer soft reset. */
125 -#define BYP (1<<3) /* Bypass drift compensated clock */
126 -#define TE (1<<2) /* 1588 timer enable. */
127 -#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
128 -#define CKSEL_MASK (0x3)
130 -/* Bit definitions for the TMR_TEVENT register */
131 -#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
132 -#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
133 -#define ALM2 (1<<17) /* Current time = alarm time register 2 */
134 -#define ALM1 (1<<16) /* Current time = alarm time register 1 */
135 -#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
136 -#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
137 -#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
139 -/* Bit definitions for the TMR_TEMASK register */
140 -#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
141 -#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
142 -#define ALM2EN (1<<17) /* Timer ALM2 event enable */
143 -#define ALM1EN (1<<16) /* Timer ALM1 event enable */
144 -#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
145 -#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
147 -/* Bit definitions for the TMR_PEVENT register */
148 -#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
149 -#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
150 -#define RXP (1<<0) /* PTP frame has been received */
152 -/* Bit definitions for the TMR_PEMASK register */
153 -#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
154 -#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
155 -#define RXPEN (1<<0) /* Receive PTP packet event enable */
157 -/* Bit definitions for the TMR_STAT register */
158 -#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
159 -#define STAT_VEC_MASK (0x3f)
161 -/* Bit definitions for the TMR_PRSC register */
162 -#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
163 -#define PRSC_OCK_MASK (0xffff)
166 -#define DRIVER "gianfar_ptp"
167 -#define DEFAULT_CKSEL 1
169 -#define REG_SIZE sizeof(struct gianfar_ptp_registers)
172 - struct gianfar_ptp_registers __iomem *regs;
173 - spinlock_t lock; /* protects regs */
174 - struct ptp_clock *clock;
175 - struct ptp_clock_info caps;
176 - struct resource *rsrc;
178 - u64 alarm_interval; /* for periodic alarm */
180 - u32 tclk_period; /* nanoseconds */
189 - * Register access functions
192 -/* Caller must hold etsects->lock. */
193 -static u64 tmr_cnt_read(struct etsects *etsects)
198 - lo = gfar_read(&etsects->regs->tmr_cnt_l);
199 - hi = gfar_read(&etsects->regs->tmr_cnt_h);
200 - ns = ((u64) hi) << 32;
205 -/* Caller must hold etsects->lock. */
206 -static void tmr_cnt_write(struct etsects *etsects, u64 ns)
209 - u32 lo = ns & 0xffffffff;
211 - gfar_write(&etsects->regs->tmr_cnt_l, lo);
212 - gfar_write(&etsects->regs->tmr_cnt_h, hi);
215 -/* Caller must hold etsects->lock. */
216 -static void set_alarm(struct etsects *etsects)
221 - ns = tmr_cnt_read(etsects) + 1500000000ULL;
222 - ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
223 - ns -= etsects->tclk_period;
225 - lo = ns & 0xffffffff;
226 - gfar_write(&etsects->regs->tmr_alarm1_l, lo);
227 - gfar_write(&etsects->regs->tmr_alarm1_h, hi);
230 -/* Caller must hold etsects->lock. */
231 -static void set_fipers(struct etsects *etsects)
233 - set_alarm(etsects);
234 - gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
235 - gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
239 - * Interrupt service routine
242 -static irqreturn_t isr(int irq, void *priv)
244 - struct etsects *etsects = priv;
245 - struct ptp_clock_event event;
247 - u32 ack = 0, lo, hi, mask, val;
249 - val = gfar_read(&etsects->regs->tmr_tevent);
253 - hi = gfar_read(&etsects->regs->tmr_etts1_h);
254 - lo = gfar_read(&etsects->regs->tmr_etts1_l);
255 - event.type = PTP_CLOCK_EXTTS;
257 - event.timestamp = ((u64) hi) << 32;
258 - event.timestamp |= lo;
259 - ptp_clock_event(etsects->clock, &event);
264 - hi = gfar_read(&etsects->regs->tmr_etts2_h);
265 - lo = gfar_read(&etsects->regs->tmr_etts2_l);
266 - event.type = PTP_CLOCK_EXTTS;
268 - event.timestamp = ((u64) hi) << 32;
269 - event.timestamp |= lo;
270 - ptp_clock_event(etsects->clock, &event);
275 - if (etsects->alarm_value) {
276 - event.type = PTP_CLOCK_ALARM;
278 - event.timestamp = etsects->alarm_value;
279 - ptp_clock_event(etsects->clock, &event);
281 - if (etsects->alarm_interval) {
282 - ns = etsects->alarm_value + etsects->alarm_interval;
284 - lo = ns & 0xffffffff;
285 - spin_lock(&etsects->lock);
286 - gfar_write(&etsects->regs->tmr_alarm2_l, lo);
287 - gfar_write(&etsects->regs->tmr_alarm2_h, hi);
288 - spin_unlock(&etsects->lock);
289 - etsects->alarm_value = ns;
291 - gfar_write(&etsects->regs->tmr_tevent, ALM2);
292 - spin_lock(&etsects->lock);
293 - mask = gfar_read(&etsects->regs->tmr_temask);
295 - gfar_write(&etsects->regs->tmr_temask, mask);
296 - spin_unlock(&etsects->lock);
297 - etsects->alarm_value = 0;
298 - etsects->alarm_interval = 0;
304 - event.type = PTP_CLOCK_PPS;
305 - ptp_clock_event(etsects->clock, &event);
309 - gfar_write(&etsects->regs->tmr_tevent, ack);
310 - return IRQ_HANDLED;
316 - * PTP clock operations
319 -static int ptp_gianfar_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
324 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
326 - if (scaled_ppm < 0) {
328 - scaled_ppm = -scaled_ppm;
330 - tmr_add = etsects->tmr_add;
333 - /* calculate diff as adj*(scaled_ppm/65536)/1000000
334 - * and round() to the nearest integer
337 - diff = div_u64(adj, 8000000);
338 - diff = (diff >> 13) + ((diff >> 12) & 1);
340 - tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
342 - gfar_write(&etsects->regs->tmr_add, tmr_add);
347 -static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
350 - unsigned long flags;
351 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
353 - spin_lock_irqsave(&etsects->lock, flags);
355 - now = tmr_cnt_read(etsects);
357 - tmr_cnt_write(etsects, now);
358 - set_fipers(etsects);
360 - spin_unlock_irqrestore(&etsects->lock, flags);
365 -static int ptp_gianfar_gettime(struct ptp_clock_info *ptp,
366 - struct timespec64 *ts)
369 - unsigned long flags;
370 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
372 - spin_lock_irqsave(&etsects->lock, flags);
374 - ns = tmr_cnt_read(etsects);
376 - spin_unlock_irqrestore(&etsects->lock, flags);
378 - *ts = ns_to_timespec64(ns);
383 -static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
384 - const struct timespec64 *ts)
387 - unsigned long flags;
388 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
390 - ns = timespec64_to_ns(ts);
392 - spin_lock_irqsave(&etsects->lock, flags);
394 - tmr_cnt_write(etsects, ns);
395 - set_fipers(etsects);
397 - spin_unlock_irqrestore(&etsects->lock, flags);
402 -static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
403 - struct ptp_clock_request *rq, int on)
405 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
406 - unsigned long flags;
409 - switch (rq->type) {
410 - case PTP_CLK_REQ_EXTTS:
411 - switch (rq->extts.index) {
421 - spin_lock_irqsave(&etsects->lock, flags);
422 - mask = gfar_read(&etsects->regs->tmr_temask);
427 - gfar_write(&etsects->regs->tmr_temask, mask);
428 - spin_unlock_irqrestore(&etsects->lock, flags);
431 - case PTP_CLK_REQ_PPS:
432 - spin_lock_irqsave(&etsects->lock, flags);
433 - mask = gfar_read(&etsects->regs->tmr_temask);
438 - gfar_write(&etsects->regs->tmr_temask, mask);
439 - spin_unlock_irqrestore(&etsects->lock, flags);
446 - return -EOPNOTSUPP;
449 -static const struct ptp_clock_info ptp_gianfar_caps = {
450 - .owner = THIS_MODULE,
451 - .name = "gianfar clock",
454 - .n_ext_ts = N_EXT_TS,
458 - .adjfine = ptp_gianfar_adjfine,
459 - .adjtime = ptp_gianfar_adjtime,
460 - .gettime64 = ptp_gianfar_gettime,
461 - .settime64 = ptp_gianfar_settime,
462 - .enable = ptp_gianfar_enable,
465 -static int gianfar_ptp_probe(struct platform_device *dev)
467 - struct device_node *node = dev->dev.of_node;
468 - struct etsects *etsects;
469 - struct timespec64 now;
472 - unsigned long flags;
474 - etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
480 - etsects->caps = ptp_gianfar_caps;
482 - if (of_property_read_u32(node, "fsl,cksel", &etsects->cksel))
483 - etsects->cksel = DEFAULT_CKSEL;
485 - if (of_property_read_u32(node,
486 - "fsl,tclk-period", &etsects->tclk_period) ||
487 - of_property_read_u32(node,
488 - "fsl,tmr-prsc", &etsects->tmr_prsc) ||
489 - of_property_read_u32(node,
490 - "fsl,tmr-add", &etsects->tmr_add) ||
491 - of_property_read_u32(node,
492 - "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
493 - of_property_read_u32(node,
494 - "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
495 - of_property_read_u32(node,
496 - "fsl,max-adj", &etsects->caps.max_adj)) {
497 - pr_err("device tree node missing required elements\n");
501 - etsects->irq = platform_get_irq(dev, 0);
503 - if (etsects->irq < 0) {
504 - pr_err("irq not in device tree\n");
507 - if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
508 - pr_err("request_irq failed\n");
512 - etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
513 - if (!etsects->rsrc) {
514 - pr_err("no resource\n");
517 - if (request_resource(&iomem_resource, etsects->rsrc)) {
518 - pr_err("resource busy\n");
522 - spin_lock_init(&etsects->lock);
524 - etsects->regs = ioremap(etsects->rsrc->start,
525 - resource_size(etsects->rsrc));
526 - if (!etsects->regs) {
527 - pr_err("ioremap ptp registers failed\n");
530 - getnstimeofday64(&now);
531 - ptp_gianfar_settime(&etsects->caps, &now);
534 - (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
535 - (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
537 - spin_lock_irqsave(&etsects->lock, flags);
539 - gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
540 - gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
541 - gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
542 - gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
543 - gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
544 - set_alarm(etsects);
545 - gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FIPERST|RTPE|TE|FRD);
547 - spin_unlock_irqrestore(&etsects->lock, flags);
549 - etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
550 - if (IS_ERR(etsects->clock)) {
551 - err = PTR_ERR(etsects->clock);
554 - gfar_phc_index = ptp_clock_index(etsects->clock);
556 - platform_set_drvdata(dev, etsects);
561 - iounmap(etsects->regs);
563 - release_resource(etsects->rsrc);
565 - free_irq(etsects->irq, etsects);
572 -static int gianfar_ptp_remove(struct platform_device *dev)
574 - struct etsects *etsects = platform_get_drvdata(dev);
576 - gfar_write(&etsects->regs->tmr_temask, 0);
577 - gfar_write(&etsects->regs->tmr_ctrl, 0);
579 - gfar_phc_index = -1;
580 - ptp_clock_unregister(etsects->clock);
581 - iounmap(etsects->regs);
582 - release_resource(etsects->rsrc);
583 - free_irq(etsects->irq, etsects);
589 -static const struct of_device_id match_table[] = {
590 - { .compatible = "fsl,etsec-ptp" },
593 -MODULE_DEVICE_TABLE(of, match_table);
595 -static struct platform_driver gianfar_ptp_driver = {
597 - .name = "gianfar_ptp",
598 - .of_match_table = match_table,
600 - .probe = gianfar_ptp_probe,
601 - .remove = gianfar_ptp_remove,
604 -module_platform_driver(gianfar_ptp_driver);
606 -MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
607 -MODULE_DESCRIPTION("PTP clock using the eTSEC");
608 -MODULE_LICENSE("GPL");
609 --- a/drivers/ptp/Makefile
610 +++ b/drivers/ptp/Makefile
611 @@ -9,3 +9,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_DTE) += ptp_
612 obj-$(CONFIG_PTP_1588_CLOCK_IXP46X) += ptp_ixp46x.o
613 obj-$(CONFIG_PTP_1588_CLOCK_PCH) += ptp_pch.o
614 obj-$(CONFIG_PTP_1588_CLOCK_KVM) += ptp_kvm.o
615 +obj-$(CONFIG_PTP_1588_CLOCK_QORIQ) += ptp_qoriq.o
616 --- a/drivers/ptp/ptp_chardev.c
617 +++ b/drivers/ptp/ptp_chardev.c
618 @@ -224,7 +224,7 @@ long ptp_ioctl(struct posix_clock *pc, u
620 pct = &sysoff->ts[0];
621 for (i = 0; i < sysoff->n_samples; i++) {
622 - getnstimeofday64(&ts);
623 + ktime_get_real_ts64(&ts);
624 pct->sec = ts.tv_sec;
625 pct->nsec = ts.tv_nsec;
627 @@ -235,7 +235,7 @@ long ptp_ioctl(struct posix_clock *pc, u
628 pct->nsec = ts.tv_nsec;
631 - getnstimeofday64(&ts);
632 + ktime_get_real_ts64(&ts);
633 pct->sec = ts.tv_sec;
634 pct->nsec = ts.tv_nsec;
635 if (copy_to_user((void __user *)arg, sysoff, sizeof(*sysoff)))
637 +++ b/drivers/ptp/ptp_qoriq.c
640 + * PTP 1588 clock for Freescale QorIQ 1588 timer
642 + * Copyright (C) 2010 OMICRON electronics GmbH
644 + * This program is free software; you can redistribute it and/or modify
645 + * it under the terms of the GNU General Public License as published by
646 + * the Free Software Foundation; either version 2 of the License, or
647 + * (at your option) any later version.
649 + * This program is distributed in the hope that it will be useful,
650 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
651 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
652 + * GNU General Public License for more details.
654 + * You should have received a copy of the GNU General Public License
655 + * along with this program; if not, write to the Free Software
656 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
659 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
661 +#include <linux/device.h>
662 +#include <linux/hrtimer.h>
663 +#include <linux/interrupt.h>
664 +#include <linux/kernel.h>
665 +#include <linux/module.h>
666 +#include <linux/of.h>
667 +#include <linux/of_platform.h>
668 +#include <linux/timex.h>
669 +#include <linux/slab.h>
670 +#include <linux/clk.h>
672 +#include <linux/fsl/ptp_qoriq.h>
675 + * Register access functions
678 +/* Caller must hold qoriq_ptp->lock. */
679 +static u64 tmr_cnt_read(struct qoriq_ptp *qoriq_ptp)
681 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
685 + lo = qoriq_read(®s->ctrl_regs->tmr_cnt_l);
686 + hi = qoriq_read(®s->ctrl_regs->tmr_cnt_h);
687 + ns = ((u64) hi) << 32;
692 +/* Caller must hold qoriq_ptp->lock. */
693 +static void tmr_cnt_write(struct qoriq_ptp *qoriq_ptp, u64 ns)
695 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
697 + u32 lo = ns & 0xffffffff;
699 + qoriq_write(®s->ctrl_regs->tmr_cnt_l, lo);
700 + qoriq_write(®s->ctrl_regs->tmr_cnt_h, hi);
703 +/* Caller must hold qoriq_ptp->lock. */
704 +static void set_alarm(struct qoriq_ptp *qoriq_ptp)
706 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
710 + ns = tmr_cnt_read(qoriq_ptp) + 1500000000ULL;
711 + ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
712 + ns -= qoriq_ptp->tclk_period;
714 + lo = ns & 0xffffffff;
715 + qoriq_write(®s->alarm_regs->tmr_alarm1_l, lo);
716 + qoriq_write(®s->alarm_regs->tmr_alarm1_h, hi);
719 +/* Caller must hold qoriq_ptp->lock. */
720 +static void set_fipers(struct qoriq_ptp *qoriq_ptp)
722 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
724 + set_alarm(qoriq_ptp);
725 + qoriq_write(®s->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
726 + qoriq_write(®s->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
730 + * Interrupt service routine
733 +static irqreturn_t isr(int irq, void *priv)
735 + struct qoriq_ptp *qoriq_ptp = priv;
736 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
737 + struct ptp_clock_event event;
739 + u32 ack = 0, lo, hi, mask, val;
741 + val = qoriq_read(®s->ctrl_regs->tmr_tevent);
745 + hi = qoriq_read(®s->etts_regs->tmr_etts1_h);
746 + lo = qoriq_read(®s->etts_regs->tmr_etts1_l);
747 + event.type = PTP_CLOCK_EXTTS;
749 + event.timestamp = ((u64) hi) << 32;
750 + event.timestamp |= lo;
751 + ptp_clock_event(qoriq_ptp->clock, &event);
756 + hi = qoriq_read(®s->etts_regs->tmr_etts2_h);
757 + lo = qoriq_read(®s->etts_regs->tmr_etts2_l);
758 + event.type = PTP_CLOCK_EXTTS;
760 + event.timestamp = ((u64) hi) << 32;
761 + event.timestamp |= lo;
762 + ptp_clock_event(qoriq_ptp->clock, &event);
767 + if (qoriq_ptp->alarm_value) {
768 + event.type = PTP_CLOCK_ALARM;
770 + event.timestamp = qoriq_ptp->alarm_value;
771 + ptp_clock_event(qoriq_ptp->clock, &event);
773 + if (qoriq_ptp->alarm_interval) {
774 + ns = qoriq_ptp->alarm_value + qoriq_ptp->alarm_interval;
776 + lo = ns & 0xffffffff;
777 + spin_lock(&qoriq_ptp->lock);
778 + qoriq_write(®s->alarm_regs->tmr_alarm2_l, lo);
779 + qoriq_write(®s->alarm_regs->tmr_alarm2_h, hi);
780 + spin_unlock(&qoriq_ptp->lock);
781 + qoriq_ptp->alarm_value = ns;
783 + qoriq_write(®s->ctrl_regs->tmr_tevent, ALM2);
784 + spin_lock(&qoriq_ptp->lock);
785 + mask = qoriq_read(®s->ctrl_regs->tmr_temask);
787 + qoriq_write(®s->ctrl_regs->tmr_temask, mask);
788 + spin_unlock(&qoriq_ptp->lock);
789 + qoriq_ptp->alarm_value = 0;
790 + qoriq_ptp->alarm_interval = 0;
796 + event.type = PTP_CLOCK_PPS;
797 + ptp_clock_event(qoriq_ptp->clock, &event);
801 + qoriq_write(®s->ctrl_regs->tmr_tevent, ack);
802 + return IRQ_HANDLED;
808 + * PTP clock operations
811 +static int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
816 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
817 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
819 + if (scaled_ppm < 0) {
821 + scaled_ppm = -scaled_ppm;
823 + tmr_add = qoriq_ptp->tmr_add;
826 + /* calculate diff as adj*(scaled_ppm/65536)/1000000
827 + * and round() to the nearest integer
830 + diff = div_u64(adj, 8000000);
831 + diff = (diff >> 13) + ((diff >> 12) & 1);
833 + tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
835 + qoriq_write(®s->ctrl_regs->tmr_add, tmr_add);
840 +static int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta)
843 + unsigned long flags;
844 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
846 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
848 + now = tmr_cnt_read(qoriq_ptp);
850 + tmr_cnt_write(qoriq_ptp, now);
851 + set_fipers(qoriq_ptp);
853 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
858 +static int ptp_qoriq_gettime(struct ptp_clock_info *ptp,
859 + struct timespec64 *ts)
862 + unsigned long flags;
863 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
865 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
867 + ns = tmr_cnt_read(qoriq_ptp);
869 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
871 + *ts = ns_to_timespec64(ns);
876 +static int ptp_qoriq_settime(struct ptp_clock_info *ptp,
877 + const struct timespec64 *ts)
880 + unsigned long flags;
881 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
883 + ns = timespec64_to_ns(ts);
885 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
887 + tmr_cnt_write(qoriq_ptp, ns);
888 + set_fipers(qoriq_ptp);
890 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
895 +static int ptp_qoriq_enable(struct ptp_clock_info *ptp,
896 + struct ptp_clock_request *rq, int on)
898 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
899 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
900 + unsigned long flags;
903 + switch (rq->type) {
904 + case PTP_CLK_REQ_EXTTS:
905 + switch (rq->extts.index) {
915 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
916 + mask = qoriq_read(®s->ctrl_regs->tmr_temask);
921 + qoriq_write(®s->ctrl_regs->tmr_temask, mask);
922 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
925 + case PTP_CLK_REQ_PPS:
926 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
927 + mask = qoriq_read(®s->ctrl_regs->tmr_temask);
932 + qoriq_write(®s->ctrl_regs->tmr_temask, mask);
933 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
940 + return -EOPNOTSUPP;
943 +static const struct ptp_clock_info ptp_qoriq_caps = {
944 + .owner = THIS_MODULE,
945 + .name = "qoriq ptp clock",
948 + .n_ext_ts = N_EXT_TS,
952 + .adjfine = ptp_qoriq_adjfine,
953 + .adjtime = ptp_qoriq_adjtime,
954 + .gettime64 = ptp_qoriq_gettime,
955 + .settime64 = ptp_qoriq_settime,
956 + .enable = ptp_qoriq_enable,
960 + * qoriq_ptp_nominal_freq - calculate nominal frequency according to
961 + * reference clock frequency
963 + * @clk_src: reference clock frequency
965 + * The nominal frequency is the desired clock frequency.
966 + * It should be less than the reference clock frequency.
967 + * It should be a factor of 1000MHz.
969 + * Return the nominal frequency
971 +static u32 qoriq_ptp_nominal_freq(u32 clk_src)
975 + clk_src /= 1000000;
976 + remainder = clk_src % 100;
978 + clk_src -= remainder;
985 + } while (1000 % clk_src);
987 + return clk_src * 1000000;
991 + * qoriq_ptp_auto_config - calculate a set of default configurations
993 + * @qoriq_ptp: pointer to qoriq_ptp
994 + * @node: pointer to device_node
996 + * If below dts properties are not provided, this function will be
997 + * called to calculate a set of default configurations for them.
998 + * "fsl,tclk-period"
1001 + * "fsl,tmr-fiper1"
1002 + * "fsl,tmr-fiper2"
1005 + * Return 0 if success
1007 +static int qoriq_ptp_auto_config(struct qoriq_ptp *qoriq_ptp,
1008 + struct device_node *node)
1014 + u32 remainder = 0;
1017 + qoriq_ptp->cksel = DEFAULT_CKSEL;
1019 + clk = of_clk_get(node, 0);
1020 + if (!IS_ERR(clk)) {
1021 + clk_src = clk_get_rate(clk);
1025 + if (clk_src <= 100000000UL) {
1026 + pr_err("error reference clock value, or lower than 100MHz\n");
1030 + nominal_freq = qoriq_ptp_nominal_freq(clk_src);
1031 + if (!nominal_freq)
1034 + qoriq_ptp->tclk_period = 1000000000UL / nominal_freq;
1035 + qoriq_ptp->tmr_prsc = DEFAULT_TMR_PRSC;
1037 + /* Calculate initial frequency compensation value for TMR_ADD register.
1038 + * freq_comp = ceil(2^32 / freq_ratio)
1039 + * freq_ratio = reference_clock_freq / nominal_freq
1041 + freq_comp = ((u64)1 << 32) * nominal_freq;
1042 + freq_comp = div_u64_rem(freq_comp, clk_src, &remainder);
1046 + qoriq_ptp->tmr_add = freq_comp;
1047 + qoriq_ptp->tmr_fiper1 = DEFAULT_FIPER1_PERIOD - qoriq_ptp->tclk_period;
1048 + qoriq_ptp->tmr_fiper2 = DEFAULT_FIPER2_PERIOD - qoriq_ptp->tclk_period;
1050 + /* max_adj = 1000000000 * (freq_ratio - 1.0) - 1
1051 + * freq_ratio = reference_clock_freq / nominal_freq
1053 + max_adj = 1000000000ULL * (clk_src - nominal_freq);
1054 + max_adj = div_u64(max_adj, nominal_freq) - 1;
1055 + qoriq_ptp->caps.max_adj = max_adj;
1060 +static int qoriq_ptp_probe(struct platform_device *dev)
1062 + struct device_node *node = dev->dev.of_node;
1063 + struct qoriq_ptp *qoriq_ptp;
1064 + struct qoriq_ptp_registers *regs;
1065 + struct timespec64 now;
1066 + int err = -ENOMEM;
1068 + unsigned long flags;
1069 + void __iomem *base;
1071 + qoriq_ptp = kzalloc(sizeof(*qoriq_ptp), GFP_KERNEL);
1077 + qoriq_ptp->caps = ptp_qoriq_caps;
1079 + if (of_property_read_u32(node, "fsl,cksel", &qoriq_ptp->cksel))
1080 + qoriq_ptp->cksel = DEFAULT_CKSEL;
1082 + if (of_property_read_u32(node,
1083 + "fsl,tclk-period", &qoriq_ptp->tclk_period) ||
1084 + of_property_read_u32(node,
1085 + "fsl,tmr-prsc", &qoriq_ptp->tmr_prsc) ||
1086 + of_property_read_u32(node,
1087 + "fsl,tmr-add", &qoriq_ptp->tmr_add) ||
1088 + of_property_read_u32(node,
1089 + "fsl,tmr-fiper1", &qoriq_ptp->tmr_fiper1) ||
1090 + of_property_read_u32(node,
1091 + "fsl,tmr-fiper2", &qoriq_ptp->tmr_fiper2) ||
1092 + of_property_read_u32(node,
1093 + "fsl,max-adj", &qoriq_ptp->caps.max_adj)) {
1094 + pr_warn("device tree node missing required elements, try automatic configuration\n");
1096 + if (qoriq_ptp_auto_config(qoriq_ptp, node))
1102 + qoriq_ptp->irq = platform_get_irq(dev, 0);
1104 + if (qoriq_ptp->irq < 0) {
1105 + pr_err("irq not in device tree\n");
1108 + if (request_irq(qoriq_ptp->irq, isr, IRQF_SHARED, DRIVER, qoriq_ptp)) {
1109 + pr_err("request_irq failed\n");
1113 + qoriq_ptp->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
1114 + if (!qoriq_ptp->rsrc) {
1115 + pr_err("no resource\n");
1118 + if (request_resource(&iomem_resource, qoriq_ptp->rsrc)) {
1119 + pr_err("resource busy\n");
1123 + spin_lock_init(&qoriq_ptp->lock);
1125 + base = ioremap(qoriq_ptp->rsrc->start,
1126 + resource_size(qoriq_ptp->rsrc));
1128 + pr_err("ioremap ptp registers failed\n");
1132 + qoriq_ptp->base = base;
1134 + if (of_device_is_compatible(node, "fsl,fman-ptp-timer")) {
1135 + qoriq_ptp->regs.ctrl_regs = base + FMAN_CTRL_REGS_OFFSET;
1136 + qoriq_ptp->regs.alarm_regs = base + FMAN_ALARM_REGS_OFFSET;
1137 + qoriq_ptp->regs.fiper_regs = base + FMAN_FIPER_REGS_OFFSET;
1138 + qoriq_ptp->regs.etts_regs = base + FMAN_ETTS_REGS_OFFSET;
1140 + qoriq_ptp->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
1141 + qoriq_ptp->regs.alarm_regs = base + ALARM_REGS_OFFSET;
1142 + qoriq_ptp->regs.fiper_regs = base + FIPER_REGS_OFFSET;
1143 + qoriq_ptp->regs.etts_regs = base + ETTS_REGS_OFFSET;
1146 + ktime_get_real_ts64(&now);
1147 + ptp_qoriq_settime(&qoriq_ptp->caps, &now);
1150 + (qoriq_ptp->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
1151 + (qoriq_ptp->cksel & CKSEL_MASK) << CKSEL_SHIFT;
1153 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
1155 + regs = &qoriq_ptp->regs;
1156 + qoriq_write(®s->ctrl_regs->tmr_ctrl, tmr_ctrl);
1157 + qoriq_write(®s->ctrl_regs->tmr_add, qoriq_ptp->tmr_add);
1158 + qoriq_write(®s->ctrl_regs->tmr_prsc, qoriq_ptp->tmr_prsc);
1159 + qoriq_write(®s->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
1160 + qoriq_write(®s->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
1161 + set_alarm(qoriq_ptp);
1162 + qoriq_write(®s->ctrl_regs->tmr_ctrl, tmr_ctrl|FIPERST|RTPE|TE|FRD);
1164 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
1166 + qoriq_ptp->clock = ptp_clock_register(&qoriq_ptp->caps, &dev->dev);
1167 + if (IS_ERR(qoriq_ptp->clock)) {
1168 + err = PTR_ERR(qoriq_ptp->clock);
1171 + qoriq_ptp->phc_index = ptp_clock_index(qoriq_ptp->clock);
1173 + platform_set_drvdata(dev, qoriq_ptp);
1178 + iounmap(qoriq_ptp->base);
1180 + release_resource(qoriq_ptp->rsrc);
1182 + free_irq(qoriq_ptp->irq, qoriq_ptp);
1190 +static int qoriq_ptp_remove(struct platform_device *dev)
1192 + struct qoriq_ptp *qoriq_ptp = platform_get_drvdata(dev);
1193 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
1195 + qoriq_write(®s->ctrl_regs->tmr_temask, 0);
1196 + qoriq_write(®s->ctrl_regs->tmr_ctrl, 0);
1198 + ptp_clock_unregister(qoriq_ptp->clock);
1199 + iounmap(qoriq_ptp->base);
1200 + release_resource(qoriq_ptp->rsrc);
1201 + free_irq(qoriq_ptp->irq, qoriq_ptp);
1207 +static const struct of_device_id match_table[] = {
1208 + { .compatible = "fsl,etsec-ptp" },
1209 + { .compatible = "fsl,fman-ptp-timer" },
1212 +MODULE_DEVICE_TABLE(of, match_table);
1214 +static struct platform_driver qoriq_ptp_driver = {
1216 + .name = "ptp_qoriq",
1217 + .of_match_table = match_table,
1219 + .probe = qoriq_ptp_probe,
1220 + .remove = qoriq_ptp_remove,
1223 +module_platform_driver(qoriq_ptp_driver);
1225 +MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1226 +MODULE_DESCRIPTION("PTP clock for Freescale QorIQ 1588 timer");
1227 +MODULE_LICENSE("GPL");
1229 +++ b/include/linux/fsl/ptp_qoriq.h
1231 +// SPDX-License-Identifier: GPL-2.0
1233 + * Copyright (C) 2010 OMICRON electronics GmbH
1234 + * Copyright 2018 NXP
1236 +#ifndef __PTP_QORIQ_H__
1237 +#define __PTP_QORIQ_H__
1239 +#include <linux/io.h>
1240 +#include <linux/ptp_clock_kernel.h>
1243 + * qoriq ptp registers
1246 + u32 tmr_ctrl; /* Timer control register */
1247 + u32 tmr_tevent; /* Timestamp event register */
1248 + u32 tmr_temask; /* Timer event mask register */
1249 + u32 tmr_pevent; /* Timestamp event register */
1250 + u32 tmr_pemask; /* Timer event mask register */
1251 + u32 tmr_stat; /* Timestamp status register */
1252 + u32 tmr_cnt_h; /* Timer counter high register */
1253 + u32 tmr_cnt_l; /* Timer counter low register */
1254 + u32 tmr_add; /* Timer drift compensation addend register */
1255 + u32 tmr_acc; /* Timer accumulator register */
1256 + u32 tmr_prsc; /* Timer prescale */
1258 + u32 tmroff_h; /* Timer offset high */
1259 + u32 tmroff_l; /* Timer offset low */
1262 +struct alarm_regs {
1263 + u32 tmr_alarm1_h; /* Timer alarm 1 high register */
1264 + u32 tmr_alarm1_l; /* Timer alarm 1 high register */
1265 + u32 tmr_alarm2_h; /* Timer alarm 2 high register */
1266 + u32 tmr_alarm2_l; /* Timer alarm 2 high register */
1269 +struct fiper_regs {
1270 + u32 tmr_fiper1; /* Timer fixed period interval */
1271 + u32 tmr_fiper2; /* Timer fixed period interval */
1272 + u32 tmr_fiper3; /* Timer fixed period interval */
1276 + u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
1277 + u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
1278 + u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
1279 + u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
1282 +struct qoriq_ptp_registers {
1283 + struct ctrl_regs __iomem *ctrl_regs;
1284 + struct alarm_regs __iomem *alarm_regs;
1285 + struct fiper_regs __iomem *fiper_regs;
1286 + struct etts_regs __iomem *etts_regs;
1289 +/* Offset definitions for the four register groups */
1290 +#define CTRL_REGS_OFFSET 0x0
1291 +#define ALARM_REGS_OFFSET 0x40
1292 +#define FIPER_REGS_OFFSET 0x80
1293 +#define ETTS_REGS_OFFSET 0xa0
1295 +#define FMAN_CTRL_REGS_OFFSET 0x80
1296 +#define FMAN_ALARM_REGS_OFFSET 0xb8
1297 +#define FMAN_FIPER_REGS_OFFSET 0xd0
1298 +#define FMAN_ETTS_REGS_OFFSET 0xe0
1301 +/* Bit definitions for the TMR_CTRL register */
1302 +#define ALM1P (1<<31) /* Alarm1 output polarity */
1303 +#define ALM2P (1<<30) /* Alarm2 output polarity */
1304 +#define FIPERST (1<<28) /* FIPER start indication */
1305 +#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
1306 +#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
1307 +#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
1308 +#define TCLK_PERIOD_MASK (0x3ff)
1309 +#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
1310 +#define FRD (1<<14) /* FIPER Realignment Disable */
1311 +#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
1312 +#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
1313 +#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
1314 +#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
1315 +#define COPH (1<<7) /* Generated clock output phase. */
1316 +#define CIPH (1<<6) /* External oscillator input clock phase */
1317 +#define TMSR (1<<5) /* Timer soft reset. */
1318 +#define BYP (1<<3) /* Bypass drift compensated clock */
1319 +#define TE (1<<2) /* 1588 timer enable. */
1320 +#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
1321 +#define CKSEL_MASK (0x3)
1323 +/* Bit definitions for the TMR_TEVENT register */
1324 +#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
1325 +#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
1326 +#define ALM2 (1<<17) /* Current time = alarm time register 2 */
1327 +#define ALM1 (1<<16) /* Current time = alarm time register 1 */
1328 +#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
1329 +#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
1330 +#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
1332 +/* Bit definitions for the TMR_TEMASK register */
1333 +#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
1334 +#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
1335 +#define ALM2EN (1<<17) /* Timer ALM2 event enable */
1336 +#define ALM1EN (1<<16) /* Timer ALM1 event enable */
1337 +#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
1338 +#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
1340 +/* Bit definitions for the TMR_PEVENT register */
1341 +#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
1342 +#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
1343 +#define RXP (1<<0) /* PTP frame has been received */
1345 +/* Bit definitions for the TMR_PEMASK register */
1346 +#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
1347 +#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
1348 +#define RXPEN (1<<0) /* Receive PTP packet event enable */
1350 +/* Bit definitions for the TMR_STAT register */
1351 +#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
1352 +#define STAT_VEC_MASK (0x3f)
1354 +/* Bit definitions for the TMR_PRSC register */
1355 +#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
1356 +#define PRSC_OCK_MASK (0xffff)
1359 +#define DRIVER "ptp_qoriq"
1362 +#define DEFAULT_CKSEL 1
1363 +#define DEFAULT_TMR_PRSC 2
1364 +#define DEFAULT_FIPER1_PERIOD 1000000000
1365 +#define DEFAULT_FIPER2_PERIOD 100000
1368 + void __iomem *base;
1369 + struct qoriq_ptp_registers regs;
1370 + spinlock_t lock; /* protects regs */
1371 + struct ptp_clock *clock;
1372 + struct ptp_clock_info caps;
1373 + struct resource *rsrc;
1376 + u64 alarm_interval; /* for periodic alarm */
1378 + u32 tclk_period; /* nanoseconds */
1386 +static inline u32 qoriq_read(unsigned __iomem *addr)
1390 + val = ioread32be(addr);
1394 +static inline void qoriq_write(unsigned __iomem *addr, u32 val)
1396 + iowrite32be(val, addr);