1 From a0a4f406c7e90b2be66e88ea8b21699940c0823f Mon Sep 17 00:00:00 2001
2 From: Joao Pinto <Joao.Pinto@synopsys.com>
3 Date: Thu, 10 Mar 2016 14:44:44 -0600
4 Subject: [PATCH 57/70] PCI: designware: Add default link up check if
5 sub-driver doesn't override
7 Add a default DesignWare "link_up" test for use when a sub-driver doesn't
8 supply its own pcie_host_ops.link_up() method.
10 [bhelgaas: changelog, split into its own patch]
11 Signed-off-by: Joao Pinto <jpinto@synopsys.com>
12 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
13 Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
15 drivers/pci/host/pcie-designware.c | 10 +++++++++-
16 1 file changed, 9 insertions(+), 1 deletion(-)
18 --- a/drivers/pci/host/pcie-designware.c
19 +++ b/drivers/pci/host/pcie-designware.c
21 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
22 #define PCIE_ATU_UPPER_TARGET 0x91C
24 +/* PCIe Port Logic registers */
25 +#define PLR_OFFSET 0x700
26 +#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
27 +#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
29 static struct pci_ops dw_pcie_ops;
31 int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
32 @@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_po
34 int dw_pcie_link_up(struct pcie_port *pp)
39 return pp->ops->link_up(pp);
42 + val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
43 + return val & PCIE_PHY_DEBUG_R1_LINK_UP;
46 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,