1 From b57dcab78fdc76a6c56c2df71518fb022429e244 Mon Sep 17 00:00:00 2001
2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
3 Date: Wed, 6 Apr 2016 19:02:07 +0800
4 Subject: [PATCH 02/13] ARM: dts: ls1021a: add SCFG MSI dts node
6 Cherry-pick upstream patch.
8 Add SCFG MSI dts node and add msi-parent property to PCIe dts node
9 that points to the corresponding MSI node.
11 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
12 Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
13 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
15 arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++++++++++
16 1 file changed, 16 insertions(+)
18 --- a/arch/arm/boot/dts/ls1021a.dtsi
19 +++ b/arch/arm/boot/dts/ls1021a.dtsi
24 + msi1: msi-controller@1570e00 {
25 + compatible = "fsl,1s1021a-msi";
26 + reg = <0x0 0x1570e00 0x0 0x8>;
28 + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
31 + msi2: msi-controller@1570e08 {
32 + compatible = "fsl,1s1021a-msi";
33 + reg = <0x0 0x1570e08 0x0 0x8>;
35 + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
39 compatible = "fsl,ifc", "simple-bus";
40 reg = <0x0 0x1530000 0x0 0x10000>;
42 bus-range = <0x0 0xff>;
43 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
44 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
45 + msi-parent = <&msi1>;
46 #interrupt-cells = <1>;
47 interrupt-map-mask = <0 0 0 7>;
48 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
50 bus-range = <0x0 0xff>;
51 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
52 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
53 + msi-parent = <&msi2>;
54 #interrupt-cells = <1>;
55 interrupt-map-mask = <0 0 0 7>;
56 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,