1 From 066320dd0643e66bc5afe0d0984e77b2e938a6f4 Mon Sep 17 00:00:00 2001
2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
3 Date: Wed, 23 Mar 2016 19:08:19 +0800
4 Subject: [PATCH 03/13] dt/bindings: Add bindings for Layerscape SCFG MSI
6 Cherry-pick upstream patch.
8 Some Layerscape SoCs use a simple MSI controller implementation.
9 It contains only two SCFG register to trigger and describe a
10 group 32 MSI interrupts. The patch adds bindings to describe
13 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
14 Acked-by: Rob Herring <robh@kernel.org>
15 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 ++++++++++++++++++++++
18 1 file changed, 30 insertions(+)
19 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
21 diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
23 index 0000000..9e38949
25 +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
27 +* Freescale Layerscape SCFG PCIe MSI controller
31 +- compatible: should be "fsl,<soc-name>-msi" to identify
32 + Layerscape PCIe MSI controller block such as:
35 +- msi-controller: indicates that this is a PCIe MSI controller node
36 +- reg: physical base address of the controller and length of memory mapped.
37 +- interrupts: an interrupt to the parent interrupt controller.
40 +- interrupt-parent: the phandle to the parent interrupt controller.
42 +This interrupt controller hardware is a second level interrupt controller that
43 +is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
44 +platforms. If interrupt-parent is not provided, the default parent interrupt
45 +controller will be used.
46 +Each PCIe node needs to have property msi-parent that points to
51 + msi1: msi-controller@1571000 {
52 + compatible = "fsl,1s1043a-msi";
53 + reg = <0x0 0x1571000 0x0 0x8>,
55 + interrupts = <0 116 0x4>;