1 From acfc6e9b34b3b3ca0d8bbe366dd08b0fac21c740 Mon Sep 17 00:00:00 2001
2 From: Yunhui Cui <yunhui.cui@nxp.com>
3 Date: Tue, 2 Feb 2016 12:21:12 +0800
4 Subject: [PATCH 101/113] mtd: spi-nor: fsl-quadspi: extend support for some
7 Add extra info in LUT table to support some special requerments.
8 Spansion S25FS-S family flash need some special operations.
10 Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
12 drivers/mtd/spi-nor/fsl-quadspi.c | 44 +++++++++++++++++++++++++++++++++++--
13 include/linux/mtd/spi-nor.h | 4 ++++
14 2 files changed, 46 insertions(+), 2 deletions(-)
16 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
17 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
22 +#define SEQID_RDAR 12
23 +#define SEQID_WRAR 13
26 #define QUADSPI_MIN_IOMAP SZ_4M
28 @@ -470,6 +473,28 @@ static void fsl_qspi_init_lut(struct fsl
29 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
30 base + QUADSPI_LUT(lut_base));
33 + * Read any device register.
34 + * Used for Spansion S25FS-S family flash only.
36 + lut_base = SEQID_RDAR * 4;
37 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
38 + LUT1(ADDR, PAD1, ADDR24BIT),
39 + base + QUADSPI_LUT(lut_base));
40 + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
41 + base + QUADSPI_LUT(lut_base + 1));
44 + * Write any device register.
45 + * Used for Spansion S25FS-S family flash only.
47 + lut_base = SEQID_WRAR * 4;
48 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
49 + LUT1(ADDR, PAD1, ADDR24BIT),
50 + base + QUADSPI_LUT(lut_base));
51 + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
52 + base + QUADSPI_LUT(lut_base + 1));
57 @@ -477,9 +502,15 @@ static void fsl_qspi_init_lut(struct fsl
58 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
61 + case SPINOR_OP_READ4_1_1_4:
62 case SPINOR_OP_READ_1_1_4:
63 case SPINOR_OP_READ_FAST:
64 + case SPINOR_OP_READ4_FAST:
66 + case SPINOR_OP_SPANSION_RDAR:
68 + case SPINOR_OP_SPANSION_WRAR:
73 @@ -491,6 +522,7 @@ static int fsl_qspi_get_seqid(struct fsl
74 case SPINOR_OP_CHIP_ERASE:
75 return SEQID_CHIP_ERASE;
77 + case SPINOR_OP_PP_4B:
81 @@ -830,8 +862,12 @@ static int fsl_qspi_read_reg(struct spi_
84 struct fsl_qspi *q = nor->priv;
87 + if (opcode == SPINOR_OP_SPANSION_RDAR)
88 + memcpy(&to, nor->cmd_buf, 4);
90 - ret = fsl_qspi_runcmd(q, opcode, 0, len);
91 + ret = fsl_qspi_runcmd(q, opcode, to, len);
95 @@ -843,9 +879,13 @@ static int fsl_qspi_write_reg(struct spi
97 struct fsl_qspi *q = nor->priv;
101 + if (opcode == SPINOR_OP_SPANSION_WRAR)
102 + memcpy(&to, nor->cmd_buf, 4);
105 - ret = fsl_qspi_runcmd(q, opcode, 0, 1);
106 + ret = fsl_qspi_runcmd(q, opcode, to, 1);
110 --- a/include/linux/mtd/spi-nor.h
111 +++ b/include/linux/mtd/spi-nor.h
113 /* Used for Spansion flashes only. */
114 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
116 +/* Used for Spansion S25FS-S family flash only. */
117 +#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
118 +#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
120 /* Used for Micron flashes only. */
121 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
122 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */