1 From 23cd071c47c064d56921975d196dc22177069dea Mon Sep 17 00:00:00 2001
2 From: Yunhui Cui <yunhui.cui@nxp.com>
3 Date: Wed, 24 Feb 2016 15:14:01 +0800
4 Subject: [PATCH 104/113] mtd: fsl-quadspi: Add quad mode for flash n25q128
6 Add some lut_tables to support quad mode for flash n25q128
7 on the board ls1021a-twr and solve flash Spansion and Micron
9 In switch {}, The value of command SPINOR_OP_RD_EVCR and
10 SPINOR_OP_SPANSION_RDAR is the same. They have to share
11 the same seq_id: SEQID_RDAR_OR_RD_EVCR.
13 Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
15 drivers/mtd/spi-nor/fsl-quadspi.c | 47 ++++++++++++++++++++++++++++---------
16 1 file changed, 36 insertions(+), 11 deletions(-)
18 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
19 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
24 -#define SEQID_RDAR 12
25 +#define SEQID_RDAR_OR_RD_EVCR 12
28 +#define SEQID_WD_EVCR 14
30 #define QUADSPI_MIN_IOMAP SZ_4M
32 @@ -393,6 +393,7 @@ static void fsl_qspi_init_lut(struct fsl
33 int rxfifo = q->devtype_data->rxfifo;
36 + const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
38 struct spi_nor *nor = &q->nor[0];
39 u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
40 @@ -489,16 +490,26 @@ static void fsl_qspi_init_lut(struct fsl
41 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
42 base + QUADSPI_LUT(lut_base));
46 - * Read any device register.
47 - * Used for Spansion S25FS-S family flash only.
48 + * Flash Micron and Spansion command confilict
49 + * use the same value 0x65. But it indicates different meaning.
51 - lut_base = SEQID_RDAR * 4;
52 - qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
53 - LUT1(ADDR, PAD1, ADDR24BIT),
54 - base + QUADSPI_LUT(lut_base));
55 - qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
56 - base + QUADSPI_LUT(lut_base + 1));
57 + lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
58 + if (devtype_data->devtype == FSL_QUADSPI_LS2080A) {
60 + * Read any device register.
61 + * Used for Spansion S25FS-S family flash only.
63 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
64 + LUT1(ADDR, PAD1, ADDR24BIT),
65 + base + QUADSPI_LUT(lut_base));
66 + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
67 + base + QUADSPI_LUT(lut_base + 1));
69 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
70 + base + QUADSPI_LUT(lut_base));
74 * Write any device register.
75 @@ -511,6 +522,11 @@ static void fsl_qspi_init_lut(struct fsl
76 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
77 base + QUADSPI_LUT(lut_base + 1));
79 + /* Write EVCR register */
80 + lut_base = SEQID_WD_EVCR * 4;
81 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
82 + base + QUADSPI_LUT(lut_base));
87 @@ -523,8 +539,15 @@ static int fsl_qspi_get_seqid(struct fsl
88 case SPINOR_OP_READ_FAST:
89 case SPINOR_OP_READ4_FAST:
92 + * Spansion & Micron use the same command value 0x65
93 + * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
94 + * Micron: SPINOR_OP_RD_EVCR,
95 + * read enhanced volatile configuration register.
96 + * case SPINOR_OP_RD_EVCR:
98 case SPINOR_OP_SPANSION_RDAR:
100 + return SEQID_RDAR_OR_RD_EVCR;
101 case SPINOR_OP_SPANSION_WRAR:
104 @@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl
108 + case SPINOR_OP_WD_EVCR:
109 + return SEQID_WD_EVCR;
111 if (cmd == q->nor[0].erase_opcode)