1 From 3970a709eb4c25e298e11cfe0ea7412bb2139197 Mon Sep 17 00:00:00 2001
2 From: Alison Wang <alison.wang@nxp.com>
3 Date: Fri, 8 Jul 2016 10:50:46 +0800
4 Subject: [PATCH 03/70] arm64: dts: Update address-cells and reg properties of
7 commit 67161e229a59faf81732892b45a9ab3bae62ea18
10 MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
11 LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
12 since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
13 the #address-cells and reg properties accordingly.
15 Signed-off-by: Alison Wang <alison.wang@nxp.com>
16 Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
18 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 10 +++++-----
19 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 18 +++++++++---------
20 2 files changed, 14 insertions(+), 14 deletions(-)
22 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
23 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
28 - #address-cells = <2>;
29 + #address-cells = <1>;
36 compatible = "arm,cortex-a53";
39 clocks = <&clockgen 1 0>;
44 compatible = "arm,cortex-a53";
47 clocks = <&clockgen 1 0>;
52 compatible = "arm,cortex-a53";
55 clocks = <&clockgen 1 0>;
60 compatible = "arm,cortex-a53";
63 clocks = <&clockgen 1 0>;
66 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
67 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
72 - #address-cells = <2>;
73 + #address-cells = <1>;
80 compatible = "arm,cortex-a57";
83 clocks = <&clockgen 1 0>;
88 compatible = "arm,cortex-a57";
91 clocks = <&clockgen 1 0>;
96 compatible = "arm,cortex-a57";
99 clocks = <&clockgen 1 1>;
104 compatible = "arm,cortex-a57";
107 clocks = <&clockgen 1 1>;
112 compatible = "arm,cortex-a57";
115 clocks = <&clockgen 1 2>;
120 compatible = "arm,cortex-a57";
123 clocks = <&clockgen 1 2>;
128 compatible = "arm,cortex-a57";
131 clocks = <&clockgen 1 3>;
136 compatible = "arm,cortex-a57";
139 clocks = <&clockgen 1 3>;