1 From cbacf87fa6fb262c98033405f15697798c3a9c5d Mon Sep 17 00:00:00 2001
2 From: Zhao Qiang <qiang.zhao@nxp.com>
3 Date: Sun, 9 Oct 2016 14:31:50 +0800
4 Subject: [PATCH 135/141] arm64: Add DTS support for FSL's LS1088ARDB
6 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
8 arch/arm64/boot/dts/freescale/Makefile | 1 +
9 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 203 ++++++++
10 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 557 +++++++++++++++++++++
11 3 files changed, 761 insertions(+)
12 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
13 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
15 --- a/arch/arm64/boot/dts/freescale/Makefile
16 +++ b/arch/arm64/boot/dts/freescale/Makefile
17 @@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
18 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
19 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
20 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
21 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
24 subdir-y := $(dts-dirs)
26 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
29 + * Device Tree file for Freescale LS1088a RDB board
31 + * Copyright (C) 2015, Freescale Semiconductor
33 + * This file is licensed under the terms of the GNU General Public
34 + * License version 2. This program is licensed "as is" without any
35 + * warranty of any kind, whether express or implied.
40 +#include "fsl-ls1088a.dtsi"
43 + model = "Freescale Layerscape 1088a RDB Board";
44 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
52 + status = "disabled";
62 + compatible = "philips,pca9547";
64 + #address-cells = <1>;
68 + #address-cells = <1>;
73 + compatible = "ti,ina220";
75 + shunt-resistor = <1000>;
80 + #address-cells = <1>;
85 + compatible = "nxp,pcf2129";
88 + interrupts = <0 150 0x4>;
92 + compatible = "adt7461a";
100 + status = "disabled";
104 + status = "disabled";
108 + status = "disabled";
112 + status = "disabled";
117 + qflash0: s25fs512s@0 {
118 + compatible = "spansion,m25p80";
119 + #address-cells = <1>;
121 + spi-max-frequency = <20000000>;
125 + qflash1: s25fs512s@1 {
126 + compatible = "spansion,m25p80";
127 + #address-cells = <1>;
129 + spi-max-frequency = <20000000>;
155 + /* Freescale F104 PHY1 */
156 + mdio1_phy1: emdio1_phy@1 {
158 + phy-connection-type = "qsgmii";
160 + mdio1_phy2: emdio1_phy@2 {
162 + phy-connection-type = "qsgmii";
164 + mdio1_phy3: emdio1_phy@3 {
166 + phy-connection-type = "qsgmii";
168 + mdio1_phy4: emdio1_phy@4 {
170 + phy-connection-type = "qsgmii";
173 + mdio1_phy5: emdio1_phy@5 {
175 + phy-connection-type = "qsgmii";
177 + mdio1_phy6: emdio1_phy@6 {
179 + phy-connection-type = "qsgmii";
181 + mdio1_phy7: emdio1_phy@7 {
183 + phy-connection-type = "qsgmii";
185 + mdio1_phy8: emdio1_phy@8 {
187 + phy-connection-type = "qsgmii";
192 + /* Aquantia AQR105 10G PHY */
193 + mdio2_phy1: emdio2_phy@1 {
194 + compatible = "ethernet-phy-ieee802.3-c45";
196 + phy-connection-type = "xfi";
200 +/* DPMAC connections to external PHYs
201 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
203 +/* DPMAC1 is 10G SFP+, fixed link */
205 + phy-handle = <&mdio2_phy1>;
208 + phy-handle = <&mdio1_phy5>;
211 + phy-handle = <&mdio1_phy6>;
214 + phy-handle = <&mdio1_phy7>;
217 + phy-handle = <&mdio1_phy8>;
220 + phy-handle = <&mdio1_phy1>;
223 + phy-handle = <&mdio1_phy2>;
226 + phy-handle = <&mdio1_phy3>;
229 + phy-handle = <&mdio1_phy4>;
232 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
235 + * Device Tree Include file for Freescale Layerscape-1088A family SoC.
237 + * Copyright (C) 2015, Freescale Semiconductor
241 +/memreserve/ 0x80000000 0x00010000;
244 + compatible = "fsl,ls1088a";
245 + interrupt-parent = <&gic>;
246 + #address-cells = <2>;
250 + #address-cells = <2>;
253 + /* We have 2 clusters having 4 Cortex-A57 cores each */
255 + device_type = "cpu";
256 + compatible = "arm,cortex-a53";
258 + clocks = <&clockgen 1 0>;
262 + device_type = "cpu";
263 + compatible = "arm,cortex-a53";
265 + clocks = <&clockgen 1 0>;
269 + device_type = "cpu";
270 + compatible = "arm,cortex-a53";
272 + clocks = <&clockgen 1 0>;
276 + device_type = "cpu";
277 + compatible = "arm,cortex-a53";
279 + clocks = <&clockgen 1 0>;
283 + device_type = "cpu";
284 + compatible = "arm,cortex-a53";
286 + clocks = <&clockgen 1 1>;
290 + device_type = "cpu";
291 + compatible = "arm,cortex-a53";
293 + clocks = <&clockgen 1 1>;
297 + device_type = "cpu";
298 + compatible = "arm,cortex-a53";
300 + clocks = <&clockgen 1 1>;
304 + device_type = "cpu";
305 + compatible = "arm,cortex-a53";
307 + clocks = <&clockgen 1 1>;
312 + compatible = "arm,armv8-pmuv3";
313 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
316 + gic: interrupt-controller@6000000 {
317 + compatible = "arm,gic-v3";
318 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
319 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
320 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
321 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
322 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
323 + #interrupt-cells = <3>;
324 + #address-cells = <2>;
327 + interrupt-controller;
328 + interrupts = <1 9 0x4>;
330 + its: gic-its@6020000 {
331 + compatible = "arm,gic-v3-its";
333 + reg = <0x0 0x6020000 0 0x20000>;
338 + compatible = "fixed-clock";
339 + #clock-cells = <0>;
340 + clock-frequency = <100000000>;
341 + clock-output-names = "sysclk";
344 + clockgen: clocking@1300000 {
345 + compatible = "fsl,ls2080a-clockgen", "fsl,ls1088a-clockgen";
346 + reg = <0 0x1300000 0 0xa0000>;
347 + #clock-cells = <2>;
348 + clocks = <&sysclk>;
351 + serial0: serial@21c0500 {
352 + device_type = "serial";
353 + compatible = "fsl,ns16550", "ns16550a";
354 + reg = <0x0 0x21c0500 0x0 0x100>;
355 + clocks = <&clockgen 4 3>;
356 + interrupts = <0 32 0x4>; /* Level high type */
359 + serial1: serial@21c0600 {
360 + device_type = "serial";
361 + compatible = "fsl,ns16550", "ns16550a";
362 + reg = <0x0 0x21c0600 0x0 0x100>;
363 + clocks = <&clockgen 4 3>;
364 + interrupts = <0 32 0x4>; /* Level high type */
367 + gpio0: gpio@2300000 {
368 + compatible = "fsl,qoriq-gpio";
369 + reg = <0x0 0x2300000 0x0 0x10000>;
370 + interrupts = <0 36 0x4>; /* Level high type */
374 + interrupt-controller;
375 + #interrupt-cells = <2>;
378 + gpio1: gpio@2310000 {
379 + compatible = "fsl,qoriq-gpio";
380 + reg = <0x0 0x2310000 0x0 0x10000>;
381 + interrupts = <0 36 0x4>; /* Level high type */
385 + interrupt-controller;
386 + #interrupt-cells = <2>;
389 + gpio2: gpio@2320000 {
390 + compatible = "fsl,qoriq-gpio";
391 + reg = <0x0 0x2320000 0x0 0x10000>;
392 + interrupts = <0 37 0x4>; /* Level high type */
396 + interrupt-controller;
397 + #interrupt-cells = <2>;
400 + gpio3: gpio@2330000 {
401 + compatible = "fsl,qoriq-gpio";
402 + reg = <0x0 0x2330000 0x0 0x10000>;
403 + interrupts = <0 37 0x4>; /* Level high type */
407 + interrupt-controller;
408 + #interrupt-cells = <2>;
411 + /* TODO: WRIOP (CCSR?) */
412 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
413 + compatible = "fsl,fman-memac-mdio";
414 + reg = <0x0 0x8B96000 0x0 0x1000>;
415 + device_type = "mdio";
416 + little-endian; /* force the driver in LE mode */
418 + /* Not necessary on the QDS, but needed on the RDB */
419 + #address-cells = <1>;
423 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
424 + compatible = "fsl,fman-memac-mdio";
425 + reg = <0x0 0x8B97000 0x0 0x1000>;
426 + device_type = "mdio";
427 + little-endian; /* force the driver in LE mode */
429 + #address-cells = <1>;
434 + compatible = "fsl,ifc", "simple-bus";
435 + reg = <0x0 0x2240000 0x0 0x20000>;
436 + interrupts = <0 21 0x4>; /* Level high type */
438 + #address-cells = <2>;
441 + ranges = <0 0 0x5 0x80000000 0x08000000
442 + 2 0 0x5 0x30000000 0x00010000
443 + 3 0 0x5 0x20000000 0x00010000>;
446 + esdhc: esdhc@2140000 {
447 + compatible = "fsl,ls2080a-esdhc", "fsl,ls1088a-esdhc", "fsl,esdhc";
448 + reg = <0x0 0x2140000 0x0 0x10000>;
449 + interrupts = <0 28 0x4>; /* Level high type */
450 + clock-frequency = <0>;
451 + voltage-ranges = <1800 1800 3300 3300>;
457 + ftm0: ftm0@2800000 {
458 + compatible = "fsl,ftm-alarm";
459 + reg = <0x0 0x2800000 0x0 0x10000>;
460 + interrupts = <0 44 4>;
463 + reset: reset@1E60000 {
464 + compatible = "fsl,ls-reset";
465 + reg = <0x0 0x1E60000 0x0 0x10000>;
468 + dspi: dspi@2100000 {
469 + compatible = "fsl,ls2085a-dspi", "fsl,ls1088a-dspi";
470 + #address-cells = <1>;
472 + reg = <0x0 0x2100000 0x0 0x10000>;
473 + interrupts = <0 26 0x4>; /* Level high type */
474 + clocks = <&clockgen 4 3>;
475 + clock-names = "dspi";
476 + spi-num-chipselects = <5>;
480 + i2c0: i2c@2000000 {
481 + compatible = "fsl,vf610-i2c";
482 + #address-cells = <1>;
484 + reg = <0x0 0x2000000 0x0 0x10000>;
485 + interrupts = <0 34 0x4>; /* Level high type */
486 + clock-names = "i2c";
487 + clocks = <&clockgen 4 3>;
490 + i2c1: i2c@2010000 {
491 + compatible = "fsl,vf610-i2c";
492 + #address-cells = <1>;
494 + reg = <0x0 0x2010000 0x0 0x10000>;
495 + interrupts = <0 34 0x4>; /* Level high type */
496 + clock-names = "i2c";
497 + clocks = <&clockgen 4 3>;
500 + i2c2: i2c@2020000 {
501 + compatible = "fsl,vf610-i2c";
502 + #address-cells = <1>;
504 + reg = <0x0 0x2020000 0x0 0x10000>;
505 + interrupts = <0 35 0x4>; /* Level high type */
506 + clock-names = "i2c";
507 + clocks = <&clockgen 4 3>;
510 + i2c3: i2c@2030000 {
511 + compatible = "fsl,vf610-i2c";
512 + #address-cells = <1>;
514 + reg = <0x0 0x2030000 0x0 0x10000>;
515 + interrupts = <0 35 0x4>; /* Level high type */
516 + clock-names = "i2c";
517 + clocks = <&clockgen 4 3>;
520 + qspi: quadspi@20c0000 {
521 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
522 + #address-cells = <1>;
524 + reg = <0x0 0x20c0000 0x0 0x10000>,
525 + <0x0 0x20000000 0x0 0x10000000>;
526 + reg-names = "QuadSPI", "QuadSPI-memory";
527 + interrupts = <0 25 0x4>; /* Level high type */
528 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
529 + clock-names = "qspi_en", "qspi";
533 + compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
534 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
535 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
536 + reg-names = "regs", "config";
537 + interrupts = <0 108 0x4>; /* aer interrupt */
538 + interrupt-names = "aer";
539 + #address-cells = <3>;
541 + device_type = "pci";
544 + bus-range = <0x0 0xff>;
545 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
546 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
547 + msi-parent = <&its>;
548 + #interrupt-cells = <1>;
549 + interrupt-map-mask = <0 0 0 7>;
550 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
551 + <0000 0 0 2 &gic 0 0 0 110 4>,
552 + <0000 0 0 3 &gic 0 0 0 111 4>,
553 + <0000 0 0 4 &gic 0 0 0 112 4>;
556 + compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
557 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
558 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
559 + reg-names = "regs", "config";
560 + interrupts = <0 113 0x4>; /* aer interrupt */
561 + interrupt-names = "aer";
562 + #address-cells = <3>;
564 + device_type = "pci";
567 + bus-range = <0x0 0xff>;
568 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
569 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
570 + msi-parent = <&its>;
571 + #interrupt-cells = <1>;
572 + interrupt-map-mask = <0 0 0 7>;
573 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
574 + <0000 0 0 2 &gic 0 0 0 115 4>,
575 + <0000 0 0 3 &gic 0 0 0 116 4>,
576 + <0000 0 0 4 &gic 0 0 0 117 4>;
580 + compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
581 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
582 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
583 + reg-names = "regs", "config";
584 + interrupts = <0 118 0x4>; /* aer interrupt */
585 + interrupt-names = "aer";
586 + #address-cells = <3>;
588 + device_type = "pci";
591 + bus-range = <0x0 0xff>;
592 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
593 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
594 + msi-parent = <&its>;
595 + #interrupt-cells = <1>;
596 + interrupt-map-mask = <0 0 0 7>;
597 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
598 + <0000 0 0 2 &gic 0 0 0 120 4>,
599 + <0000 0 0 3 &gic 0 0 0 121 4>,
600 + <0000 0 0 4 &gic 0 0 0 122 4>;
603 + sata0: sata@3200000 {
604 + compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
605 + reg = <0x0 0x3200000 0x0 0x10000>;
606 + interrupts = <0 133 0x4>; /* Level high type */
607 + clocks = <&clockgen 4 3>;
610 + usb0: usb3@3100000 {
611 + compatible = "snps,dwc3";
612 + reg = <0x0 0x3100000 0x0 0x10000>;
613 + interrupts = <0 80 0x4>; /* Level high type */
616 + snps,dis_rxdet_inp3_quirk;
619 + usb1: usb3@3110000 {
620 + compatible = "snps,dwc3";
621 + reg = <0x0 0x3110000 0x0 0x10000>;
622 + interrupts = <0 81 0x4>; /* Level high type */
625 + snps,dis_rxdet_inp3_quirk;
628 + smmu: iommu@5000000 {
629 + compatible = "arm,mmu-500";
630 + reg = <0 0x5000000 0 0x800000>;
631 + #global-interrupts = <12>;
632 + interrupts = <0 13 4>, /* global secure fault */
633 + <0 14 4>, /* combined secure interrupt */
634 + <0 15 4>, /* global non-secure fault */
635 + <0 16 4>, /* combined non-secure interrupt */
636 + /* performance counter interrupts 0-7 */
645 + /* per context interrupt, 64 interrupts */
710 + mmu-masters = <&fsl_mc 0x300 0>;
714 + compatible = "arm,armv8-timer";
715 + interrupts = <1 13 0x1>,/*Phy Secure PPI, edge triggered*/
716 + <1 14 0x1>, /*Phy Non-Secure PPI, edge triggered*/
717 + <1 11 0x1>, /*Virtual PPI, edge triggered */
718 + <1 10 0x1>; /*Hypervisor PPI, edge triggered */
721 + fsl_mc: fsl-mc@80c000000 {
722 + compatible = "fsl,qoriq-mc";
723 + #stream-id-cells = <2>;
724 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
725 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
726 + msi-parent = <&its>;
727 + #address-cells = <3>;
731 + * Region type 0x0 - MC portals
732 + * Region type 0x1 - QBMAN portals
734 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
735 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
738 + #address-cells = <1>;
742 + compatible = "fsl,qoriq-mc-dpmac";
746 + compatible = "fsl,qoriq-mc-dpmac";
750 + compatible = "fsl,qoriq-mc-dpmac";
754 + compatible = "fsl,qoriq-mc-dpmac";
758 + compatible = "fsl,qoriq-mc-dpmac";
762 + compatible = "fsl,qoriq-mc-dpmac";
766 + compatible = "fsl,qoriq-mc-dpmac";
770 + compatible = "fsl,qoriq-mc-dpmac";
774 + compatible = "fsl,qoriq-mc-dpmac";
777 + dpmac10: dpmac@10 {
778 + compatible = "fsl,qoriq-mc-dpmac";
786 + device_type = "memory";
787 + reg = <0x00000000 0x80000000 0 0x80000000>;
788 + /* DRAM space 1 - 2 GB DRAM */