1 From 45ba5bb2bdc9462fe5998aeb75e2c7e33b56c9fb Mon Sep 17 00:00:00 2001
2 From: Zhao Qiang <qiang.zhao@nxp.com>
3 Date: Mon, 7 Nov 2016 10:23:52 +0800
4 Subject: [PATCH 227/238] ls2088a/dts: add ls2088a dts
6 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
8 arch/arm64/boot/dts/freescale/Makefile | 2 +
9 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 241 ++++++
10 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 207 +++++
11 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 854 +++++++++++++++++++++
12 4 files changed, 1304 insertions(+)
13 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
14 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
15 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
17 diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
18 index b599645..e6c2a9f 100644
19 --- a/arch/arm64/boot/dts/freescale/Makefile
20 +++ b/arch/arm64/boot/dts/freescale/Makefile
21 @@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
22 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
23 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
24 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
25 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
26 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
29 subdir-y := $(dts-dirs)
30 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
32 index 0000000..04d3726
34 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
37 + * Device Tree file for Freescale LS2080a QDS Board
39 + * Copyright (C) 2016, Freescale Semiconductor
41 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
43 + * This file is licensed under the terms of the GNU General Public
44 + * License version 2. This program is licensed "as is" without any
45 + * warranty of any kind, whether express or implied.
50 +#include "fsl-ls2088a.dtsi"
53 + model = "Freescale Layerscape 2088a QDS Board";
54 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
63 + #address-cells = <2>;
65 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
66 + 0x2 0x0 0x5 0x30000000 0x00010000
67 + 0x3 0x0 0x5 0x20000000 0x00010000>;
70 + #address-cells = <1>;
72 + compatible = "cfi-flash";
73 + reg = <0x0 0x0 0x8000000>;
79 + compatible = "fsl,ifc-nand";
80 + reg = <0x2 0x0 0x10000>;
84 + reg = <0x3 0x0 0x10000>;
85 + compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
97 + compatible = "nxp,pca9547";
99 + #address-cells = <1>;
102 + #address-cells = <1>;
106 + compatible = "dallas,ds3232";
112 + #address-cells = <1>;
117 + compatible = "ti,ina220";
119 + shunt-resistor = <500>;
122 + compatible = "ti,ina220";
124 + shunt-resistor = <1000>;
129 + #address-cells = <1>;
134 + compatible = "adi,adt7461";
142 + status = "disabled";
146 + status = "disabled";
150 + status = "disabled";
155 + dflash0: n25q128a {
156 + #address-cells = <1>;
158 + compatible = "st,m25p80";
159 + spi-max-frequency = <3000000>;
162 + dflash1: sst25wf040b {
163 + #address-cells = <1>;
165 + compatible = "st,m25p80";
166 + spi-max-frequency = <3000000>;
170 + #address-cells = <1>;
172 + compatible = "st,m25p80";
173 + spi-max-frequency = <3000000>;
180 + qflash0: s25fs256s1@0 {
181 + #address-cells = <1>;
183 + compatible = "st,m25p80";
184 + spi-max-frequency = <20000000>;
189 + qflash2: s25fs256s1@2 {
190 + #address-cells = <1>;
192 + compatible = "st,m25p80";
193 + spi-max-frequency = <20000000>;
216 + boardctrl: board-control@3,0 {
217 + #address-cells = <1>;
219 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
220 + reg = <3 0 0x300>; /* TODO check address */
221 + ranges = <0 3 0 0x300>;
224 + compatible = "mdio-mux-mmioreg", "mdio-mux";
225 + mdio-parent-bus = <&emdio1>;
226 + reg = <0x54 1>; /* BRDCFG4 */
227 + mux-mask = <0xe0>; /* EMI1_MDIO */
229 + #address-cells=<1>;
232 + /* Child MDIO buses, one for each riser card:
233 + reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
235 + VSC8234 PHYs on the riser cards.
238 + mdio_mux3: mdio@60 {
240 + #address-cells = <1>;
243 + mdio0_phy12: mdio_phy0@1c {
245 + phy-connection-type = "sgmii";
247 + mdio0_phy13: mdio_phy1@1d {
249 + phy-connection-type = "sgmii";
251 + mdio0_phy14: mdio_phy2@1e {
253 + phy-connection-type = "sgmii";
255 + mdio0_phy15: mdio_phy3@1f {
257 + phy-connection-type = "sgmii";
264 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
266 + phy-handle = <&mdio0_phy12>;
269 + phy-handle = <&mdio0_phy13>;
272 + phy-handle = <&mdio0_phy14>;
275 + phy-handle = <&mdio0_phy15>;
277 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
279 index 0000000..ce553fb
281 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
284 + * Device Tree file for Freescale LS2080a RDB board
286 + * Copyright (C) 2015, Freescale Semiconductor
288 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
290 + * This file is licensed under the terms of the GNU General Public
291 + * License version 2. This program is licensed "as is" without any
292 + * warranty of any kind, whether express or implied.
297 +#include "fsl-ls2088a.dtsi"
300 + model = "Freescale Layerscape 2088a RDB Board";
301 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
310 + #address-cells = <2>;
312 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
313 + 0x2 0x0 0x5 0x30000000 0x00010000
314 + 0x3 0x0 0x5 0x20000000 0x00010000>;
317 + #address-cells = <1>;
319 + compatible = "cfi-flash";
320 + reg = <0x0 0x0 0x8000000>;
322 + device-width = <1>;
326 + compatible = "fsl,ifc-nand";
327 + reg = <0x2 0x0 0x10000>;
331 + reg = <0x3 0x0 0x10000>;
332 + compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
344 + compatible = "nxp,pca9547";
346 + #address-cells = <1>;
348 + i2c-mux-never-disable;
350 + #address-cells = <1>;
354 + compatible = "dallas,ds3232";
360 + #address-cells = <1>;
365 + compatible = "adi,adt7461";
373 + status = "disabled";
377 + status = "disabled";
381 + status = "disabled";
386 + dflash0: n25q512a {
387 + #address-cells = <1>;
389 + compatible = "st,m25p80";
390 + spi-max-frequency = <3000000>;
396 + status = "disabled";
417 + mdio1_phy1: emdio1_phy@1 {
419 + phy-connection-type = "xfi";
421 + mdio1_phy2: emdio1_phy@2 {
423 + phy-connection-type = "xfi";
425 + mdio1_phy3: emdio1_phy@3 {
427 + phy-connection-type = "xfi";
429 + mdio1_phy4: emdio1_phy@4 {
431 + phy-connection-type = "xfi";
437 + mdio2_phy1: emdio2_phy@1 {
438 + compatible = "ethernet-phy-ieee802.3-c45";
439 + interrupts = <0 1 0x4>; /* Level high type */
441 + phy-connection-type = "xfi";
443 + mdio2_phy2: emdio2_phy@2 {
444 + compatible = "ethernet-phy-ieee802.3-c45";
445 + interrupts = <0 2 0x4>; /* Level high type */
447 + phy-connection-type = "xfi";
449 + mdio2_phy3: emdio2_phy@3 {
450 + compatible = "ethernet-phy-ieee802.3-c45";
451 + interrupts = <0 4 0x4>; /* Level high type */
453 + phy-connection-type = "xfi";
455 + mdio2_phy4: emdio2_phy@4 {
456 + compatible = "ethernet-phy-ieee802.3-c45";
457 + interrupts = <0 5 0x4>; /* Level high type */
459 + phy-connection-type = "xfi";
463 +/* Update DPMAC connections to external PHYs, under the assumption of
464 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
467 + phy-handle = <&mdio1_phy1>;
470 + phy-handle = <&mdio1_phy2>;
473 + phy-handle = <&mdio1_phy3>;
476 + phy-handle = <&mdio1_phy4>;
479 + phy-handle = <&mdio2_phy1>;
482 + phy-handle = <&mdio2_phy2>;
485 + phy-handle = <&mdio2_phy3>;
488 + phy-handle = <&mdio2_phy4>;
490 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
492 index 0000000..bd69942
494 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
497 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
499 + * Copyright (C) 2016, Freescale Semiconductor
501 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
503 + * This file is dual-licensed: you can use it either under the terms
504 + * of the GPLv2 or the X11 license, at your option. Note that this dual
505 + * licensing only applies to this file, and not this project as a
508 + * a) This library is free software; you can redistribute it and/or
509 + * modify it under the terms of the GNU General Public License as
510 + * published by the Free Software Foundation; either version 2 of the
511 + * License, or (at your option) any later version.
513 + * This library is distributed in the hope that it will be useful,
514 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
515 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
516 + * GNU General Public License for more details.
518 + * Or, alternatively,
520 + * b) Permission is hereby granted, free of charge, to any person
521 + * obtaining a copy of this software and associated documentation
522 + * files (the "Software"), to deal in the Software without
523 + * restriction, including without limitation the rights to use,
524 + * copy, modify, merge, publish, distribute, sublicense, and/or
525 + * sell copies of the Software, and to permit persons to whom the
526 + * Software is furnished to do so, subject to the following
529 + * The above copyright notice and this permission notice shall be
530 + * included in all copies or substantial portions of the Software.
532 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
533 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
534 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
535 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
536 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
537 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
538 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
539 + * OTHER DEALINGS IN THE SOFTWARE.
542 +#include <dt-bindings/thermal/thermal.h>
544 +/memreserve/ 0x80000000 0x00010000;
547 + compatible = "fsl,ls2088a";
548 + interrupt-parent = <&gic>;
549 + #address-cells = <2>;
553 + #address-cells = <2>;
557 + device_type = "cpu";
558 + compatible = "arm,cortex-a72";
560 + clocks = <&clockgen 1 0>;
561 + #cooling-cells = <2>;
562 + cpu-idle-states = <&CPU_PW20>;
566 + device_type = "cpu";
567 + compatible = "arm,cortex-a72";
569 + clocks = <&clockgen 1 0>;
570 + cpu-idle-states = <&CPU_PW20>;
574 + device_type = "cpu";
575 + compatible = "arm,cortex-a72";
577 + clocks = <&clockgen 1 1>;
578 + #cooling-cells = <2>;
579 + cpu-idle-states = <&CPU_PW20>;
583 + device_type = "cpu";
584 + compatible = "arm,cortex-a72";
586 + clocks = <&clockgen 1 1>;
587 + cpu-idle-states = <&CPU_PW20>;
591 + device_type = "cpu";
592 + compatible = "arm,cortex-a72";
594 + clocks = <&clockgen 1 2>;
595 + #cooling-cells = <2>;
596 + cpu-idle-states = <&CPU_PW20>;
600 + device_type = "cpu";
601 + compatible = "arm,cortex-a72";
603 + clocks = <&clockgen 1 2>;
604 + cpu-idle-states = <&CPU_PW20>;
608 + device_type = "cpu";
609 + compatible = "arm,cortex-a72";
611 + clocks = <&clockgen 1 3>;
612 + #cooling-cells = <2>;
613 + cpu-idle-states = <&CPU_PW20>;
617 + device_type = "cpu";
618 + compatible = "arm,cortex-a72";
620 + clocks = <&clockgen 1 3>;
621 + cpu-idle-states = <&CPU_PW20>;
626 + compatible = "arm,armv8-pmuv3";
627 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
631 + entry-method = "arm,psci";
633 + CPU_PW20: cpu-pw20 {
634 + compatible = "arm,idle-state";
635 + idle-state-name = "PW20";
636 + arm,psci-suspend-param = <0x00010000>;
637 + entry-latency-us = <2000>;
638 + exit-latency-us = <2000>;
639 + min-residency-us = <6000>;
643 + gic: interrupt-controller@6000000 {
644 + compatible = "arm,gic-v3";
645 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
646 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
647 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
648 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
649 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
650 + #interrupt-cells = <3>;
651 + #address-cells = <2>;
654 + interrupt-controller;
655 + interrupts = <1 9 0x4>;
657 + its: gic-its@6020000 {
658 + compatible = "arm,gic-v3-its";
660 + reg = <0x0 0x6020000 0 0x20000>;
665 + compatible = "fixed-clock";
666 + #clock-cells = <0>;
667 + clock-frequency = <100000000>;
668 + clock-output-names = "sysclk";
671 + clockgen: clocking@1300000 {
672 + compatible = "fsl,ls2088a-clockgen";
673 + reg = <0 0x1300000 0 0xa0000>;
674 + #clock-cells = <2>;
675 + clocks = <&sysclk>;
679 + compatible = "fsl,qoriq-tmu", "fsl,ls2080a-tmu", "fsl,ls2088a-tmu";
680 + reg = <0x0 0x1f80000 0x0 0x10000>;
681 + interrupts = <0 23 0x4>;
682 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
683 + fsl,tmu-calibration = <0x00000000 0x00000026
684 + 0x00000001 0x0000002d
685 + 0x00000002 0x00000032
686 + 0x00000003 0x00000039
687 + 0x00000004 0x0000003f
688 + 0x00000005 0x00000046
689 + 0x00000006 0x0000004d
690 + 0x00000007 0x00000054
691 + 0x00000008 0x0000005a
692 + 0x00000009 0x00000061
693 + 0x0000000a 0x0000006a
694 + 0x0000000b 0x00000071
696 + 0x00010000 0x00000025
697 + 0x00010001 0x0000002c
698 + 0x00010002 0x00000035
699 + 0x00010003 0x0000003d
700 + 0x00010004 0x00000045
701 + 0x00010005 0x0000004e
702 + 0x00010006 0x00000057
703 + 0x00010007 0x00000061
704 + 0x00010008 0x0000006b
705 + 0x00010009 0x00000076
707 + 0x00020000 0x00000029
708 + 0x00020001 0x00000033
709 + 0x00020002 0x0000003d
710 + 0x00020003 0x00000049
711 + 0x00020004 0x00000056
712 + 0x00020005 0x00000061
713 + 0x00020006 0x0000006d
715 + 0x00030000 0x00000021
716 + 0x00030001 0x0000002a
717 + 0x00030002 0x0000003c
718 + 0x00030003 0x0000004e>;
720 + #thermal-sensor-cells = <1>;
724 + cpu_thermal: cpu-thermal {
725 + polling-delay-passive = <1000>;
726 + polling-delay = <5000>;
728 + thermal-sensors = <&tmu 4>;
731 + cpu_alert: cpu-alert {
732 + temperature = <75000>;
733 + hysteresis = <2000>;
736 + cpu_crit: cpu-crit {
737 + temperature = <85000>;
738 + hysteresis = <2000>;
745 + trip = <&cpu_alert>;
747 + <&cpu0 THERMAL_NO_LIMIT
751 + trip = <&cpu_alert>;
753 + <&cpu2 THERMAL_NO_LIMIT
757 + trip = <&cpu_alert>;
759 + <&cpu4 THERMAL_NO_LIMIT
763 + trip = <&cpu_alert>;
765 + <&cpu6 THERMAL_NO_LIMIT
772 + serial0: serial@21c0500 {
773 + device_type = "serial";
774 + compatible = "fsl,ns16550", "ns16550a";
775 + reg = <0x0 0x21c0500 0x0 0x100>;
776 + clocks = <&clockgen 4 3>;
777 + interrupts = <0 32 0x4>; /* Level high type */
780 + serial1: serial@21c0600 {
781 + device_type = "serial";
782 + compatible = "fsl,ns16550", "ns16550a";
783 + reg = <0x0 0x21c0600 0x0 0x100>;
784 + clocks = <&clockgen 4 3>;
785 + interrupts = <0 32 0x4>; /* Level high type */
787 + cluster1_core0_watchdog: wdt@c000000 {
788 + compatible = "arm,sp805-wdt", "arm,primecell";
789 + reg = <0x0 0xc000000 0x0 0x1000>;
790 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
791 + clock-names = "apb_pclk", "wdog_clk";
794 + cluster1_core1_watchdog: wdt@c010000 {
795 + compatible = "arm,sp805-wdt", "arm,primecell";
796 + reg = <0x0 0xc010000 0x0 0x1000>;
797 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
798 + clock-names = "apb_pclk", "wdog_clk";
801 + cluster2_core0_watchdog: wdt@c100000 {
802 + compatible = "arm,sp805-wdt", "arm,primecell";
803 + reg = <0x0 0xc100000 0x0 0x1000>;
804 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
805 + clock-names = "apb_pclk", "wdog_clk";
808 + cluster2_core1_watchdog: wdt@c110000 {
809 + compatible = "arm,sp805-wdt", "arm,primecell";
810 + reg = <0x0 0xc110000 0x0 0x1000>;
811 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
812 + clock-names = "apb_pclk", "wdog_clk";
815 + cluster3_core0_watchdog: wdt@c200000 {
816 + compatible = "arm,sp805-wdt", "arm,primecell";
817 + reg = <0x0 0xc200000 0x0 0x1000>;
818 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
819 + clock-names = "apb_pclk", "wdog_clk";
822 + cluster3_core1_watchdog: wdt@c210000 {
823 + compatible = "arm,sp805-wdt", "arm,primecell";
824 + reg = <0x0 0xc210000 0x0 0x1000>;
825 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
826 + clock-names = "apb_pclk", "wdog_clk";
829 + cluster4_core0_watchdog: wdt@c300000 {
830 + compatible = "arm,sp805-wdt", "arm,primecell";
831 + reg = <0x0 0xc300000 0x0 0x1000>;
832 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
833 + clock-names = "apb_pclk", "wdog_clk";
836 + cluster4_core1_watchdog: wdt@c310000 {
837 + compatible = "arm,sp805-wdt", "arm,primecell";
838 + reg = <0x0 0xc310000 0x0 0x1000>;
839 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
840 + clock-names = "apb_pclk", "wdog_clk";
843 + gpio0: gpio@2300000 {
844 + compatible = "fsl,qoriq-gpio";
845 + reg = <0x0 0x2300000 0x0 0x10000>;
846 + interrupts = <0 36 0x4>; /* Level high type */
850 + interrupt-controller;
851 + #interrupt-cells = <2>;
854 + gpio1: gpio@2310000 {
855 + compatible = "fsl,qoriq-gpio";
856 + reg = <0x0 0x2310000 0x0 0x10000>;
857 + interrupts = <0 36 0x4>; /* Level high type */
861 + interrupt-controller;
862 + #interrupt-cells = <2>;
865 + gpio2: gpio@2320000 {
866 + compatible = "fsl,qoriq-gpio";
867 + reg = <0x0 0x2320000 0x0 0x10000>;
868 + interrupts = <0 37 0x4>; /* Level high type */
872 + interrupt-controller;
873 + #interrupt-cells = <2>;
876 + gpio3: gpio@2330000 {
877 + compatible = "fsl,qoriq-gpio";
878 + reg = <0x0 0x2330000 0x0 0x10000>;
879 + interrupts = <0 37 0x4>; /* Level high type */
883 + interrupt-controller;
884 + #interrupt-cells = <2>;
887 + /* TODO: WRIOP (CCSR?) */
888 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
889 + compatible = "fsl,fman-memac-mdio";
890 + reg = <0x0 0x8B96000 0x0 0x1000>;
891 + device_type = "mdio"; /* TODO: is this necessary? */
892 + little-endian; /* force the driver in LE mode */
894 + /* Not necessary on the QDS, but needed on the RDB */
895 + #address-cells = <1>;
899 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
900 + compatible = "fsl,fman-memac-mdio";
901 + reg = <0x0 0x8B97000 0x0 0x1000>;
902 + device_type = "mdio"; /* TODO: is this necessary? */
903 + little-endian; /* force the driver in LE mode */
905 + #address-cells = <1>;
910 + compatible = "fsl,ifc", "simple-bus";
911 + reg = <0x0 0x2240000 0x0 0x20000>;
912 + interrupts = <0 21 0x4>; /* Level high type */
914 + #address-cells = <2>;
917 + ranges = <0 0 0x5 0x80000000 0x08000000
918 + 2 0 0x5 0x30000000 0x00010000
919 + 3 0 0x5 0x20000000 0x00010000>;
922 + esdhc: esdhc@2140000 {
923 + compatible = "fsl,ls2088a-esdhc", "fsl,ls2080a-esdhc",
925 + reg = <0x0 0x2140000 0x0 0x10000>;
926 + interrupts = <0 28 0x4>; /* Level high type */
927 + clock-frequency = <0>;
928 + voltage-ranges = <1800 1800 3300 3300>;
934 + ftm0: ftm0@2800000 {
935 + compatible = "fsl,ftm-alarm";
936 + reg = <0x0 0x2800000 0x0 0x10000>;
937 + interrupts = <0 44 4>;
940 + reset: reset@1E60000 {
941 + compatible = "fsl,ls-reset";
942 + reg = <0x0 0x1E60000 0x0 0x10000>;
945 + dspi: dspi@2100000 {
946 + compatible = "fsl,ls2088a-dspi", "fsl,ls2085a-dspi",
947 + "fsl,ls2080a-dspi";
948 + #address-cells = <1>;
950 + reg = <0x0 0x2100000 0x0 0x10000>;
951 + interrupts = <0 26 0x4>; /* Level high type */
952 + clocks = <&clockgen 4 3>;
953 + clock-names = "dspi";
954 + spi-num-chipselects = <5>;
958 + i2c0: i2c@2000000 {
959 + compatible = "fsl,vf610-i2c";
960 + #address-cells = <1>;
962 + reg = <0x0 0x2000000 0x0 0x10000>;
963 + interrupts = <0 34 0x4>; /* Level high type */
964 + clock-names = "i2c";
965 + clocks = <&clockgen 4 3>;
968 + i2c1: i2c@2010000 {
969 + compatible = "fsl,vf610-i2c";
970 + #address-cells = <1>;
972 + reg = <0x0 0x2010000 0x0 0x10000>;
973 + interrupts = <0 34 0x4>; /* Level high type */
974 + clock-names = "i2c";
975 + clocks = <&clockgen 4 3>;
978 + i2c2: i2c@2020000 {
979 + compatible = "fsl,vf610-i2c";
980 + #address-cells = <1>;
982 + reg = <0x0 0x2020000 0x0 0x10000>;
983 + interrupts = <0 35 0x4>; /* Level high type */
984 + clock-names = "i2c";
985 + clocks = <&clockgen 4 3>;
988 + i2c3: i2c@2030000 {
989 + compatible = "fsl,vf610-i2c";
990 + #address-cells = <1>;
992 + reg = <0x0 0x2030000 0x0 0x10000>;
993 + interrupts = <0 35 0x4>; /* Level high type */
994 + clock-names = "i2c";
995 + clocks = <&clockgen 4 3>;
998 + qspi: quadspi@20c0000 {
999 + compatible = "fsl,ls2088a-qspi", "fsl,ls2080a-qspi";
1000 + #address-cells = <1>;
1001 + #size-cells = <0>;
1002 + reg = <0x0 0x20c0000 0x0 0x10000>,
1003 + <0x0 0x20000000 0x0 0x10000000>;
1004 + reg-names = "QuadSPI", "QuadSPI-memory";
1005 + interrupts = <0 25 0x4>; /* Level high type */
1006 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
1007 + clock-names = "qspi_en", "qspi";
1010 + pcie1: pcie@3400000 {
1011 + compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1012 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1013 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1014 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
1015 + reg-names = "regs", "config";
1016 + interrupts = <0 108 0x4>; /* Level high type */
1017 + interrupt-names = "aer";
1018 + #address-cells = <3>;
1019 + #size-cells = <2>;
1020 + device_type = "pci";
1024 + bus-range = <0x0 0xff>;
1025 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
1026 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1027 + msi-parent = <&its>;
1028 + #interrupt-cells = <1>;
1029 + interrupt-map-mask = <0 0 0 7>;
1030 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1031 + <0000 0 0 2 &gic 0 0 0 110 4>,
1032 + <0000 0 0 3 &gic 0 0 0 111 4>,
1033 + <0000 0 0 4 &gic 0 0 0 112 4>;
1036 + pcie2: pcie@3500000 {
1037 + compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1038 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1039 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
1040 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
1041 + reg-names = "regs", "config";
1042 + interrupts = <0 113 0x4>; /* Level high type */
1043 + interrupt-names = "aer";
1044 + #address-cells = <3>;
1045 + #size-cells = <2>;
1046 + device_type = "pci";
1050 + bus-range = <0x0 0xff>;
1051 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
1052 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1053 + msi-parent = <&its>;
1054 + #interrupt-cells = <1>;
1055 + interrupt-map-mask = <0 0 0 7>;
1056 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1057 + <0000 0 0 2 &gic 0 0 0 115 4>,
1058 + <0000 0 0 3 &gic 0 0 0 116 4>,
1059 + <0000 0 0 4 &gic 0 0 0 117 4>;
1062 + pcie3: pcie@3600000 {
1063 + compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1064 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1065 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
1066 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
1067 + reg-names = "regs", "config";
1068 + interrupts = <0 118 0x4>; /* Level high type */
1069 + interrupt-names = "aer";
1070 + #address-cells = <3>;
1071 + #size-cells = <2>;
1072 + device_type = "pci";
1076 + bus-range = <0x0 0xff>;
1077 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
1078 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1079 + msi-parent = <&its>;
1080 + #interrupt-cells = <1>;
1081 + interrupt-map-mask = <0 0 0 7>;
1082 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1083 + <0000 0 0 2 &gic 0 0 0 120 4>,
1084 + <0000 0 0 3 &gic 0 0 0 121 4>,
1085 + <0000 0 0 4 &gic 0 0 0 122 4>;
1088 + pcie4: pcie@3700000 {
1089 + compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1090 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1091 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
1092 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
1093 + reg-names = "regs", "config";
1094 + interrupts = <0 123 0x4>; /* Level high type */
1095 + interrupt-names = "aer";
1096 + #address-cells = <3>;
1097 + #size-cells = <2>;
1098 + device_type = "pci";
1102 + bus-range = <0x0 0xff>;
1103 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 /* downstream I/O */
1104 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1105 + msi-parent = <&its>;
1106 + #interrupt-cells = <1>;
1107 + interrupt-map-mask = <0 0 0 7>;
1108 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1109 + <0000 0 0 2 &gic 0 0 0 125 4>,
1110 + <0000 0 0 3 &gic 0 0 0 126 4>,
1111 + <0000 0 0 4 &gic 0 0 0 127 4>;
1114 + sata0: sata@3200000 {
1115 + status = "disabled";
1116 + compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1117 + reg = <0x0 0x3200000 0x0 0x10000>;
1118 + interrupts = <0 133 0x4>; /* Level high type */
1119 + clocks = <&clockgen 4 3>;
1122 + sata1: sata@3210000 {
1123 + status = "disabled";
1124 + compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1125 + reg = <0x0 0x3210000 0x0 0x10000>;
1126 + interrupts = <0 136 0x4>; /* Level high type */
1127 + clocks = <&clockgen 4 3>;
1130 + usb0: usb3@3100000 {
1131 + status = "disabled";
1132 + compatible = "snps,dwc3";
1133 + reg = <0x0 0x3100000 0x0 0x10000>;
1134 + interrupts = <0 80 0x4>; /* Level high type */
1137 + snps,dis_rxdet_inp3_quirk;
1140 + usb1: usb3@3110000 {
1141 + status = "disabled";
1142 + compatible = "snps,dwc3";
1143 + reg = <0x0 0x3110000 0x0 0x10000>;
1144 + interrupts = <0 81 0x4>; /* Level high type */
1147 + snps,dis_rxdet_inp3_quirk;
1150 + smmu: iommu@5000000 {
1151 + compatible = "arm,mmu-500";
1152 + reg = <0 0x5000000 0 0x800000>;
1153 + #global-interrupts = <12>;
1154 + interrupts = <0 13 4>, /* global secure fault */
1155 + <0 14 4>, /* combined secure interrupt */
1156 + <0 15 4>, /* global non-secure fault */
1157 + <0 16 4>, /* combined non-secure interrupt */
1158 + /* performance counter interrupts 0-7 */
1167 + /* per context interrupt, 64 interrupts */
1232 + mmu-masters = <&fsl_mc 0x300 0>;
1236 + compatible = "arm,armv8-timer";
1237 + interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */
1238 + <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */
1239 + <1 11 0x1>, /* Virtual PPI, edge triggered */
1240 + <1 10 0x1>; /* Hypervisor PPI, edge triggered */
1242 + fsl,erratum-a008585;
1245 + fsl_mc: fsl-mc@80c000000 {
1246 + compatible = "fsl,qoriq-mc";
1247 + #stream-id-cells = <2>;
1248 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
1249 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
1250 + msi-parent = <&its>;
1251 + #address-cells = <3>;
1252 + #size-cells = <1>;
1255 + * Region type 0x0 - MC portals
1256 + * Region type 0x1 - QBMAN portals
1258 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1259 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1262 + * Define the maximum number of MACs present on the SoC.
1263 + * They won't necessarily be all probed, since the
1264 + * Data Path Layout file and the MC firmware can put fewer
1265 + * actual DPMAC objects on the MC bus.
1268 + #address-cells = <1>;
1269 + #size-cells = <0>;
1272 + compatible = "fsl,qoriq-mc-dpmac";
1276 + compatible = "fsl,qoriq-mc-dpmac";
1280 + compatible = "fsl,qoriq-mc-dpmac";
1284 + compatible = "fsl,qoriq-mc-dpmac";
1288 + compatible = "fsl,qoriq-mc-dpmac";
1292 + compatible = "fsl,qoriq-mc-dpmac";
1296 + compatible = "fsl,qoriq-mc-dpmac";
1300 + compatible = "fsl,qoriq-mc-dpmac";
1304 + compatible = "fsl,qoriq-mc-dpmac";
1307 + dpmac10: dpmac@10 {
1308 + compatible = "fsl,qoriq-mc-dpmac";
1311 + dpmac11: dpmac@11 {
1312 + compatible = "fsl,qoriq-mc-dpmac";
1315 + dpmac12: dpmac@12 {
1316 + compatible = "fsl,qoriq-mc-dpmac";
1319 + dpmac13: dpmac@13 {
1320 + compatible = "fsl,qoriq-mc-dpmac";
1323 + dpmac14: dpmac@14 {
1324 + compatible = "fsl,qoriq-mc-dpmac";
1327 + dpmac15: dpmac@15 {
1328 + compatible = "fsl,qoriq-mc-dpmac";
1331 + dpmac16: dpmac@16 {
1332 + compatible = "fsl,qoriq-mc-dpmac";
1339 + compatible = "arm,ccn-504";
1340 + reg = <0x0 0x04000000 0x0 0x01000000>;
1341 + interrupts = <0 12 4>;
1345 + device_type = "memory";
1346 + reg = <0x00000000 0x80000000 0 0x80000000>;
1347 + /* DRAM space 1 - 2 GB DRAM */