1 From 45ba5bb2bdc9462fe5998aeb75e2c7e33b56c9fb Mon Sep 17 00:00:00 2001
2 From: Zhao Qiang <qiang.zhao@nxp.com>
3 Date: Mon, 7 Nov 2016 10:23:52 +0800
4 Subject: [PATCH 227/238] ls2088a/dts: add ls2088a dts
6 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
8 arch/arm64/boot/dts/freescale/Makefile | 2 +
9 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 241 ++++++
10 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 207 +++++
11 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 854 +++++++++++++++++++++
12 4 files changed, 1304 insertions(+)
13 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
14 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
15 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
17 --- a/arch/arm64/boot/dts/freescale/Makefile
18 +++ b/arch/arm64/boot/dts/freescale/Makefile
19 @@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
20 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
21 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
22 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
23 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
24 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
27 subdir-y := $(dts-dirs)
29 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
32 + * Device Tree file for Freescale LS2080a QDS Board
34 + * Copyright (C) 2016, Freescale Semiconductor
36 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
38 + * This file is licensed under the terms of the GNU General Public
39 + * License version 2. This program is licensed "as is" without any
40 + * warranty of any kind, whether express or implied.
45 +#include "fsl-ls2088a.dtsi"
48 + model = "Freescale Layerscape 2088a QDS Board";
49 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
58 + #address-cells = <2>;
60 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
61 + 0x2 0x0 0x5 0x30000000 0x00010000
62 + 0x3 0x0 0x5 0x20000000 0x00010000>;
65 + #address-cells = <1>;
67 + compatible = "cfi-flash";
68 + reg = <0x0 0x0 0x8000000>;
74 + compatible = "fsl,ifc-nand";
75 + reg = <0x2 0x0 0x10000>;
79 + reg = <0x3 0x0 0x10000>;
80 + compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
92 + compatible = "nxp,pca9547";
94 + #address-cells = <1>;
97 + #address-cells = <1>;
101 + compatible = "dallas,ds3232";
107 + #address-cells = <1>;
112 + compatible = "ti,ina220";
114 + shunt-resistor = <500>;
117 + compatible = "ti,ina220";
119 + shunt-resistor = <1000>;
124 + #address-cells = <1>;
129 + compatible = "adi,adt7461";
137 + status = "disabled";
141 + status = "disabled";
145 + status = "disabled";
150 + dflash0: n25q128a {
151 + #address-cells = <1>;
153 + compatible = "st,m25p80";
154 + spi-max-frequency = <3000000>;
157 + dflash1: sst25wf040b {
158 + #address-cells = <1>;
160 + compatible = "st,m25p80";
161 + spi-max-frequency = <3000000>;
165 + #address-cells = <1>;
167 + compatible = "st,m25p80";
168 + spi-max-frequency = <3000000>;
175 + qflash0: s25fs256s1@0 {
176 + #address-cells = <1>;
178 + compatible = "st,m25p80";
179 + spi-max-frequency = <20000000>;
184 + qflash2: s25fs256s1@2 {
185 + #address-cells = <1>;
187 + compatible = "st,m25p80";
188 + spi-max-frequency = <20000000>;
211 + boardctrl: board-control@3,0 {
212 + #address-cells = <1>;
214 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
215 + reg = <3 0 0x300>; /* TODO check address */
216 + ranges = <0 3 0 0x300>;
219 + compatible = "mdio-mux-mmioreg", "mdio-mux";
220 + mdio-parent-bus = <&emdio1>;
221 + reg = <0x54 1>; /* BRDCFG4 */
222 + mux-mask = <0xe0>; /* EMI1_MDIO */
224 + #address-cells=<1>;
227 + /* Child MDIO buses, one for each riser card:
228 + reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
230 + VSC8234 PHYs on the riser cards.
233 + mdio_mux3: mdio@60 {
235 + #address-cells = <1>;
238 + mdio0_phy12: mdio_phy0@1c {
240 + phy-connection-type = "sgmii";
242 + mdio0_phy13: mdio_phy1@1d {
244 + phy-connection-type = "sgmii";
246 + mdio0_phy14: mdio_phy2@1e {
248 + phy-connection-type = "sgmii";
250 + mdio0_phy15: mdio_phy3@1f {
252 + phy-connection-type = "sgmii";
259 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
261 + phy-handle = <&mdio0_phy12>;
264 + phy-handle = <&mdio0_phy13>;
267 + phy-handle = <&mdio0_phy14>;
270 + phy-handle = <&mdio0_phy15>;
273 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
276 + * Device Tree file for Freescale LS2080a RDB board
278 + * Copyright (C) 2015, Freescale Semiconductor
280 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
282 + * This file is licensed under the terms of the GNU General Public
283 + * License version 2. This program is licensed "as is" without any
284 + * warranty of any kind, whether express or implied.
289 +#include "fsl-ls2088a.dtsi"
292 + model = "Freescale Layerscape 2088a RDB Board";
293 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
302 + #address-cells = <2>;
304 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
305 + 0x2 0x0 0x5 0x30000000 0x00010000
306 + 0x3 0x0 0x5 0x20000000 0x00010000>;
309 + #address-cells = <1>;
311 + compatible = "cfi-flash";
312 + reg = <0x0 0x0 0x8000000>;
314 + device-width = <1>;
318 + compatible = "fsl,ifc-nand";
319 + reg = <0x2 0x0 0x10000>;
323 + reg = <0x3 0x0 0x10000>;
324 + compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
336 + compatible = "nxp,pca9547";
338 + #address-cells = <1>;
340 + i2c-mux-never-disable;
342 + #address-cells = <1>;
346 + compatible = "dallas,ds3232";
352 + #address-cells = <1>;
357 + compatible = "adi,adt7461";
365 + status = "disabled";
369 + status = "disabled";
373 + status = "disabled";
378 + dflash0: n25q512a {
379 + #address-cells = <1>;
381 + compatible = "st,m25p80";
382 + spi-max-frequency = <3000000>;
388 + status = "disabled";
409 + mdio1_phy1: emdio1_phy@1 {
411 + phy-connection-type = "xfi";
413 + mdio1_phy2: emdio1_phy@2 {
415 + phy-connection-type = "xfi";
417 + mdio1_phy3: emdio1_phy@3 {
419 + phy-connection-type = "xfi";
421 + mdio1_phy4: emdio1_phy@4 {
423 + phy-connection-type = "xfi";
429 + mdio2_phy1: emdio2_phy@1 {
430 + compatible = "ethernet-phy-ieee802.3-c45";
431 + interrupts = <0 1 0x4>; /* Level high type */
433 + phy-connection-type = "xfi";
435 + mdio2_phy2: emdio2_phy@2 {
436 + compatible = "ethernet-phy-ieee802.3-c45";
437 + interrupts = <0 2 0x4>; /* Level high type */
439 + phy-connection-type = "xfi";
441 + mdio2_phy3: emdio2_phy@3 {
442 + compatible = "ethernet-phy-ieee802.3-c45";
443 + interrupts = <0 4 0x4>; /* Level high type */
445 + phy-connection-type = "xfi";
447 + mdio2_phy4: emdio2_phy@4 {
448 + compatible = "ethernet-phy-ieee802.3-c45";
449 + interrupts = <0 5 0x4>; /* Level high type */
451 + phy-connection-type = "xfi";
455 +/* Update DPMAC connections to external PHYs, under the assumption of
456 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
459 + phy-handle = <&mdio1_phy1>;
462 + phy-handle = <&mdio1_phy2>;
465 + phy-handle = <&mdio1_phy3>;
468 + phy-handle = <&mdio1_phy4>;
471 + phy-handle = <&mdio2_phy1>;
474 + phy-handle = <&mdio2_phy2>;
477 + phy-handle = <&mdio2_phy3>;
480 + phy-handle = <&mdio2_phy4>;
483 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
486 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
488 + * Copyright (C) 2016, Freescale Semiconductor
490 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
492 + * This file is dual-licensed: you can use it either under the terms
493 + * of the GPLv2 or the X11 license, at your option. Note that this dual
494 + * licensing only applies to this file, and not this project as a
497 + * a) This library is free software; you can redistribute it and/or
498 + * modify it under the terms of the GNU General Public License as
499 + * published by the Free Software Foundation; either version 2 of the
500 + * License, or (at your option) any later version.
502 + * This library is distributed in the hope that it will be useful,
503 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
504 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
505 + * GNU General Public License for more details.
507 + * Or, alternatively,
509 + * b) Permission is hereby granted, free of charge, to any person
510 + * obtaining a copy of this software and associated documentation
511 + * files (the "Software"), to deal in the Software without
512 + * restriction, including without limitation the rights to use,
513 + * copy, modify, merge, publish, distribute, sublicense, and/or
514 + * sell copies of the Software, and to permit persons to whom the
515 + * Software is furnished to do so, subject to the following
518 + * The above copyright notice and this permission notice shall be
519 + * included in all copies or substantial portions of the Software.
521 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
522 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
523 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
524 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
525 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
526 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
527 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
528 + * OTHER DEALINGS IN THE SOFTWARE.
531 +#include <dt-bindings/thermal/thermal.h>
533 +/memreserve/ 0x80000000 0x00010000;
536 + compatible = "fsl,ls2088a";
537 + interrupt-parent = <&gic>;
538 + #address-cells = <2>;
542 + #address-cells = <2>;
546 + device_type = "cpu";
547 + compatible = "arm,cortex-a72";
549 + clocks = <&clockgen 1 0>;
550 + #cooling-cells = <2>;
551 + cpu-idle-states = <&CPU_PW20>;
555 + device_type = "cpu";
556 + compatible = "arm,cortex-a72";
558 + clocks = <&clockgen 1 0>;
559 + cpu-idle-states = <&CPU_PW20>;
563 + device_type = "cpu";
564 + compatible = "arm,cortex-a72";
566 + clocks = <&clockgen 1 1>;
567 + #cooling-cells = <2>;
568 + cpu-idle-states = <&CPU_PW20>;
572 + device_type = "cpu";
573 + compatible = "arm,cortex-a72";
575 + clocks = <&clockgen 1 1>;
576 + cpu-idle-states = <&CPU_PW20>;
580 + device_type = "cpu";
581 + compatible = "arm,cortex-a72";
583 + clocks = <&clockgen 1 2>;
584 + #cooling-cells = <2>;
585 + cpu-idle-states = <&CPU_PW20>;
589 + device_type = "cpu";
590 + compatible = "arm,cortex-a72";
592 + clocks = <&clockgen 1 2>;
593 + cpu-idle-states = <&CPU_PW20>;
597 + device_type = "cpu";
598 + compatible = "arm,cortex-a72";
600 + clocks = <&clockgen 1 3>;
601 + #cooling-cells = <2>;
602 + cpu-idle-states = <&CPU_PW20>;
606 + device_type = "cpu";
607 + compatible = "arm,cortex-a72";
609 + clocks = <&clockgen 1 3>;
610 + cpu-idle-states = <&CPU_PW20>;
615 + compatible = "arm,armv8-pmuv3";
616 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
620 + entry-method = "arm,psci";
622 + CPU_PW20: cpu-pw20 {
623 + compatible = "arm,idle-state";
624 + idle-state-name = "PW20";
625 + arm,psci-suspend-param = <0x00010000>;
626 + entry-latency-us = <2000>;
627 + exit-latency-us = <2000>;
628 + min-residency-us = <6000>;
632 + gic: interrupt-controller@6000000 {
633 + compatible = "arm,gic-v3";
634 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
635 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
636 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
637 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
638 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
639 + #interrupt-cells = <3>;
640 + #address-cells = <2>;
643 + interrupt-controller;
644 + interrupts = <1 9 0x4>;
646 + its: gic-its@6020000 {
647 + compatible = "arm,gic-v3-its";
649 + reg = <0x0 0x6020000 0 0x20000>;
654 + compatible = "fixed-clock";
655 + #clock-cells = <0>;
656 + clock-frequency = <100000000>;
657 + clock-output-names = "sysclk";
660 + clockgen: clocking@1300000 {
661 + compatible = "fsl,ls2088a-clockgen";
662 + reg = <0 0x1300000 0 0xa0000>;
663 + #clock-cells = <2>;
664 + clocks = <&sysclk>;
668 + compatible = "fsl,qoriq-tmu", "fsl,ls2080a-tmu", "fsl,ls2088a-tmu";
669 + reg = <0x0 0x1f80000 0x0 0x10000>;
670 + interrupts = <0 23 0x4>;
671 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
672 + fsl,tmu-calibration = <0x00000000 0x00000026
673 + 0x00000001 0x0000002d
674 + 0x00000002 0x00000032
675 + 0x00000003 0x00000039
676 + 0x00000004 0x0000003f
677 + 0x00000005 0x00000046
678 + 0x00000006 0x0000004d
679 + 0x00000007 0x00000054
680 + 0x00000008 0x0000005a
681 + 0x00000009 0x00000061
682 + 0x0000000a 0x0000006a
683 + 0x0000000b 0x00000071
685 + 0x00010000 0x00000025
686 + 0x00010001 0x0000002c
687 + 0x00010002 0x00000035
688 + 0x00010003 0x0000003d
689 + 0x00010004 0x00000045
690 + 0x00010005 0x0000004e
691 + 0x00010006 0x00000057
692 + 0x00010007 0x00000061
693 + 0x00010008 0x0000006b
694 + 0x00010009 0x00000076
696 + 0x00020000 0x00000029
697 + 0x00020001 0x00000033
698 + 0x00020002 0x0000003d
699 + 0x00020003 0x00000049
700 + 0x00020004 0x00000056
701 + 0x00020005 0x00000061
702 + 0x00020006 0x0000006d
704 + 0x00030000 0x00000021
705 + 0x00030001 0x0000002a
706 + 0x00030002 0x0000003c
707 + 0x00030003 0x0000004e>;
709 + #thermal-sensor-cells = <1>;
713 + cpu_thermal: cpu-thermal {
714 + polling-delay-passive = <1000>;
715 + polling-delay = <5000>;
717 + thermal-sensors = <&tmu 4>;
720 + cpu_alert: cpu-alert {
721 + temperature = <75000>;
722 + hysteresis = <2000>;
725 + cpu_crit: cpu-crit {
726 + temperature = <85000>;
727 + hysteresis = <2000>;
734 + trip = <&cpu_alert>;
736 + <&cpu0 THERMAL_NO_LIMIT
740 + trip = <&cpu_alert>;
742 + <&cpu2 THERMAL_NO_LIMIT
746 + trip = <&cpu_alert>;
748 + <&cpu4 THERMAL_NO_LIMIT
752 + trip = <&cpu_alert>;
754 + <&cpu6 THERMAL_NO_LIMIT
761 + serial0: serial@21c0500 {
762 + device_type = "serial";
763 + compatible = "fsl,ns16550", "ns16550a";
764 + reg = <0x0 0x21c0500 0x0 0x100>;
765 + clocks = <&clockgen 4 3>;
766 + interrupts = <0 32 0x4>; /* Level high type */
769 + serial1: serial@21c0600 {
770 + device_type = "serial";
771 + compatible = "fsl,ns16550", "ns16550a";
772 + reg = <0x0 0x21c0600 0x0 0x100>;
773 + clocks = <&clockgen 4 3>;
774 + interrupts = <0 32 0x4>; /* Level high type */
776 + cluster1_core0_watchdog: wdt@c000000 {
777 + compatible = "arm,sp805-wdt", "arm,primecell";
778 + reg = <0x0 0xc000000 0x0 0x1000>;
779 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
780 + clock-names = "apb_pclk", "wdog_clk";
783 + cluster1_core1_watchdog: wdt@c010000 {
784 + compatible = "arm,sp805-wdt", "arm,primecell";
785 + reg = <0x0 0xc010000 0x0 0x1000>;
786 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
787 + clock-names = "apb_pclk", "wdog_clk";
790 + cluster2_core0_watchdog: wdt@c100000 {
791 + compatible = "arm,sp805-wdt", "arm,primecell";
792 + reg = <0x0 0xc100000 0x0 0x1000>;
793 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
794 + clock-names = "apb_pclk", "wdog_clk";
797 + cluster2_core1_watchdog: wdt@c110000 {
798 + compatible = "arm,sp805-wdt", "arm,primecell";
799 + reg = <0x0 0xc110000 0x0 0x1000>;
800 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
801 + clock-names = "apb_pclk", "wdog_clk";
804 + cluster3_core0_watchdog: wdt@c200000 {
805 + compatible = "arm,sp805-wdt", "arm,primecell";
806 + reg = <0x0 0xc200000 0x0 0x1000>;
807 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
808 + clock-names = "apb_pclk", "wdog_clk";
811 + cluster3_core1_watchdog: wdt@c210000 {
812 + compatible = "arm,sp805-wdt", "arm,primecell";
813 + reg = <0x0 0xc210000 0x0 0x1000>;
814 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
815 + clock-names = "apb_pclk", "wdog_clk";
818 + cluster4_core0_watchdog: wdt@c300000 {
819 + compatible = "arm,sp805-wdt", "arm,primecell";
820 + reg = <0x0 0xc300000 0x0 0x1000>;
821 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
822 + clock-names = "apb_pclk", "wdog_clk";
825 + cluster4_core1_watchdog: wdt@c310000 {
826 + compatible = "arm,sp805-wdt", "arm,primecell";
827 + reg = <0x0 0xc310000 0x0 0x1000>;
828 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
829 + clock-names = "apb_pclk", "wdog_clk";
832 + gpio0: gpio@2300000 {
833 + compatible = "fsl,qoriq-gpio";
834 + reg = <0x0 0x2300000 0x0 0x10000>;
835 + interrupts = <0 36 0x4>; /* Level high type */
839 + interrupt-controller;
840 + #interrupt-cells = <2>;
843 + gpio1: gpio@2310000 {
844 + compatible = "fsl,qoriq-gpio";
845 + reg = <0x0 0x2310000 0x0 0x10000>;
846 + interrupts = <0 36 0x4>; /* Level high type */
850 + interrupt-controller;
851 + #interrupt-cells = <2>;
854 + gpio2: gpio@2320000 {
855 + compatible = "fsl,qoriq-gpio";
856 + reg = <0x0 0x2320000 0x0 0x10000>;
857 + interrupts = <0 37 0x4>; /* Level high type */
861 + interrupt-controller;
862 + #interrupt-cells = <2>;
865 + gpio3: gpio@2330000 {
866 + compatible = "fsl,qoriq-gpio";
867 + reg = <0x0 0x2330000 0x0 0x10000>;
868 + interrupts = <0 37 0x4>; /* Level high type */
872 + interrupt-controller;
873 + #interrupt-cells = <2>;
876 + /* TODO: WRIOP (CCSR?) */
877 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
878 + compatible = "fsl,fman-memac-mdio";
879 + reg = <0x0 0x8B96000 0x0 0x1000>;
880 + device_type = "mdio"; /* TODO: is this necessary? */
881 + little-endian; /* force the driver in LE mode */
883 + /* Not necessary on the QDS, but needed on the RDB */
884 + #address-cells = <1>;
888 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
889 + compatible = "fsl,fman-memac-mdio";
890 + reg = <0x0 0x8B97000 0x0 0x1000>;
891 + device_type = "mdio"; /* TODO: is this necessary? */
892 + little-endian; /* force the driver in LE mode */
894 + #address-cells = <1>;
899 + compatible = "fsl,ifc", "simple-bus";
900 + reg = <0x0 0x2240000 0x0 0x20000>;
901 + interrupts = <0 21 0x4>; /* Level high type */
903 + #address-cells = <2>;
906 + ranges = <0 0 0x5 0x80000000 0x08000000
907 + 2 0 0x5 0x30000000 0x00010000
908 + 3 0 0x5 0x20000000 0x00010000>;
911 + esdhc: esdhc@2140000 {
912 + compatible = "fsl,ls2088a-esdhc", "fsl,ls2080a-esdhc",
914 + reg = <0x0 0x2140000 0x0 0x10000>;
915 + interrupts = <0 28 0x4>; /* Level high type */
916 + clock-frequency = <0>;
917 + voltage-ranges = <1800 1800 3300 3300>;
923 + ftm0: ftm0@2800000 {
924 + compatible = "fsl,ftm-alarm";
925 + reg = <0x0 0x2800000 0x0 0x10000>;
926 + interrupts = <0 44 4>;
929 + reset: reset@1E60000 {
930 + compatible = "fsl,ls-reset";
931 + reg = <0x0 0x1E60000 0x0 0x10000>;
934 + dspi: dspi@2100000 {
935 + compatible = "fsl,ls2088a-dspi", "fsl,ls2085a-dspi",
936 + "fsl,ls2080a-dspi";
937 + #address-cells = <1>;
939 + reg = <0x0 0x2100000 0x0 0x10000>;
940 + interrupts = <0 26 0x4>; /* Level high type */
941 + clocks = <&clockgen 4 3>;
942 + clock-names = "dspi";
943 + spi-num-chipselects = <5>;
947 + i2c0: i2c@2000000 {
948 + compatible = "fsl,vf610-i2c";
949 + #address-cells = <1>;
951 + reg = <0x0 0x2000000 0x0 0x10000>;
952 + interrupts = <0 34 0x4>; /* Level high type */
953 + clock-names = "i2c";
954 + clocks = <&clockgen 4 3>;
957 + i2c1: i2c@2010000 {
958 + compatible = "fsl,vf610-i2c";
959 + #address-cells = <1>;
961 + reg = <0x0 0x2010000 0x0 0x10000>;
962 + interrupts = <0 34 0x4>; /* Level high type */
963 + clock-names = "i2c";
964 + clocks = <&clockgen 4 3>;
967 + i2c2: i2c@2020000 {
968 + compatible = "fsl,vf610-i2c";
969 + #address-cells = <1>;
971 + reg = <0x0 0x2020000 0x0 0x10000>;
972 + interrupts = <0 35 0x4>; /* Level high type */
973 + clock-names = "i2c";
974 + clocks = <&clockgen 4 3>;
977 + i2c3: i2c@2030000 {
978 + compatible = "fsl,vf610-i2c";
979 + #address-cells = <1>;
981 + reg = <0x0 0x2030000 0x0 0x10000>;
982 + interrupts = <0 35 0x4>; /* Level high type */
983 + clock-names = "i2c";
984 + clocks = <&clockgen 4 3>;
987 + qspi: quadspi@20c0000 {
988 + compatible = "fsl,ls2088a-qspi", "fsl,ls2080a-qspi";
989 + #address-cells = <1>;
991 + reg = <0x0 0x20c0000 0x0 0x10000>,
992 + <0x0 0x20000000 0x0 0x10000000>;
993 + reg-names = "QuadSPI", "QuadSPI-memory";
994 + interrupts = <0 25 0x4>; /* Level high type */
995 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
996 + clock-names = "qspi_en", "qspi";
999 + pcie1: pcie@3400000 {
1000 + compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1001 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1002 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1003 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
1004 + reg-names = "regs", "config";
1005 + interrupts = <0 108 0x4>; /* Level high type */
1006 + interrupt-names = "aer";
1007 + #address-cells = <3>;
1008 + #size-cells = <2>;
1009 + device_type = "pci";
1013 + bus-range = <0x0 0xff>;
1014 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
1015 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1016 + msi-parent = <&its>;
1017 + #interrupt-cells = <1>;
1018 + interrupt-map-mask = <0 0 0 7>;
1019 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1020 + <0000 0 0 2 &gic 0 0 0 110 4>,
1021 + <0000 0 0 3 &gic 0 0 0 111 4>,
1022 + <0000 0 0 4 &gic 0 0 0 112 4>;
1025 + pcie2: pcie@3500000 {
1026 + compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1027 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1028 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
1029 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
1030 + reg-names = "regs", "config";
1031 + interrupts = <0 113 0x4>; /* Level high type */
1032 + interrupt-names = "aer";
1033 + #address-cells = <3>;
1034 + #size-cells = <2>;
1035 + device_type = "pci";
1039 + bus-range = <0x0 0xff>;
1040 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
1041 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1042 + msi-parent = <&its>;
1043 + #interrupt-cells = <1>;
1044 + interrupt-map-mask = <0 0 0 7>;
1045 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1046 + <0000 0 0 2 &gic 0 0 0 115 4>,
1047 + <0000 0 0 3 &gic 0 0 0 116 4>,
1048 + <0000 0 0 4 &gic 0 0 0 117 4>;
1051 + pcie3: pcie@3600000 {
1052 + compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
1053 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1054 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
1055 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
1056 + reg-names = "regs", "config";
1057 + interrupts = <0 118 0x4>; /* Level high type */
1058 + interrupt-names = "aer";
1059 + #address-cells = <3>;
1060 + #size-cells = <2>;
1061 + device_type = "pci";
1065 + bus-range = <0x0 0xff>;
1066 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
1067 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1068 + msi-parent = <&its>;
1069 + #interrupt-cells = <1>;
1070 + interrupt-map-mask = <0 0 0 7>;
1071 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1072 + <0000 0 0 2 &gic 0 0 0 120 4>,
1073 + <0000 0 0 3 &gic 0 0 0 121 4>,
1074 + <0000 0 0 4 &gic 0 0 0 122 4>;
1077 + pcie4: pcie@3700000 {
1078 + compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
1079 + "fsl,ls2085a-pcie", "snps,dw-pcie";
1080 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
1081 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
1082 + reg-names = "regs", "config";
1083 + interrupts = <0 123 0x4>; /* Level high type */
1084 + interrupt-names = "aer";
1085 + #address-cells = <3>;
1086 + #size-cells = <2>;
1087 + device_type = "pci";
1091 + bus-range = <0x0 0xff>;
1092 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 /* downstream I/O */
1093 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1094 + msi-parent = <&its>;
1095 + #interrupt-cells = <1>;
1096 + interrupt-map-mask = <0 0 0 7>;
1097 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1098 + <0000 0 0 2 &gic 0 0 0 125 4>,
1099 + <0000 0 0 3 &gic 0 0 0 126 4>,
1100 + <0000 0 0 4 &gic 0 0 0 127 4>;
1103 + sata0: sata@3200000 {
1104 + status = "disabled";
1105 + compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1106 + reg = <0x0 0x3200000 0x0 0x10000>;
1107 + interrupts = <0 133 0x4>; /* Level high type */
1108 + clocks = <&clockgen 4 3>;
1111 + sata1: sata@3210000 {
1112 + status = "disabled";
1113 + compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
1114 + reg = <0x0 0x3210000 0x0 0x10000>;
1115 + interrupts = <0 136 0x4>; /* Level high type */
1116 + clocks = <&clockgen 4 3>;
1119 + usb0: usb3@3100000 {
1120 + status = "disabled";
1121 + compatible = "snps,dwc3";
1122 + reg = <0x0 0x3100000 0x0 0x10000>;
1123 + interrupts = <0 80 0x4>; /* Level high type */
1126 + snps,dis_rxdet_inp3_quirk;
1129 + usb1: usb3@3110000 {
1130 + status = "disabled";
1131 + compatible = "snps,dwc3";
1132 + reg = <0x0 0x3110000 0x0 0x10000>;
1133 + interrupts = <0 81 0x4>; /* Level high type */
1136 + snps,dis_rxdet_inp3_quirk;
1139 + smmu: iommu@5000000 {
1140 + compatible = "arm,mmu-500";
1141 + reg = <0 0x5000000 0 0x800000>;
1142 + #global-interrupts = <12>;
1143 + interrupts = <0 13 4>, /* global secure fault */
1144 + <0 14 4>, /* combined secure interrupt */
1145 + <0 15 4>, /* global non-secure fault */
1146 + <0 16 4>, /* combined non-secure interrupt */
1147 + /* performance counter interrupts 0-7 */
1156 + /* per context interrupt, 64 interrupts */
1221 + mmu-masters = <&fsl_mc 0x300 0>;
1225 + compatible = "arm,armv8-timer";
1226 + interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */
1227 + <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */
1228 + <1 11 0x1>, /* Virtual PPI, edge triggered */
1229 + <1 10 0x1>; /* Hypervisor PPI, edge triggered */
1231 + fsl,erratum-a008585;
1234 + fsl_mc: fsl-mc@80c000000 {
1235 + compatible = "fsl,qoriq-mc";
1236 + #stream-id-cells = <2>;
1237 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
1238 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
1239 + msi-parent = <&its>;
1240 + #address-cells = <3>;
1241 + #size-cells = <1>;
1244 + * Region type 0x0 - MC portals
1245 + * Region type 0x1 - QBMAN portals
1247 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1248 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1251 + * Define the maximum number of MACs present on the SoC.
1252 + * They won't necessarily be all probed, since the
1253 + * Data Path Layout file and the MC firmware can put fewer
1254 + * actual DPMAC objects on the MC bus.
1257 + #address-cells = <1>;
1258 + #size-cells = <0>;
1261 + compatible = "fsl,qoriq-mc-dpmac";
1265 + compatible = "fsl,qoriq-mc-dpmac";
1269 + compatible = "fsl,qoriq-mc-dpmac";
1273 + compatible = "fsl,qoriq-mc-dpmac";
1277 + compatible = "fsl,qoriq-mc-dpmac";
1281 + compatible = "fsl,qoriq-mc-dpmac";
1285 + compatible = "fsl,qoriq-mc-dpmac";
1289 + compatible = "fsl,qoriq-mc-dpmac";
1293 + compatible = "fsl,qoriq-mc-dpmac";
1296 + dpmac10: dpmac@10 {
1297 + compatible = "fsl,qoriq-mc-dpmac";
1300 + dpmac11: dpmac@11 {
1301 + compatible = "fsl,qoriq-mc-dpmac";
1304 + dpmac12: dpmac@12 {
1305 + compatible = "fsl,qoriq-mc-dpmac";
1308 + dpmac13: dpmac@13 {
1309 + compatible = "fsl,qoriq-mc-dpmac";
1312 + dpmac14: dpmac@14 {
1313 + compatible = "fsl,qoriq-mc-dpmac";
1316 + dpmac15: dpmac@15 {
1317 + compatible = "fsl,qoriq-mc-dpmac";
1320 + dpmac16: dpmac@16 {
1321 + compatible = "fsl,qoriq-mc-dpmac";
1328 + compatible = "arm,ccn-504";
1329 + reg = <0x0 0x04000000 0x0 0x01000000>;
1330 + interrupts = <0 12 4>;
1334 + device_type = "memory";
1335 + reg = <0x00000000 0x80000000 0 0x80000000>;
1336 + /* DRAM space 1 - 2 GB DRAM */