1 From 1569c166572f9576c6726472b5a726a1a56900bd Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Thu, 16 Feb 2017 18:00:14 +0800
4 Subject: [PATCH] arm64: dts: ls1046a: update MSI dts node
6 Update MSI dts node according to below patchwork patch.
8 arm64: dts: ls1046a: add MSI dts node
9 https://patchwork.kernel.org/patch/9520299
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
13 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 58 +++++++++++++-------------
14 1 file changed, 30 insertions(+), 28 deletions(-)
16 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
17 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
19 * OTHER DEALINGS IN THE SOFTWARE.
22 +#include <dt-bindings/interrupt-controller/arm-gic.h>
25 compatible = "fsl,ls1046a";
26 interrupt-parent = <&gic>;
31 - msi: msi-controller@1580000 {
32 + msi1: msi-controller@1580000 {
33 compatible = "fsl,ls1046a-msi";
34 - #address-cells = <2>;
38 + reg = <0x0 0x1580000 0x0 0x10000>;
39 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
40 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
41 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
42 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
46 - reg = <0x0 0x1580000 0x0 0x10000>;
47 - interrupts = <0 116 0x4>,
53 - reg = <0x0 0x1590000 0x0 0x10000>;
54 - interrupts = <0 126 0x4>,
60 - reg = <0x0 0x15a0000 0x0 0x10000>;
61 - interrupts = <0 160 0x4>,
66 + msi2: msi-controller@1590000 {
67 + compatible = "fsl,ls1046a-msi";
69 + reg = <0x0 0x1590000 0x0 0x10000>;
70 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
71 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
72 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
73 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
76 + msi3: msi-controller@15a0000 {
77 + compatible = "fsl,ls1046a-msi";
79 + reg = <0x0 0x15a0000 0x0 0x10000>;
80 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
81 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
82 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
83 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
88 bus-range = <0x0 0xff>;
89 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
90 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
91 - msi-parent = <&msi>;
92 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
93 #interrupt-cells = <1>;
94 interrupt-map-mask = <0 0 0 7>;
95 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
97 bus-range = <0x0 0xff>;
98 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
99 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
100 - msi-parent = <&msi>;
101 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
102 #interrupt-cells = <1>;
103 interrupt-map-mask = <0 0 0 7>;
104 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
106 bus-range = <0x0 0xff>;
107 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
108 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
109 - msi-parent = <&msi>;
110 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
111 #interrupt-cells = <1>;
112 interrupt-map-mask = <0 0 0 7>;
113 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,