1 From c2d0a12b5cfa61e43494483f5d1ee466b4998830 Mon Sep 17 00:00:00 2001
2 From: Liu Gang <Gang.Liu@nxp.com>
3 Date: Thu, 14 Jan 2016 19:48:09 +0800
4 Subject: [PATCH 42/70] drivers/gpio: Port gpio driver to support layerscape
7 Layerscape has the same ip block/controller as
8 GPIO on powerpc platform(MPC8XXX).
10 So use portable i/o accessors, as in_be32/out_be32
11 accessors are Power architecture specific whereas
12 ioread32/iowrite32 and ioread32be/iowrite32be are
13 available in other architectures.
15 Layerscape GPIO controller's registers may be big
16 or little endian, so the code needs to get the
17 endian property from DTB, then make additional
18 functions to fit right register read/write
21 Currently the code can support ls2080a GPIO with
22 little endian registers. And it can also work well
23 on other layerscape platform with big endian GPIO
26 Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
28 drivers/gpio/Kconfig | 7 ++--
29 drivers/gpio/gpio-mpc8xxx.c | 87 +++++++++++++++++++++++++++++++------------
30 2 files changed, 68 insertions(+), 26 deletions(-)
32 --- a/drivers/gpio/Kconfig
33 +++ b/drivers/gpio/Kconfig
34 @@ -282,12 +282,13 @@ config GPIO_MPC5200
35 depends on PPC_MPC52xx
38 - bool "MPC512x/MPC8xxx GPIO support"
39 + bool "MPC512x/MPC8xxx/QorIQ GPIO support"
40 depends on PPC_MPC512x || PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || \
41 - FSL_SOC_BOOKE || PPC_86xx
42 + FSL_SOC_BOOKE || PPC_86xx || ARCH_LAYERSCAPE || ARM || \
45 Say Y here if you're going to use hardware that connects to the
46 - MPC512x/831x/834x/837x/8572/8610 GPIOs.
47 + MPC512x/831x/834x/837x/8572/8610/QorIQ GPIOs.
51 --- a/drivers/gpio/gpio-mpc8xxx.c
52 +++ b/drivers/gpio/gpio-mpc8xxx.c
55 - * GPIOs on MPC512x/8349/8572/8610 and compatible
56 + * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible
58 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
61 #include <linux/gpio.h>
62 #include <linux/slab.h>
63 #include <linux/irq.h>
64 +#include <linux/irqdomain.h>
66 #define MPC8XXX_GPIO_PINS 32
68 @@ -44,6 +45,27 @@ struct mpc8xxx_gpio_chip {
69 const void *of_dev_id_data;
72 +static bool gpio_little_endian;
73 +static inline u32 gpio_in32(void __iomem *addr)
77 + if (gpio_little_endian)
78 + val = ioread32(addr);
80 + val = ioread32be(addr);
85 +static inline void gpio_out32(u32 val, void __iomem *addr)
87 + if (gpio_little_endian)
88 + iowrite32(val, addr);
90 + iowrite32be(val, addr);
93 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
95 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
96 @@ -59,9 +81,17 @@ static void mpc8xxx_gpio_save_regs(struc
98 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
100 - mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
101 + mpc8xxx_gc->data = gpio_in32(mm->regs + GPIO_DAT);
104 +/* Generic set and clear bits accessor ports */
105 +#define bgpio_setbits32(_addr, _v) \
106 + gpio_out32(gpio_in32(_addr) | (_v), (_addr))
107 +#define bgpio_clrbits32(_addr, _v) \
108 + gpio_out32(gpio_in32(_addr) & ~(_v), (_addr))
109 +#define bgpio_clrsetbits32(addr, clear, set) \
110 + gpio_out32((gpio_in32(addr) & ~(clear)) | (set), (addr))
112 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
113 * defined as output cannot be determined by reading GPDAT register,
114 * so we use shadow data register instead. The status of input pins
115 @@ -74,9 +104,9 @@ static int mpc8572_gpio_get(struct gpio_
116 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
117 u32 out_mask, out_shadow;
119 - out_mask = in_be32(mm->regs + GPIO_DIR);
120 + out_mask = gpio_in32(mm->regs + GPIO_DIR);
122 - val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
123 + val = gpio_in32(mm->regs + GPIO_DAT) & ~out_mask;
124 out_shadow = mpc8xxx_gc->data & out_mask;
126 return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
127 @@ -86,7 +116,7 @@ static int mpc8xxx_gpio_get(struct gpio_
129 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
131 - return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
132 + return gpio_in32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
135 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
136 @@ -102,7 +132,7 @@ static void mpc8xxx_gpio_set(struct gpio
138 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
140 - out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
141 + gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT);
143 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
145 @@ -128,7 +158,7 @@ static void mpc8xxx_gpio_set_multiple(st
149 - out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
150 + gpio_out32(mpc8xxx_gc->data, mm->regs + GPIO_DAT);
152 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
154 @@ -141,7 +171,7 @@ static int mpc8xxx_gpio_dir_in(struct gp
156 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
158 - clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
159 + bgpio_clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
161 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
163 @@ -158,7 +188,7 @@ static int mpc8xxx_gpio_dir_out(struct g
165 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
167 - setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
168 + bgpio_setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
170 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
172 @@ -201,7 +231,8 @@ static void mpc8xxx_gpio_irq_cascade(str
173 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
176 - mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
177 + mask = gpio_in32(mm->regs + GPIO_IER)
178 + & gpio_in32(mm->regs + GPIO_IMR);
180 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
182 @@ -217,7 +248,8 @@ static void mpc8xxx_irq_unmask(struct ir
184 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
186 - setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
187 + bgpio_setbits32(mm->regs + GPIO_IMR,
188 + mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
190 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
192 @@ -230,7 +262,8 @@ static void mpc8xxx_irq_mask(struct irq_
194 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
196 - clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
197 + bgpio_clrbits32(mm->regs + GPIO_IMR,
198 + mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
200 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
202 @@ -240,7 +273,7 @@ static void mpc8xxx_irq_ack(struct irq_d
203 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
204 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
206 - out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
207 + gpio_out32(mpc8xxx_gpio2mask(irqd_to_hwirq(d)), mm->regs + GPIO_IER);
210 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
211 @@ -252,15 +285,15 @@ static int mpc8xxx_irq_set_type(struct i
213 case IRQ_TYPE_EDGE_FALLING:
214 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
215 - setbits32(mm->regs + GPIO_ICR,
216 - mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
217 + bgpio_setbits32(mm->regs + GPIO_ICR,
218 + mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
219 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
222 case IRQ_TYPE_EDGE_BOTH:
223 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
224 - clrbits32(mm->regs + GPIO_ICR,
225 - mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
226 + bgpio_clrbits32(mm->regs + GPIO_ICR,
227 + mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
228 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
231 @@ -292,20 +325,20 @@ static int mpc512x_irq_set_type(struct i
232 case IRQ_TYPE_EDGE_FALLING:
233 case IRQ_TYPE_LEVEL_LOW:
234 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
235 - clrsetbits_be32(reg, 3 << shift, 2 << shift);
236 + bgpio_clrsetbits32(reg, 3 << shift, 2 << shift);
237 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
240 case IRQ_TYPE_EDGE_RISING:
241 case IRQ_TYPE_LEVEL_HIGH:
242 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
243 - clrsetbits_be32(reg, 3 << shift, 1 << shift);
244 + bgpio_clrsetbits32(reg, 3 << shift, 1 << shift);
245 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
248 case IRQ_TYPE_EDGE_BOTH:
249 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
250 - clrbits32(reg, 3 << shift);
251 + bgpio_clrbits32(reg, 3 << shift);
252 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
255 @@ -398,6 +431,14 @@ static int mpc8xxx_probe(struct platform
256 mm_gc = &mpc8xxx_gc->mm_gc;
259 + if (of_property_read_bool(np, "little-endian")) {
260 + gpio_little_endian = true;
261 + dev_dbg(&pdev->dev, "GPIO REGISTERS are LITTLE endian\n");
263 + gpio_little_endian = false;
264 + dev_dbg(&pdev->dev, "GPIO REGISTERS are BIG endian\n");
267 mm_gc->save_regs = mpc8xxx_gpio_save_regs;
268 gc->ngpio = MPC8XXX_GPIO_PINS;
269 gc->direction_input = mpc8xxx_gpio_dir_in;
270 @@ -422,7 +463,7 @@ static int mpc8xxx_probe(struct platform
273 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0);
274 - if (mpc8xxx_gc->irqn == NO_IRQ)
275 + if (mpc8xxx_gc->irqn == 0)
278 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
279 @@ -435,8 +476,8 @@ static int mpc8xxx_probe(struct platform
280 mpc8xxx_gc->of_dev_id_data = id->data;
282 /* ack and mask all irqs */
283 - out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
284 - out_be32(mm_gc->regs + GPIO_IMR, 0);
285 + gpio_out32(0xffffffff, mm_gc->regs + GPIO_IER);
286 + gpio_out32(0, mm_gc->regs + GPIO_IMR);
288 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn,
289 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc);