1 From a761ae710d6395af0d8d17a0b4b8f93a816ead46 Mon Sep 17 00:00:00 2001
2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
3 Date: Tue, 17 Jan 2017 17:32:43 +0800
4 Subject: [PATCH 12/13] irqchip/ls-scfg-msi: add MSI affinity support
6 Cherry-pick patchwork patch.
8 For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4 GIC
9 SPI interrupts which can be associated with different Core.
10 So we can support affinity to improve the performance.
11 The MSI message data is a byte for Layerscape MSI.
14 SRS bit0-1 is to select a MSIR which is associated with a CPU.
15 IBS bit2-6 of ls1046, bit2-4 of ls1043a v1.1 is to select bit of the
16 MSIR. With affinity, only bits of MSIR0(srs=0 cpu0) are available.
17 All other bits of the MSIR1-3(cpu1-3) are reserved. The MSI hwirq
18 always equals bit index of the MSIR0. When changing affinity, MSI
19 message data will be appended corresponding SRS then MSI will be
20 moved to the corresponding core.
21 But in affinity mode, there is only 8 MSI interrupts for a controller
22 of LS1043a v1.1. It cannot meet the requirement of the some PCIe
23 devices such as 4 ports Ethernet card. In contrast, without affinity,
24 all MSIRs can be used for core 0, the MSI interrupts can up to 32.
25 So the parameter is added to control affinity mode.
26 "lsmsi=no-affinity" will disable affinity and increase MSI
29 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
30 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
32 drivers/irqchip/irq-ls-scfg-msi.c | 68 ++++++++++++++++++++++++++++++++++++---
33 1 file changed, 63 insertions(+), 5 deletions(-)
35 diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
36 index 71a2050..57e3d90 100644
37 --- a/drivers/irqchip/irq-ls-scfg-msi.c
38 +++ b/drivers/irqchip/irq-ls-scfg-msi.c
39 @@ -40,6 +40,7 @@ struct ls_scfg_msir {
41 unsigned int bit_start;
43 + unsigned int srs; /* Shared interrupt register select */
47 @@ -70,6 +71,19 @@ static struct msi_domain_info ls_scfg_msi_domain_info = {
48 .chip = &ls_scfg_msi_irq_chip,
51 +static int msi_affinity_flag = 1;
53 +static int __init early_parse_ls_scfg_msi(char *p)
55 + if (p && strncmp(p, "no-affinity", 11) == 0)
56 + msi_affinity_flag = 0;
58 + msi_affinity_flag = 1;
62 +early_param("lsmsi", early_parse_ls_scfg_msi);
64 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
66 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
67 @@ -77,12 +91,36 @@ static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
68 msg->address_hi = upper_32_bits(msi_data->msiir_addr);
69 msg->address_lo = lower_32_bits(msi_data->msiir_addr);
70 msg->data = data->hwirq;
72 + if (msi_affinity_flag)
73 + msg->data |= cpumask_first(data->common->affinity);
76 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
77 const struct cpumask *mask, bool force)
80 + struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
83 + if (!msi_affinity_flag)
87 + cpu = cpumask_any_and(mask, cpu_online_mask);
89 + cpu = cpumask_first(mask);
91 + if (cpu >= msi_data->msir_num)
94 + if (msi_data->msir[cpu].gic_irq <= 0) {
95 + pr_warn("cannot bind the irq to cpu%d\n", cpu);
99 + cpumask_copy(irq_data->common->affinity, mask);
101 + return IRQ_SET_MASK_OK;
104 static struct irq_chip ls_scfg_msi_parent_chip = {
105 @@ -158,7 +196,7 @@ static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
107 for_each_set_bit_from(pos, &val, size) {
108 hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
111 virq = irq_find_mapping(msi_data->parent, hwirq);
113 generic_handle_irq(virq);
114 @@ -221,10 +259,19 @@ static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
115 ls_scfg_msi_irq_handler,
118 + if (msi_affinity_flag) {
119 + /* Associate MSIR interrupt to the cpu */
120 + irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
121 + msir->srs = 0; /* This value is determined by the CPU */
125 /* Release the hwirqs corresponding to this MSIR */
126 - for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
127 - hwirq = i << msi_data->cfg->ibs_shift | msir->index;
128 - bitmap_clear(msi_data->used, hwirq, 1);
129 + if (!msi_affinity_flag || msir->index == 0) {
130 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
131 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
132 + bitmap_clear(msi_data->used, hwirq, 1);
137 @@ -321,6 +368,17 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
138 bitmap_set(msi_data->used, 0, msi_data->irqs_num);
140 msi_data->msir_num = of_irq_count(pdev->dev.of_node);
142 + if (msi_affinity_flag) {
145 + cpu_num = num_possible_cpus();
146 + if (msi_data->msir_num >= cpu_num)
147 + msi_data->msir_num = cpu_num;
149 + msi_affinity_flag = 0;
152 msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
153 sizeof(*msi_data->msir),