1 From bd3df6d053a28d5aa630524c9087c21def30e764 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:09:35 +0800
4 Subject: [PATCH] clk: support layerscape
6 This is a integrated patch for layerscape clock support.
8 Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
9 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
10 Signed-off-by: Scott Wood <oss@buserror.net>
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
13 drivers/clk/clk-qoriq.c | 170 ++++++++++++++++++++++++++++++++++++++++++++----
14 1 file changed, 156 insertions(+), 14 deletions(-)
16 diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
17 index 80ae2a51..0e7de00a 100644
18 --- a/drivers/clk/clk-qoriq.c
19 +++ b/drivers/clk/clk-qoriq.c
22 #include <linux/clk.h>
23 #include <linux/clk-provider.h>
24 +#include <linux/clkdev.h>
25 #include <linux/fsl/guts.h>
27 #include <linux/kernel.h>
28 @@ -87,7 +88,7 @@ struct clockgen {
29 struct device_node *node;
31 struct clockgen_chipinfo info; /* mutable copy */
33 + struct clk *sysclk, *coreclk;
34 struct clockgen_pll pll[6];
35 struct clk *cmux[NUM_CMUX];
36 struct clk *hwaccel[NUM_HWACCEL];
37 @@ -266,6 +267,39 @@ static const struct clockgen_muxinfo ls1043a_hwa2 = {
41 +static const struct clockgen_muxinfo ls1046a_hwa1 = {
45 + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
46 + { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
47 + { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
48 + { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
49 + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
50 + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
54 +static const struct clockgen_muxinfo ls1046a_hwa2 = {
57 + { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
58 + { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
59 + { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
62 + { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
66 +static const struct clockgen_muxinfo ls1012a_cmux = {
68 + [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
70 + [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
74 static const struct clockgen_muxinfo t1023_hwa1 = {
77 @@ -488,6 +522,42 @@ static const struct clockgen_chipinfo chipinfo[] = {
82 + .compat = "fsl,ls1046a-clockgen",
83 + .init_periph = t2080_init_periph,
88 + &ls1046a_hwa1, &ls1046a_hwa2
94 + .flags = CG_PLL_8BIT,
97 + .compat = "fsl,ls1088a-clockgen",
99 + &clockgen2_cmux_cga12
105 + .flags = CG_VER3 | CG_LITTLE_ENDIAN,
108 + .compat = "fsl,ls1012a-clockgen",
118 .compat = "fsl,ls2080a-clockgen",
120 @@ -846,7 +916,12 @@ static void __init create_muxes(struct clockgen *cg)
122 static void __init clockgen_init(struct device_node *np);
124 -/* Legacy nodes may get probed before the parent clockgen node */
126 + * Legacy nodes may get probed before the parent clockgen node.
127 + * It is assumed that device trees with legacy nodes will not
128 + * contain a "clocks" property -- otherwise the input clocks may
129 + * not be initialized at this point.
131 static void __init legacy_init_clockgen(struct device_node *np)
134 @@ -887,18 +962,13 @@ static struct clk __init
135 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
138 -static struct clk *sysclk_from_parent(const char *name)
139 +static struct clk __init *input_clock(const char *name, struct clk *clk)
142 - const char *parent_name;
144 - clk = of_clk_get(clockgen.node, 0);
147 + const char *input_name;
149 /* Register the input clock under the desired name. */
150 - parent_name = __clk_get_name(clk);
151 - clk = clk_register_fixed_factor(NULL, name, parent_name,
152 + input_name = __clk_get_name(clk);
153 + clk = clk_register_fixed_factor(NULL, name, input_name,
156 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
157 @@ -907,6 +977,29 @@ static struct clk *sysclk_from_parent(const char *name)
161 +static struct clk __init *input_clock_by_name(const char *name,
162 + const char *dtname)
166 + clk = of_clk_get_by_name(clockgen.node, dtname);
170 + return input_clock(name, clk);
173 +static struct clk __init *input_clock_by_index(const char *name, int idx)
177 + clk = of_clk_get(clockgen.node, 0);
181 + return input_clock(name, clk);
184 static struct clk * __init create_sysclk(const char *name)
186 struct device_node *sysclk;
187 @@ -916,7 +1009,11 @@ static struct clk * __init create_sysclk(const char *name)
191 - clk = sysclk_from_parent(name);
192 + clk = input_clock_by_name(name, "sysclk");
196 + clk = input_clock_by_index(name, 0);
200 @@ -927,7 +1024,27 @@ static struct clk * __init create_sysclk(const char *name)
204 - pr_err("%s: No input clock\n", __func__);
205 + pr_err("%s: No input sysclk\n", __func__);
209 +static struct clk * __init create_coreclk(const char *name)
213 + clk = input_clock_by_name(name, "coreclk");
218 + * This indicates a mix of legacy nodes with the new coreclk
219 + * mechanism, which should never happen. If this error occurs,
220 + * don't use the wrong input clock just because coreclk isn't
223 + if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
229 @@ -950,11 +1067,19 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
232 struct clockgen_pll *pll = &cg->pll[idx];
233 + const char *input = "cg-sysclk";
236 if (!(cg->info.pll_mask & (1 << idx)))
239 + if (cg->coreclk && idx != PLATFORM_PLL) {
240 + if (IS_ERR(cg->coreclk))
243 + input = "cg-coreclk";
246 if (cg->info.flags & CG_VER3) {
249 @@ -1000,12 +1125,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
251 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
255 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
256 "cg-pll%d-div%d", idx, i + 1);
258 clk = clk_register_fixed_factor(NULL,
259 - pll->div[i].name, "cg-sysclk", 0, mult, i + 1);
260 + pll->div[i].name, input, 0, mult, i + 1);
262 pr_err("%s: %s: register failed %ld\n",
263 __func__, pll->div[i].name, PTR_ERR(clk));
264 @@ -1013,6 +1139,11 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
267 pll->div[i].clk = clk;
268 + ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
270 + pr_err("%s: %s: register to lookup table failed %ld\n",
271 + __func__, pll->div[i].name, PTR_ERR(clk));
276 @@ -1142,6 +1273,13 @@ static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
278 clk = pll->div[idx].clk;
290 @@ -1253,6 +1391,7 @@ static void __init clockgen_init(struct device_node *np)
291 clockgen.info.flags |= CG_CMUX_GE_PLAT;
293 clockgen.sysclk = create_sysclk("cg-sysclk");
294 + clockgen.coreclk = create_coreclk("cg-coreclk");
295 create_plls(&clockgen);
296 create_muxes(&clockgen);
298 @@ -1273,8 +1412,11 @@ static void __init clockgen_init(struct device_node *np)
300 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
301 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
302 +CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
303 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
304 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
305 +CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
306 +CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
307 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);