1 From 7e7944c484954ff7b5d53047194e59bfffd1540a Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:20:55 +0800
4 Subject: [PATCH] rtc: support layerscape
6 This is a integrated patch for layerscape rtc support.
8 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
9 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
11 drivers/rtc/rtc-pcf85263.c | 665 +++++++++++++++++++++++++++++++++++++++++++++
12 1 file changed, 665 insertions(+)
13 create mode 100644 drivers/rtc/rtc-pcf85263.c
15 diff --git a/drivers/rtc/rtc-pcf85263.c b/drivers/rtc/rtc-pcf85263.c
17 index 00000000..629c2840
19 +++ b/drivers/rtc/rtc-pcf85263.c
22 + * rtc-pcf85263 Driver for the NXP PCF85263 RTC
23 + * Copyright 2016 Parkeon
25 + * This program is free software; you can redistribute it and/or modify
26 + * it under the terms of the GNU General Public License version 2 as
27 + * published by the Free Software Foundation.
30 +#include <linux/module.h>
31 +#include <linux/mutex.h>
32 +#include <linux/rtc.h>
33 +#include <linux/i2c.h>
34 +#include <linux/bcd.h>
35 +#include <linux/of.h>
36 +#include <linux/of_device.h>
37 +#include <linux/regmap.h>
40 +#define DRV_NAME "rtc-pcf85263"
42 +/* Quartz capacitance */
43 +#define PCF85263_QUARTZCAP_7pF 0
44 +#define PCF85263_QUARTZCAP_6pF 1
45 +#define PCF85263_QUARTZCAP_12p5pF 2
47 +/* Quartz drive strength */
48 +#define PCF85263_QUARTZDRIVE_NORMAL 0
49 +#define PCF85263_QUARTZDRIVE_LOW 1
50 +#define PCF85263_QUARTZDRIVE_HIGH 2
53 +#define PCF85263_REG_RTC_SC 0x01 /* Seconds */
54 +#define PCF85263_REG_RTC_SC_OS BIT(7) /* Oscilator stopped flag */
56 +#define PCF85263_REG_RTC_MN 0x02 /* Minutes */
57 +#define PCF85263_REG_RTC_HR 0x03 /* Hours */
58 +#define PCF85263_REG_RTC_DT 0x04 /* Day of month 1-31 */
59 +#define PCF85263_REG_RTC_DW 0x05 /* Day of week 0-6 */
60 +#define PCF85263_REG_RTC_MO 0x06 /* Month 1-12 */
61 +#define PCF85263_REG_RTC_YR 0x07 /* Year 0-99 */
63 +#define PCF85263_REG_ALM1_SC 0x08 /* Seconds */
64 +#define PCF85263_REG_ALM1_MN 0x09 /* Minutes */
65 +#define PCF85263_REG_ALM1_HR 0x0a /* Hours */
66 +#define PCF85263_REG_ALM1_DT 0x0b /* Day of month 1-31 */
67 +#define PCF85263_REG_ALM1_MO 0x0c /* Month 1-12 */
69 +#define PCF85263_REG_ALM_CTL 0x10
70 +#define PCF85263_REG_ALM_CTL_ALL_A1E 0x1f /* sec,min,hr,day,mon alarm 1 */
72 +#define PCF85263_REG_OSC 0x25
73 +#define PCF85263_REG_OSC_CL_MASK (BIT(0) | BIT(1))
74 +#define PCF85263_REG_OSC_CL_SHIFT 0
75 +#define PCF85263_REG_OSC_OSCD_MASK (BIT(2) | BIT(3))
76 +#define PCF85263_REG_OSC_OSCD_SHIFT 2
77 +#define PCF85263_REG_OSC_LOWJ BIT(4)
78 +#define PCF85263_REG_OSC_12H BIT(5)
80 +#define PCF85263_REG_PINIO 0x27
81 +#define PCF85263_REG_PINIO_INTAPM_MASK (BIT(0) | BIT(1))
82 +#define PCF85263_REG_PINIO_INTAPM_SHIFT 0
83 +#define PCF85263_INTAPM_INTA (0x2 << PCF85263_REG_PINIO_INTAPM_SHIFT)
84 +#define PCF85263_INTAPM_HIGHZ (0x3 << PCF85263_REG_PINIO_INTAPM_SHIFT)
85 +#define PCF85263_REG_PINIO_TSPM_MASK (BIT(2) | BIT(3))
86 +#define PCF85263_REG_PINIO_TSPM_SHIFT 2
87 +#define PCF85263_TSPM_DISABLED (0x0 << PCF85263_REG_PINIO_TSPM_SHIFT)
88 +#define PCF85263_TSPM_INTB (0x1 << PCF85263_REG_PINIO_TSPM_SHIFT)
89 +#define PCF85263_REG_PINIO_CLKDISABLE BIT(7)
91 +#define PCF85263_REG_FUNCTION 0x28
92 +#define PCF85263_REG_FUNCTION_COF_MASK 0x7
93 +#define PCF85263_REG_FUNCTION_COF_OFF 0x7 /* No clock output */
95 +#define PCF85263_REG_INTA_CTL 0x29
96 +#define PCF85263_REG_INTB_CTL 0x2A
97 +#define PCF85263_REG_INTx_CTL_A1E BIT(4) /* Alarm 1 */
98 +#define PCF85263_REG_INTx_CTL_ILP BIT(7) /* 0=pulse, 1=level */
100 +#define PCF85263_REG_FLAGS 0x2B
101 +#define PCF85263_REG_FLAGS_A1F BIT(5)
103 +#define PCF85263_REG_RAM_BYTE 0x2c
105 +#define PCF85263_REG_STOPENABLE 0x2e
106 +#define PCF85263_REG_STOPENABLE_STOP BIT(0)
108 +#define PCF85263_REG_RESET 0x2f /* Reset command */
109 +#define PCF85263_REG_RESET_CMD_CPR 0xa4 /* Clear prescaler */
111 +#define PCF85263_MAX_REG 0x2f
113 +#define PCF85263_HR_PM BIT(5)
115 +enum pcf85263_irqpin {
116 + PCF85263_IRQPIN_NONE,
117 + PCF85263_IRQPIN_INTA,
118 + PCF85263_IRQPIN_INTB
121 +static const char *const pcf85263_irqpin_names[] = {
122 + [PCF85263_IRQPIN_NONE] = "None",
123 + [PCF85263_IRQPIN_INTA] = "INTA",
124 + [PCF85263_IRQPIN_INTB] = "INTB"
128 + struct device *dev;
129 + struct rtc_device *rtc;
130 + struct regmap *regmap;
131 + enum pcf85263_irqpin irq_pin;
137 + * Helpers to convert 12h to 24h and vice versa.
138 + * Values in register are stored in BCD with a PM flag in bit 5
140 + * 23:00 <=> 11PM <=> 0x31
141 + * 00:00 <=> 12AM <=> 0x12
142 + * 01:00 <=> 1AM <=> 0x01
143 + * 12:00 <=> 12PM <=> 0x32
144 + * 13:00 <=> 1PM <=> 0x21
146 +static int pcf85263_bcd12h_to_bin24h(int regval)
148 + int hr = bcd2bin(regval & 0x1f);
149 + bool pm = regval & PCF85263_HR_PM;
152 + return pm ? 12 : 0;
154 + return pm ? hr + 12 : hr;
157 +static int pcf85263_bin24h_to_bcd12h(int hr24)
159 + bool pm = hr24 >= 12;
160 + int hr12 = hr24 % 12;
165 + return bin2bcd(hr12) | pm ? 0 : PCF85263_HR_PM;
168 +static int pcf85263_read_time(struct device *dev, struct rtc_time *tm)
170 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
171 + const int first = PCF85263_REG_RTC_SC;
172 + const int last = PCF85263_REG_RTC_YR;
173 + const int len = last - first + 1;
178 + ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
182 + if (regs[PCF85263_REG_RTC_SC - first] & PCF85263_REG_RTC_SC_OS) {
183 + dev_warn(dev, "Oscillator stop detected, date/time is not reliable.\n");
187 + tm->tm_sec = bcd2bin(regs[PCF85263_REG_RTC_SC - first] & 0x7f);
188 + tm->tm_min = bcd2bin(regs[PCF85263_REG_RTC_MN - first] & 0x7f);
190 + hr_reg = regs[PCF85263_REG_RTC_HR - first];
191 + if (pcf85263->mode_12h)
192 + tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
194 + tm->tm_hour = bcd2bin(hr_reg & 0x3f);
196 + tm->tm_mday = bcd2bin(regs[PCF85263_REG_RTC_DT - first]);
197 + tm->tm_wday = bcd2bin(regs[PCF85263_REG_RTC_DW - first]);
198 + tm->tm_mon = bcd2bin(regs[PCF85263_REG_RTC_MO - first]) - 1;
199 + tm->tm_year = bcd2bin(regs[PCF85263_REG_RTC_YR - first]);
201 + tm->tm_year += 100; /* Assume 21st century */
206 +static int pcf85263_set_time(struct device *dev, struct rtc_time *tm)
208 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
211 + * Before setting time need to stop RTC and disable prescaler
212 + * Do this all in a single I2C transaction exploiting wraparound
213 + * as described in data sheet.
214 + * This means that the array below must be in register order
217 + PCF85263_REG_STOPENABLE_STOP, /* STOP */
218 + PCF85263_REG_RESET_CMD_CPR, /* Disable prescaler */
219 + /* Wrap around to register 0 (1/100s) */
220 + 0, /* 1/100s always zero. */
221 + bin2bcd(tm->tm_sec),
222 + bin2bcd(tm->tm_min),
223 + bin2bcd(tm->tm_hour), /* 24-hour */
224 + bin2bcd(tm->tm_mday),
225 + bin2bcd(tm->tm_wday + 1),
226 + bin2bcd(tm->tm_mon + 1),
227 + bin2bcd(tm->tm_year % 100)
231 + ret = regmap_bulk_write(pcf85263->regmap, PCF85263_REG_STOPENABLE,
232 + regs, sizeof(regs));
236 + /* As we have set the time in 24H update the hardware for that */
237 + if (pcf85263->mode_12h) {
238 + pcf85263->mode_12h = false;
239 + ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_OSC,
240 + PCF85263_REG_OSC_12H, 0);
245 + /* Start it again */
246 + return regmap_write(pcf85263->regmap, PCF85263_REG_STOPENABLE, 0);
249 +static int pcf85263_enable_alarm(struct pcf85263 *pcf85263, bool enable)
254 + ret = regmap_update_bits(pcf85263->regmap, PCF85263_REG_ALM_CTL,
255 + PCF85263_REG_ALM_CTL_ALL_A1E,
256 + enable ? PCF85263_REG_ALM_CTL_ALL_A1E : 0);
260 + switch (pcf85263->irq_pin) {
261 + case PCF85263_IRQPIN_NONE:
264 + case PCF85263_IRQPIN_INTA:
265 + reg = PCF85263_REG_INTA_CTL;
268 + case PCF85263_IRQPIN_INTB:
269 + reg = PCF85263_REG_INTB_CTL;
276 + return regmap_update_bits(pcf85263->regmap, reg,
277 + PCF85263_REG_INTx_CTL_A1E,
278 + enable ? PCF85263_REG_INTx_CTL_A1E : 0);
281 +static int pcf85263_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
283 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
284 + struct rtc_time *tm = &alarm->time;
285 + const int first = PCF85263_REG_ALM1_SC;
286 + const int last = PCF85263_REG_ALM1_MO;
287 + const int len = last - first + 1;
290 + unsigned int regval;
293 + ret = regmap_bulk_read(pcf85263->regmap, first, regs, len);
297 + tm->tm_sec = bcd2bin(regs[PCF85263_REG_ALM1_SC - first] & 0x7f);
298 + tm->tm_min = bcd2bin(regs[PCF85263_REG_ALM1_MN - first] & 0x7f);
300 + hr_reg = regs[PCF85263_REG_ALM1_HR - first];
301 + if (pcf85263->mode_12h)
302 + tm->tm_hour = pcf85263_bcd12h_to_bin24h(hr_reg);
304 + tm->tm_hour = bcd2bin(hr_reg & 0x3f);
306 + tm->tm_mday = bcd2bin(regs[PCF85263_REG_ALM1_DT - first]);
307 + tm->tm_mon = bcd2bin(regs[PCF85263_REG_ALM1_MO - first]) - 1;
311 + ret = regmap_read(pcf85263->regmap, PCF85263_REG_ALM_CTL, ®val);
314 + alarm->enabled = !!(regval & PCF85263_REG_ALM_CTL_ALL_A1E);
316 + ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, ®val);
319 + alarm->pending = !!(regval & PCF85263_REG_FLAGS_A1F);
324 +static int pcf85263_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
326 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
327 + struct rtc_time *tm = &alarm->time;
328 + const int first = PCF85263_REG_ALM1_SC;
329 + const int last = PCF85263_REG_ALM1_MO;
330 + const int len = last - first + 1;
334 + /* Disable alarm comparison during update */
335 + ret = pcf85263_enable_alarm(pcf85263, false);
339 + /* Clear any pending alarm (write 0=>clr, 1=>no change) */
340 + ret = regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
341 + (unsigned int)(~PCF85263_REG_FLAGS_A1F));
345 + /* Set the alarm time registers */
346 + regs[PCF85263_REG_ALM1_SC - first] = bin2bcd(tm->tm_sec);
347 + regs[PCF85263_REG_ALM1_MN - first] = bin2bcd(tm->tm_min);
348 + regs[PCF85263_REG_ALM1_HR - first] = pcf85263->mode_12h ?
349 + pcf85263_bin24h_to_bcd12h(tm->tm_hour) :
350 + bin2bcd(tm->tm_hour);
351 + regs[PCF85263_REG_ALM1_DT - first] = bin2bcd(tm->tm_mday);
352 + regs[PCF85263_REG_ALM1_MO - first] = bin2bcd(tm->tm_mon + 1);
354 + ret = regmap_bulk_write(pcf85263->regmap, first, regs, sizeof(regs));
358 + if (alarm->enabled)
359 + ret = pcf85263_enable_alarm(pcf85263, true);
364 +static int pcf85263_alarm_irq_enable(struct device *dev, unsigned int enable)
366 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
368 + return pcf85263_enable_alarm(pcf85263, !!enable);
371 +static irqreturn_t pcf85263_irq(int irq, void *data)
373 + struct pcf85263 *pcf85263 = data;
374 + unsigned int regval;
377 + ret = regmap_read(pcf85263->regmap, PCF85263_REG_FLAGS, ®val);
381 + if (regval & PCF85263_REG_FLAGS_A1F) {
382 + regmap_write(pcf85263->regmap, PCF85263_REG_FLAGS,
383 + (unsigned int)(~PCF85263_REG_FLAGS_A1F));
385 + rtc_update_irq(pcf85263->rtc, 1, RTC_IRQF | RTC_AF);
387 + return IRQ_HANDLED;
393 +static int pcf85263_check_osc_stopped(struct pcf85263 *pcf85263)
395 + unsigned int regval;
398 + ret = regmap_read(pcf85263->regmap, PCF85263_REG_RTC_SC, ®val);
402 + ret = regval & PCF85263_REG_RTC_SC_OS ? 1 : 0;
404 + dev_warn(pcf85263->dev, "Oscillator stop detected, date/time is not reliable.\n");
409 +#ifdef CONFIG_RTC_INTF_DEV
410 +static int pcf85263_ioctl(struct device *dev,
411 + unsigned int cmd, unsigned long arg)
413 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
418 + ret = pcf85263_check_osc_stopped(pcf85263);
422 + if (copy_to_user((void __user *)arg, &ret, sizeof(int)))
427 + return regmap_update_bits(pcf85263->regmap,
428 + PCF85263_REG_RTC_SC,
429 + PCF85263_REG_RTC_SC_OS, 0);
431 + return -ENOIOCTLCMD;
435 +#define pcf85263_ioctl NULL
438 +static int pcf85263_init_hw(struct pcf85263 *pcf85263)
440 + struct device_node *np = pcf85263->dev->of_node;
441 + unsigned int regval;
445 + /* Determine if oscilator has been stopped (probably low power) */
446 + ret = pcf85263_check_osc_stopped(pcf85263);
448 + /* Log here since this is the first hw access on probe */
449 + dev_err(pcf85263->dev, "Unable to read register\n");
454 + /* Determine 12/24H mode */
455 + ret = regmap_read(pcf85263->regmap, PCF85263_REG_OSC, ®val);
458 + pcf85263->mode_12h = !!(regval & PCF85263_REG_OSC_12H);
460 + /* Set oscilator register */
461 + regval &= ~PCF85263_REG_OSC_12H; /* keep current 12/24 h setting */
463 + propval = PCF85263_QUARTZCAP_12p5pF;
464 + of_property_read_u32(np, "quartz-load-capacitance", &propval);
465 + regval |= ((propval << PCF85263_REG_OSC_CL_SHIFT)
466 + & PCF85263_REG_OSC_CL_MASK);
468 + propval = PCF85263_QUARTZDRIVE_NORMAL;
469 + of_property_read_u32(np, "quartz-drive-strength", &propval);
470 + regval |= ((propval << PCF85263_REG_OSC_OSCD_SHIFT)
471 + & PCF85263_REG_OSC_OSCD_MASK);
473 + if (of_property_read_bool(np, "quartz-low-jitter"))
474 + regval |= PCF85263_REG_OSC_LOWJ;
476 + ret = regmap_write(pcf85263->regmap, PCF85263_REG_OSC, regval);
480 + /* Set function register (RTC mode, 1s tick, clock output static) */
481 + ret = regmap_write(pcf85263->regmap, PCF85263_REG_FUNCTION,
482 + PCF85263_REG_FUNCTION_COF_OFF);
486 + /* Set all interrupts to disabled, level mode */
487 + ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTA_CTL,
488 + PCF85263_REG_INTx_CTL_ILP);
491 + ret = regmap_write(pcf85263->regmap, PCF85263_REG_INTB_CTL,
492 + PCF85263_REG_INTx_CTL_ILP);
496 + /* Setup IO pin config register */
497 + regval = PCF85263_REG_PINIO_CLKDISABLE;
498 + switch (pcf85263->irq_pin) {
499 + case PCF85263_IRQPIN_INTA:
500 + regval |= (PCF85263_INTAPM_INTA | PCF85263_TSPM_DISABLED);
502 + case PCF85263_IRQPIN_INTB:
503 + regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_INTB);
505 + case PCF85263_IRQPIN_NONE:
506 + regval |= (PCF85263_INTAPM_HIGHZ | PCF85263_TSPM_DISABLED);
509 + ret = regmap_write(pcf85263->regmap, PCF85263_REG_PINIO, regval);
514 +static const struct rtc_class_ops rtc_ops = {
515 + .ioctl = pcf85263_ioctl,
516 + .read_time = pcf85263_read_time,
517 + .set_time = pcf85263_set_time,
518 + .read_alarm = pcf85263_read_alarm,
519 + .set_alarm = pcf85263_set_alarm,
520 + .alarm_irq_enable = pcf85263_alarm_irq_enable,
523 +static const struct regmap_config pcf85263_regmap_cfg = {
526 + .max_register = PCF85263_MAX_REG,
530 + * On some boards the interrupt line may not be wired to the CPU but only to
531 + * a power supply circuit.
532 + * In that case no interrupt will be specified in the device tree but the
533 + * wakeup-source DT property may be used to enable wakeup programming in
536 +static bool pcf85263_can_wakeup_machine(struct pcf85263 *pcf85263)
538 + return pcf85263->irq ||
539 + of_property_read_bool(pcf85263->dev->of_node, "wakeup-source");
542 +static int pcf85263_probe(struct i2c_client *client,
543 + const struct i2c_device_id *id)
545 + struct device *dev = &client->dev;
546 + struct pcf85263 *pcf85263;
549 + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C |
550 + I2C_FUNC_SMBUS_BYTE_DATA |
551 + I2C_FUNC_SMBUS_I2C_BLOCK))
554 + pcf85263 = devm_kzalloc(dev, sizeof(*pcf85263), GFP_KERNEL);
558 + pcf85263->dev = dev;
559 + pcf85263->irq = client->irq;
560 + dev_set_drvdata(dev, pcf85263);
562 + pcf85263->regmap = devm_regmap_init_i2c(client, &pcf85263_regmap_cfg);
563 + if (IS_ERR(pcf85263->regmap)) {
564 + ret = PTR_ERR(pcf85263->regmap);
565 + dev_err(dev, "regmap allocation failed (%d)\n", ret);
570 + /* Determine which interrupt pin the board uses */
571 + if (pcf85263_can_wakeup_machine(pcf85263)) {
572 + if (of_property_match_string(dev->of_node,
573 + "interrupt-names", "INTB") >= 0)
574 + pcf85263->irq_pin = PCF85263_IRQPIN_INTB;
576 + pcf85263->irq_pin = PCF85263_IRQPIN_INTA;
578 + pcf85263->irq_pin = PCF85263_IRQPIN_NONE;
581 + ret = pcf85263_init_hw(pcf85263);
585 + if (pcf85263->irq) {
586 + ret = devm_request_threaded_irq(dev, pcf85263->irq, NULL,
589 + dev->driver->name, pcf85263);
591 + dev_err(dev, "irq %d unavailable (%d)\n",
592 + pcf85263->irq, ret);
597 + if (pcf85263_can_wakeup_machine(pcf85263))
598 + device_init_wakeup(dev, true);
600 + pcf85263->rtc = devm_rtc_device_register(dev, dev->driver->name,
601 + &rtc_ops, THIS_MODULE);
602 + ret = PTR_ERR_OR_ZERO(pcf85263->rtc);
606 + /* We cannot support UIE mode if we do not have an IRQ line */
607 + if (!pcf85263->irq)
608 + pcf85263->rtc->uie_unsupported = 1;
610 + dev_info(pcf85263->dev,
611 + "PCF85263 RTC (irqpin=%s irq=%d)\n",
612 + pcf85263_irqpin_names[pcf85263->irq_pin],
618 +static int pcf85263_remove(struct i2c_client *client)
620 + struct pcf85263 *pcf85263 = i2c_get_clientdata(client);
622 + if (pcf85263_can_wakeup_machine(pcf85263))
623 + device_init_wakeup(pcf85263->dev, false);
628 +#ifdef CONFIG_PM_SLEEP
629 +static int pcf85263_suspend(struct device *dev)
631 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
634 + if (device_may_wakeup(dev))
635 + ret = enable_irq_wake(pcf85263->irq);
640 +static int pcf85263_resume(struct device *dev)
642 + struct pcf85263 *pcf85263 = dev_get_drvdata(dev);
645 + if (device_may_wakeup(dev))
646 + ret = disable_irq_wake(pcf85263->irq);
653 +static const struct i2c_device_id pcf85263_id[] = {
657 +MODULE_DEVICE_TABLE(i2c, pcf85263_id);
660 +static const struct of_device_id pcf85263_of_match[] = {
661 + { .compatible = "nxp,pcf85263" },
664 +MODULE_DEVICE_TABLE(of, pcf85263_of_match);
667 +static SIMPLE_DEV_PM_OPS(pcf85263_pm_ops, pcf85263_suspend, pcf85263_resume);
669 +static struct i2c_driver pcf85263_driver = {
671 + .name = "rtc-pcf85263",
672 + .of_match_table = of_match_ptr(pcf85263_of_match),
673 + .pm = &pcf85263_pm_ops,
675 + .probe = pcf85263_probe,
676 + .remove = pcf85263_remove,
677 + .id_table = pcf85263_id,
680 +module_i2c_driver(pcf85263_driver);
682 +MODULE_AUTHOR("Martin Fuzzey <mfuzzey@parkeon.com>");
683 +MODULE_DESCRIPTION("PCF85263 RTC Driver");
684 +MODULE_LICENSE("GPL");