1 From a9f1c1d3e410596d0a39fd92562cc48ef960b1b7 Mon Sep 17 00:00:00 2001
2 From: Li Yang <leoyang.li@nxp.com>
3 Date: Fri, 5 Oct 2018 18:33:49 -0500
4 Subject: [PATCH] ARM: dts: accumulated change
6 Signed-off-by: Li Yang <leoyang.li@nxp.com>
8 arch/arm/boot/dts/ls1021a-qds.dts | 15 +++++++++++++++
9 arch/arm/boot/dts/ls1021a-twr.dts | 15 +++++++++++++++
10 arch/arm/boot/dts/ls1021a.dtsi | 29 ++++++++++++++++++++++++-----
11 3 files changed, 54 insertions(+), 5 deletions(-)
13 --- a/arch/arm/boot/dts/ls1021a-qds.dts
14 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
23 + qflash0: s25fl128s@0 {
24 + compatible = "spansion,m25p80";
25 + #address-cells = <1>;
27 + spi-max-frequency = <20000000>;
29 + spi-rx-bus-width = <4>;
30 + spi-tx-bus-width = <4>;
36 phy-handle = <&sgmii_phy1c>;
37 --- a/arch/arm/boot/dts/ls1021a-twr.dts
38 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
47 + qflash0: n25q128a13@0 {
48 + compatible = "n25q128a13", "jedec,spi-nor";
49 + #address-cells = <1>;
51 + spi-max-frequency = <20000000>;
53 + spi-rx-bus-width = <4>;
54 + spi-tx-bus-width = <4>;
60 phy-handle = <&sgmii_phy2>;
61 --- a/arch/arm/boot/dts/ls1021a.dtsi
62 +++ b/arch/arm/boot/dts/ls1021a.dtsi
65 compatible = "fsl,ifc", "simple-bus";
66 reg = <0x0 0x1530000 0x0 0x10000>;
68 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
72 compatible = "fsl,ls1021a-dcfg", "syscon";
73 - reg = <0x0 0x1ee0000 0x0 0x10000>;
74 + reg = <0x0 0x1ee0000 0x0 0x1000>;
82 - compatible = "fsl,vf610-i2c";
83 + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
86 reg = <0x0 0x2180000 0x0 0x10000>;
88 clocks = <&clockgen 4 1>;
89 dma-names = "tx", "rx";
90 dmas = <&edma0 1 39>, <&edma0 1 38>;
91 + fsl-scl-gpio = <&gpio3 23 0>;
96 - compatible = "fsl,vf610-i2c";
97 + compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c";
100 reg = <0x0 0x2190000 0x0 0x10000>;
102 clocks = <&clockgen 4 1>;
103 dma-names = "tx", "rx";
104 dmas = <&edma0 1 37>, <&edma0 1 36>;
105 + fsl-scl-gpio = <&gpio3 23 0>;
113 + ftm0: ftm0@29d0000 {
114 + compatible = "fsl,ftm-alarm";
115 + reg = <0x0 0x29d0000 0x0 0x10000>,
116 + <0x0 0x1ee2140 0x0 0x4>;
117 + reg-names = "ftm", "FlexTimer1";
118 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
124 compatible = "fsl,vf610-ftm-pwm";
128 snps,quirk-frame-length-adjustment = <0x20>;
129 snps,dis_rxdet_inp3_quirk;
131 + snps,dis-u1u2-when-u3-quirk;
132 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
136 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
137 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
138 reg-names = "regs", "config";
139 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
140 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
141 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
142 + interrupt-names = "pme", "aer";
143 fsl,pcie-scfg = <&scfg 0>;
144 #address-cells = <3>;
147 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
148 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
149 reg-names = "regs", "config";
150 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
151 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
152 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
153 + interrupt-names = "pme", "aer";
154 fsl,pcie-scfg = <&scfg 1>;
155 #address-cells = <3>;