target/linux/layerscape/patches-5.4/302-dts-0033-arm64-dts-freescale-lx2160a-add-pcie-DT-nodes.patch

   1 From 86e03654997db1b70e71f717ab3e74b1df2f402c Mon Sep 17 00:00:00 2001
   2 From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
   3 Date: Thu, 13 Jul 2017 18:28:27 +0800
   4 Subject: [PATCH] arm64: dts: freescale: lx2160a: add pcie DT nodes
   5
   6 The LX2160A integrated 6 PCIe Gen4 controllers.
   7
   8 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
   9 ---
  10  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 162 +++++++++++++++++++++++++
  11  1 file changed, 162 insertions(+)
  12
  13 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
  14 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
  15 @@ -903,6 +903,168 @@
  16                         status = "disabled";
  17                 };
  18
  19 +               pcie@3400000 {
  20 +                       compatible = "fsl,lx2160a-pcie";
  21 +                       reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
  22 +                              0x80 0x00000000 0x0 0x00001000>; /* configuration space */
  23 +                       reg-names = "csr_axi_slave", "config_axi_slave";
  24 +                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
  25 +                                    <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
  26 +                                    <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
  27 +                       interrupt-names = "aer", "pme", "intr";
  28 +                       #address-cells = <3>;
  29 +                       #size-cells = <2>;
  30 +                       device_type = "pci";
  31 +                       dma-coherent;
  32 +                       apio-wins = <8>;
  33 +                       ppio-wins = <8>;
  34 +                       bus-range = <0x0 0xff>;
  35 +                       ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  36 +                       msi-parent = <&its>;
  37 +                       #interrupt-cells = <1>;
  38 +                       interrupt-map-mask = <0 0 0 7>;
  39 +                       interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
  40 +                                       <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
  41 +                                       <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
  42 +                                       <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  43 +                       status = "disabled";
  44 +               };
  45 +
  46 +               pcie@3500000 {
  47 +                       compatible = "fsl,lx2160a-pcie";
  48 +                       reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
  49 +                              0x88 0x00000000 0x0 0x00001000>; /* configuration space */
  50 +                       reg-names = "csr_axi_slave", "config_axi_slave";
  51 +                       interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
  52 +                                    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
  53 +                                    <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
  54 +                       interrupt-names = "aer", "pme", "intr";
  55 +                       #address-cells = <3>;
  56 +                       #size-cells = <2>;
  57 +                       device_type = "pci";
  58 +                       dma-coherent;
  59 +                       apio-wins = <8>;
  60 +                       ppio-wins = <8>;
  61 +                       bus-range = <0x0 0xff>;
  62 +                       ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  63 +                       msi-parent = <&its>;
  64 +                       #interrupt-cells = <1>;
  65 +                       interrupt-map-mask = <0 0 0 7>;
  66 +                       interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
  67 +                                       <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
  68 +                                       <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  69 +                                       <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
  70 +                       status = "disabled";
  71 +               };
  72 +
  73 +               pcie@3600000 {
  74 +                       compatible = "fsl,lx2160a-pcie";
  75 +                       reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
  76 +                              0x90 0x00000000 0x0 0x00001000>; /* configuration space */
  77 +                       reg-names = "csr_axi_slave", "config_axi_slave";
  78 +                       interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
  79 +                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
  80 +                                    <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
  81 +                       interrupt-names = "aer", "pme", "intr";
  82 +                       #address-cells = <3>;
  83 +                       #size-cells = <2>;
  84 +                       device_type = "pci";
  85 +                       dma-coherent;
  86 +                       apio-wins = <8>;
  87 +                       ppio-wins = <8>;
  88 +                       bus-range = <0x0 0xff>;
  89 +                       ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  90 +                       msi-parent = <&its>;
  91 +                       #interrupt-cells = <1>;
  92 +                       interrupt-map-mask = <0 0 0 7>;
  93 +                       interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
  94 +                                       <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  95 +                                       <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  96 +                                       <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  97 +                       status = "disabled";
  98 +               };
  99 +
 100 +               pcie@3700000 {
 101 +                       compatible = "fsl,lx2160a-pcie";
 102 +                       reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
 103 +                              0x98 0x00000000 0x0 0x00001000>; /* configuration space */
 104 +                       reg-names = "csr_axi_slave", "config_axi_slave";
 105 +                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 106 +                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 107 +                                    <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 108 +                       interrupt-names = "aer", "pme", "intr";
 109 +                       #address-cells = <3>;
 110 +                       #size-cells = <2>;
 111 +                       device_type = "pci";
 112 +                       dma-coherent;
 113 +                       apio-wins = <8>;
 114 +                       ppio-wins = <8>;
 115 +                       bus-range = <0x0 0xff>;
 116 +                       ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 117 +                       msi-parent = <&its>;
 118 +                       #interrupt-cells = <1>;
 119 +                       interrupt-map-mask = <0 0 0 7>;
 120 +                       interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 121 +                                       <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 122 +                                       <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 123 +                                       <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 124 +                       status = "disabled";
 125 +               };
 126 +
 127 +               pcie@3800000 {
 128 +                       compatible = "fsl,lx2160a-pcie";
 129 +                       reg = <0x00 0x03800000 0x0 0x00100000   /* controller registers */
 130 +                              0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
 131 +                       reg-names = "csr_axi_slave", "config_axi_slave";
 132 +                       interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 133 +                                    <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 134 +                                    <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 135 +                       interrupt-names = "aer", "pme", "intr";
 136 +                       #address-cells = <3>;
 137 +                       #size-cells = <2>;
 138 +                       device_type = "pci";
 139 +                       dma-coherent;
 140 +                       apio-wins = <8>;
 141 +                       ppio-wins = <8>;
 142 +                       bus-range = <0x0 0xff>;
 143 +                       ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 144 +                       msi-parent = <&its>;
 145 +                       #interrupt-cells = <1>;
 146 +                       interrupt-map-mask = <0 0 0 7>;
 147 +                       interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 148 +                                       <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 149 +                                       <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 150 +                                       <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 151 +                       status = "disabled";
 152 +               };
 153 +
 154 +               pcie@3900000 {
 155 +                       compatible = "fsl,lx2160a-pcie";
 156 +                       reg = <0x00 0x03900000 0x0 0x00100000   /* controller registers */
 157 +                              0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
 158 +                       reg-names = "csr_axi_slave", "config_axi_slave";
 159 +                       interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
 160 +                                    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 161 +                                    <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
 162 +                       interrupt-names = "aer", "pme", "intr";
 163 +                       #address-cells = <3>;
 164 +                       #size-cells = <2>;
 165 +                       device_type = "pci";
 166 +                       dma-coherent;
 167 +                       apio-wins = <8>;
 168 +                       ppio-wins = <8>;
 169 +                       bus-range = <0x0 0xff>;
 170 +                       ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 171 +                       msi-parent = <&its>;
 172 +                       #interrupt-cells = <1>;
 173 +                       interrupt-map-mask = <0 0 0 7>;
 174 +                       interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 175 +                                       <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 176 +                                       <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 177 +                                       <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 178 +                       status = "disabled";
 179 +               };
 180 +
 181                 smmu: iommu@5000000 {
 182                         compatible = "arm,mmu-500";
 183                         reg = <0 0x5000000 0 0x800000>;