1 From c9be87f17c64d08c06e4858589a0014f73868867 Mon Sep 17 00:00:00 2001
2 From: Pankaj Bansal <pankaj.bansal@nxp.com>
3 Date: Thu, 28 Feb 2019 17:28:36 +0530
4 Subject: [PATCH] arm64: dts: lx2160aqds: Add mdio mux nodes
6 The two external MDIO buses used to communicate with phy devices that are
7 external to SOC are muxed in LX2160AQDS board.
8 These buses can be routed to any one of the eight IO slots on LX2160AQDS
9 board depending on value in fpga register 0x54.
10 Additionally the external MDIO1 is used to communicate to the onboard
12 The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is
13 controlled by bits 4-7 of fpga register.
15 Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
17 arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++++++
18 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 8 ++
19 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++--
20 3 files changed, 165 insertions(+), 12 deletions(-)
22 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
23 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts
30 + compatible = "mdio-mux-multiplexer";
31 + mux-controls = <&mux 0>;
32 + mdio-parent-bus = <&emdio1>;
36 + mdio@0 { /* On-board PHY #1 RGMI1*/
38 + #address-cells = <1>;
42 + mdio@8 { /* On-board PHY #2 RGMI2*/
44 + #address-cells = <1>;
48 + mdio@18 { /* Slot #1 */
50 + #address-cells = <1>;
54 + mdio@19 { /* Slot #2 */
56 + #address-cells = <1>;
60 + mdio@1a { /* Slot #3 */
62 + #address-cells = <1>;
66 + mdio@1b { /* Slot #4 */
68 + #address-cells = <1>;
72 + mdio@1c { /* Slot #5 */
74 + #address-cells = <1>;
78 + mdio@1d { /* Slot #6 */
80 + #address-cells = <1>;
84 + mdio@1e { /* Slot #7 */
86 + #address-cells = <1>;
90 + mdio@1f { /* Slot #8 */
92 + #address-cells = <1>;
98 + compatible = "mdio-mux-multiplexer";
99 + mux-controls = <&mux 1>;
100 + mdio-parent-bus = <&emdio2>;
101 + #address-cells=<1>;
104 + mdio@0 { /* Slot #1 (secondary EMI) */
106 + #address-cells = <1>;
110 + mdio@1 { /* Slot #2 (secondary EMI) */
112 + #address-cells = <1>;
116 + mdio@2 { /* Slot #3 (secondary EMI) */
118 + #address-cells = <1>;
122 + mdio@3 { /* Slot #4 (secondary EMI) */
124 + #address-cells = <1>;
128 + mdio@4 { /* Slot #5 (secondary EMI) */
130 + #address-cells = <1>;
134 + mdio@5 { /* Slot #6 (secondary EMI) */
136 + #address-cells = <1>;
140 + mdio@6 { /* Slot #7 (secondary EMI) */
142 + #address-cells = <1>;
146 + mdio@7 { /* Slot #8 (secondary EMI) */
148 + #address-cells = <1>;
175 + compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
179 + mux: mux-controller {
180 + compatible = "reg-mux";
181 + #mux-control-cells = <1>;
182 + mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
183 + <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
188 compatible = "nxp,pca9547";
190 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
191 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
207 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
208 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
209 @@ -478,26 +478,26 @@
213 - /* TODO: WRIOP (CCSR?) */
214 - emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
215 + /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
216 + emdio1: mdio@8b96000 {
217 compatible = "fsl,fman-memac-mdio";
218 - reg = <0x0 0x8B96000 0x0 0x1000>;
219 - device_type = "mdio"; /* TODO: is this necessary? */
220 - little-endian; /* force the driver in LE mode */
222 - /* Not necessary on the QDS, but needed on the RDB */
223 + reg = <0x0 0x8b96000 0x0 0x1000>;
224 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
225 #address-cells = <1>;
227 + little-endian; /* force the driver in LE mode */
228 + status = "disabled";
231 - emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
232 + /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
233 + emdio2: mdio@8b97000 {
234 compatible = "fsl,fman-memac-mdio";
235 - reg = <0x0 0x8B97000 0x0 0x1000>;
236 - device_type = "mdio"; /* TODO: is this necessary? */
237 - little-endian; /* force the driver in LE mode */
239 + reg = <0x0 0x8b97000 0x0 0x1000>;
240 + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
241 #address-cells = <1>;
243 + little-endian; /* force the driver in LE mode */
244 + status = "disabled";
247 pcs_mdio1: mdio@0x8c07000 {