1 From f6233242d21bb4cb973a7dfc61dcfbf6d9a5d22b Mon Sep 17 00:00:00 2001
2 From: Yuantian Tang <andy.tang@nxp.com>
3 Date: Mon, 2 Sep 2019 17:45:19 +0800
4 Subject: [PATCH] arm64: dts: lx2160a: add tmu device node
6 Add the TMU (Thermal Monitoring Unit) device node to enable
9 Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
11 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++++++++++++++++++++----
12 1 file changed, 92 insertions(+), 16 deletions(-)
14 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
15 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 +#include <dt-bindings/thermal/thermal.h>
22 /memreserve/ 0x80000000 0x00010000;
27 // 8 clusters having 2 Cortex-A72 cores each
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
35 next-level-cache = <&cluster0_l2>;
36 cpu-idle-states = <&cpu_pw15>;
37 + #cooling-cells = <2>;
43 compatible = "arm,cortex-a72";
44 enable-method = "psci";
47 next-level-cache = <&cluster0_l2>;
48 cpu-idle-states = <&cpu_pw15>;
49 + #cooling-cells = <2>;
55 compatible = "arm,cortex-a72";
56 enable-method = "psci";
59 next-level-cache = <&cluster1_l2>;
60 cpu-idle-states = <&cpu_pw15>;
61 + #cooling-cells = <2>;
67 compatible = "arm,cortex-a72";
68 enable-method = "psci";
71 next-level-cache = <&cluster1_l2>;
72 cpu-idle-states = <&cpu_pw15>;
73 + #cooling-cells = <2>;
79 compatible = "arm,cortex-a72";
80 enable-method = "psci";
83 next-level-cache = <&cluster2_l2>;
84 cpu-idle-states = <&cpu_pw15>;
85 + #cooling-cells = <2>;
91 compatible = "arm,cortex-a72";
92 enable-method = "psci";
95 next-level-cache = <&cluster2_l2>;
96 cpu-idle-states = <&cpu_pw15>;
97 + #cooling-cells = <2>;
103 compatible = "arm,cortex-a72";
104 enable-method = "psci";
106 i-cache-sets = <192>;
107 next-level-cache = <&cluster3_l2>;
108 cpu-idle-states = <&cpu_pw15>;
109 + #cooling-cells = <2>;
115 compatible = "arm,cortex-a72";
116 enable-method = "psci";
118 i-cache-sets = <192>;
119 next-level-cache = <&cluster3_l2>;
120 cpu-idle-states = <&cpu_pw15>;
121 + #cooling-cells = <2>;
127 compatible = "arm,cortex-a72";
128 enable-method = "psci";
130 i-cache-sets = <192>;
131 next-level-cache = <&cluster4_l2>;
132 cpu-idle-states = <&cpu_pw15>;
133 + #cooling-cells = <2>;
139 compatible = "arm,cortex-a72";
140 enable-method = "psci";
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster4_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 + #cooling-cells = <2>;
151 compatible = "arm,cortex-a72";
152 enable-method = "psci";
154 i-cache-sets = <192>;
155 next-level-cache = <&cluster5_l2>;
156 cpu-idle-states = <&cpu_pw15>;
157 + #cooling-cells = <2>;
163 compatible = "arm,cortex-a72";
164 enable-method = "psci";
166 i-cache-sets = <192>;
167 next-level-cache = <&cluster5_l2>;
168 cpu-idle-states = <&cpu_pw15>;
169 + #cooling-cells = <2>;
175 compatible = "arm,cortex-a72";
176 enable-method = "psci";
178 i-cache-sets = <192>;
179 next-level-cache = <&cluster6_l2>;
180 cpu-idle-states = <&cpu_pw15>;
181 + #cooling-cells = <2>;
187 compatible = "arm,cortex-a72";
188 enable-method = "psci";
190 i-cache-sets = <192>;
191 next-level-cache = <&cluster6_l2>;
192 cpu-idle-states = <&cpu_pw15>;
193 + #cooling-cells = <2>;
199 compatible = "arm,cortex-a72";
200 enable-method = "psci";
202 i-cache-sets = <192>;
203 next-level-cache = <&cluster7_l2>;
204 cpu-idle-states = <&cpu_pw15>;
205 + #cooling-cells = <2>;
211 compatible = "arm,cortex-a72";
212 enable-method = "psci";
214 i-cache-sets = <192>;
215 next-level-cache = <&cluster7_l2>;
216 cpu-idle-states = <&cpu_pw15>;
217 + #cooling-cells = <2>;
220 cluster0_l2: l2-cache0 {
222 clock-output-names = "sysclk";
226 + core_thermal1: core-thermal1 {
227 + polling-delay-passive = <1000>;
228 + polling-delay = <5000>;
229 + thermal-sensors = <&tmu 0>;
232 + core_cluster_alert: core-cluster-alert {
233 + temperature = <85000>;
234 + hysteresis = <2000>;
238 + core_cluster_crit: core-cluster-crit {
239 + temperature = <95000>;
240 + hysteresis = <2000>;
247 + trip = <&core_cluster_alert>;
249 + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
253 + <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
254 + <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
255 + <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
256 + <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
257 + <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
258 + <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
259 + <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
260 + <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
261 + <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
262 + <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
263 + <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
264 + <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
271 compatible = "simple-bus";
272 #address-cells = <2>;
278 + compatible = "fsl,qoriq-tmu";
279 + reg = <0x0 0x1f80000 0x0 0x10000>;
280 + interrupts = <0 23 0x4>;
281 + fsl,tmu-range = <0x800000E6 0x8001017D>;
282 + fsl,tmu-calibration =
283 + /* Calibration data group 1 */
284 + <0x00000000 0x00000035
285 + /* Calibration data group 2 */
286 + 0x00010001 0x00000154>;
288 + #thermal-sensor-cells = <1>;
291 uart0: serial@21c0000 {
292 compatible = "arm,sbsa-uart","arm,pl011";
293 reg = <0x0 0x21c0000 0x0 0x1000>;