1 From 094a648bc2217a9624f35224059c3eac86196143 Mon Sep 17 00:00:00 2001
2 From: Joakim Zhang <qiangqing.zhang@nxp.com>
3 Date: Fri, 12 Jul 2019 08:02:51 +0000
4 Subject: [PATCH] can: flexcan: add ISO CAN FD feature support
6 ISO CAN FD is introduced to increase the failture detection capability
7 than non-ISO CAN FD. The non-ISO CAN FD is still supported by FlexCAN so
8 that it can be used mainly during an intermediate phase, for evaluation
9 and development purposes.
11 Therefore, it is strongly recommended to configure FlexCAN to the ISO
12 CAN FD protocol by setting the ISOCANFDEN field in the CTRL2 register.
14 NOTE: If you only set "fd on", driver will use ISO FD mode by default.
15 You should set "fd-non-iso on" after setting "fd on" if you want to use
18 Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
19 Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
21 drivers/net/can/flexcan.c | 8 +++++++-
22 1 file changed, 7 insertions(+), 1 deletion(-)
24 --- a/drivers/net/can/flexcan.c
25 +++ b/drivers/net/can/flexcan.c
27 #define FLEXCAN_CTRL2_MRP BIT(18)
28 #define FLEXCAN_CTRL2_RRS BIT(17)
29 #define FLEXCAN_CTRL2_EACEN BIT(16)
30 +#define FLEXCAN_CTRL2_ISOCANFDEN BIT(12)
32 /* FLEXCAN memory error control register (MECR) bits */
33 #define FLEXCAN_MECR_ECRWRDIS BIT(31)
34 @@ -1324,6 +1325,7 @@ static int flexcan_chip_start(struct net
35 reg_fdctrl = priv->read(®s->fdctrl) & ~FLEXCAN_FDCTRL_FDRATE;
36 reg_fdctrl &= ~(FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3));
37 reg_mcr = priv->read(®s->mcr) & ~FLEXCAN_MCR_FDEN;
38 + reg_ctrl2 = priv->read(®s->ctrl2) & ~FLEXCAN_CTRL2_ISOCANFDEN;
40 /* support BRS when set CAN FD mode
41 * 64 bytes payload per MB and 7 MBs per RAM block by default
42 @@ -1333,10 +1335,14 @@ static int flexcan_chip_start(struct net
43 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE;
44 reg_fdctrl |= FLEXCAN_FDCTRL_MBDSR1(0x3) | FLEXCAN_FDCTRL_MBDSR0(0x3);
45 reg_mcr |= FLEXCAN_MCR_FDEN;
47 + if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
48 + reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN;
51 priv->write(reg_fdctrl, ®s->fdctrl);
52 priv->write(reg_mcr, ®s->mcr);
53 + priv->write(reg_ctrl2, ®s->ctrl2);
56 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) {
57 @@ -1856,7 +1862,7 @@ static int flexcan_probe(struct platform
59 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_TIMESTAMP_SUPPORT_FD) {
60 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) {
61 - priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD;
62 + priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO;
63 priv->can.bittiming_const = &flexcan_fd_bittiming_const;
64 priv->can.data_bittiming_const = &flexcan_fd_data_bittiming_const;