1 From 7095b3b3b28031708ab74a65c32e84e231bc9d27 Mon Sep 17 00:00:00 2001
2 From: Sandor Yu <Sandor.yu@nxp.com>
3 Date: Wed, 11 Sep 2019 17:18:29 +0800
4 Subject: [PATCH] drm: imx: add imx8mq hdmi support
6 add struct imx_mhdp_device for imx specific.
7 add imx8mq hdmi support.
8 move imx8qm specific functions to plat_data
11 Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
13 drivers/gpu/drm/imx/Makefile | 2 +-
14 drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c | 8 +-
15 drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c | 7 +-
16 drivers/gpu/drm/imx/cdn-mhdp-imx8mq.c | 163 ------------
17 drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c | 437 ++++++++++----------------------
18 drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c | 202 +++++++++++++++
19 drivers/gpu/drm/imx/cdn-mhdp-phy.h | 12 +-
20 drivers/gpu/drm/imx/cdns-mhdp-imx.h | 80 ++++++
21 8 files changed, 421 insertions(+), 490 deletions(-)
22 delete mode 100644 drivers/gpu/drm/imx/cdn-mhdp-imx8mq.c
23 create mode 100644 drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
24 create mode 100644 drivers/gpu/drm/imx/cdns-mhdp-imx.h
26 --- a/drivers/gpu/drm/imx/Makefile
27 +++ b/drivers/gpu/drm/imx/Makefile
28 @@ -9,4 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
29 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
31 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
32 -obj-$(CONFIG_DRM_IMX_CDNS_MHDP) += cdn-mhdp-imx8qm.o cdn-mhdp-imx8mq.o cdn-mhdp-dp-phy.o cdn-mhdp-hdmi-phy.o
33 +obj-$(CONFIG_DRM_IMX_CDNS_MHDP) += cdn-mhdp-imxdrv.o cdn-mhdp-dp-phy.o cdn-mhdp-hdmi-phy.o cdn-mhdp-imx8qm.o
34 --- a/drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c
35 +++ b/drivers/gpu/drm/imx/cdn-mhdp-dp-phy.c
37 #include <linux/clk.h>
38 #include <linux/kernel.h>
39 #include <drm/drm_dp_helper.h>
41 #include <drm/bridge/cdns-mhdp-common.h>
42 #include "cdn-mhdp-phy.h"
44 @@ -477,9 +476,8 @@ static int dp_phy_power_up(struct cdns_m
48 -int cdns_dp_phy_init_imx8mq(struct imx_mhdp_device *hdp)
49 +int cdns_dp_phy_set_imx8mq(struct cdns_mhdp_device *mhdp)
51 - struct cdns_mhdp_device *mhdp = &hdp->mhdp;
54 /* Disable phy clock if PHY in power up state */
55 @@ -504,10 +502,8 @@ int cdns_dp_phy_init_imx8mq(struct imx_m
60 -int cdns_dp_phy_init_imx8qm(struct imx_mhdp_device *hdp)
61 +int cdns_dp_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
63 - struct cdns_mhdp_device *mhdp = &hdp->mhdp;
66 /* Disable phy clock if PHY in power up state */
67 --- a/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
68 +++ b/drivers/gpu/drm/imx/cdn-mhdp-hdmi-phy.c
69 @@ -624,9 +624,8 @@ static int hdmi_phy_power_up(struct cdns
73 -int cdns_hdmi_phy_set_imx8mq(struct imx_mhdp_device *hdp)
74 +int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *mhdp)
76 - struct cdns_mhdp_device *mhdp = &hdp->mhdp;
77 struct drm_display_mode *mode = &mhdp->mode;
80 @@ -653,9 +652,8 @@ int cdns_hdmi_phy_set_imx8mq(struct imx_
84 -int cdns_hdmi_phy_set_imx8qm(struct imx_mhdp_device *hdp)
85 +int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
87 - struct cdns_mhdp_device *mhdp = &hdp->mhdp;
88 struct drm_display_mode *mode = &mhdp->mode;
91 @@ -681,4 +679,3 @@ int cdns_hdmi_phy_set_imx8qm(struct imx_
96 --- a/drivers/gpu/drm/imx/cdn-mhdp-imx8mq.c
100 - * Copyright (C) 2019 NXP Semiconductor, Inc.
102 - * This program is free software; you can redistribute it and/or modify
103 - * it under the terms of the GNU General Public License version 2 as
104 - * published by the Free Software Foundation.
106 -#include <linux/module.h>
107 -#include <linux/platform_device.h>
108 -#include <linux/component.h>
109 -#include <linux/mfd/syscon.h>
110 -#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
111 -#include <drm/drm_of.h>
112 -#include <drm/drmP.h>
113 -#include <drm/drm_crtc_helper.h>
114 -#include <drm/drm_edid.h>
115 -#include <drm/drm_encoder_slave.h>
117 -#include <drm/bridge/cdns-mhdp-imx.h>
118 -#include "cdn-mhdp-phy.h"
119 -#include "imx-drm.h"
122 - struct device *dev;
123 - struct drm_encoder encoder;
126 -static void cdns_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
130 -static void cdns_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
134 -static int cdns_hdmi_imx_atomic_check(struct drm_encoder *encoder,
135 - struct drm_crtc_state *crtc_state,
136 - struct drm_connector_state *conn_state)
141 -static const struct drm_encoder_helper_funcs cdns_hdmi_imx_encoder_helper_funcs = {
142 - .enable = cdns_hdmi_imx_encoder_enable,
143 - .disable = cdns_hdmi_imx_encoder_disable,
144 - .atomic_check = cdns_hdmi_imx_atomic_check,
147 -static const struct drm_encoder_funcs cdns_hdmi_imx_encoder_funcs = {
148 - .destroy = drm_encoder_cleanup,
151 -static struct cdn_plat_data imx8mq_hdmi_drv_data = {
152 - .bind = cdns_hdmi_bind,
153 - .unbind = cdns_hdmi_unbind,
154 - .phy_init = cdns_hdmi_phy_set_imx8mq,
157 -static struct cdn_plat_data imx8mq_dp_drv_data = {
158 - .bind = cdns_dp_bind,
159 - .unbind = cdns_dp_unbind,
160 - .phy_init = cdns_dp_phy_init_imx8mq,
163 -static const struct of_device_id cdns_hdmi_imx_dt_ids[] = {
164 - { .compatible = "cdn,imx8mq-hdmi",
165 - .data = &imx8mq_hdmi_drv_data
167 - { .compatible = "cdn,imx8mq-dp",
168 - .data = &imx8mq_dp_drv_data
172 -MODULE_DEVICE_TABLE(of, cdns_hdmi_imx_dt_ids);
174 -static int cdns_hdmi_imx_bind(struct device *dev, struct device *master,
177 - struct platform_device *pdev = to_platform_device(dev);
178 - const struct cdn_plat_data *plat_data;
179 - const struct of_device_id *match;
180 - struct drm_device *drm = data;
181 - struct drm_encoder *encoder;
182 - struct imx_hdmi *hdmi;
185 - if (!pdev->dev.of_node)
188 - hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
192 - match = of_match_node(cdns_hdmi_imx_dt_ids, pdev->dev.of_node);
193 - plat_data = match->data;
194 - hdmi->dev = &pdev->dev;
195 - encoder = &hdmi->encoder;
197 - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
199 - * If we failed to find the CRTC(s) which this encoder is
200 - * supposed to be connected to, it's because the CRTC has
201 - * not been registered yet. Defer probing, and hope that
202 - * the required CRTC is added later.
204 - if (encoder->possible_crtcs == 0)
205 - return -EPROBE_DEFER;
207 - drm_encoder_helper_add(encoder, &cdns_hdmi_imx_encoder_helper_funcs);
208 - drm_encoder_init(drm, encoder, &cdns_hdmi_imx_encoder_funcs,
209 - DRM_MODE_ENCODER_TMDS, NULL);
211 - ret = plat_data->bind(pdev, encoder, plat_data);
214 - * If cdns_hdmi_bind() fails we'll never call cdns_hdmi_unbind(),
215 - * which would have called the encoder cleanup. Do it manually.
218 - drm_encoder_cleanup(encoder);
223 -static void cdns_hdmi_imx_unbind(struct device *dev, struct device *master,
226 - struct imx_mhdp_device *hdp = dev_get_drvdata(dev);
228 - hdp->plat_data->unbind(dev);
231 -static const struct component_ops cdns_hdmi_imx_ops = {
232 - .bind = cdns_hdmi_imx_bind,
233 - .unbind = cdns_hdmi_imx_unbind,
236 -static int cdns_hdmi_imx_probe(struct platform_device *pdev)
238 - return component_add(&pdev->dev, &cdns_hdmi_imx_ops);
241 -static int cdns_hdmi_imx_remove(struct platform_device *pdev)
243 - component_del(&pdev->dev, &cdns_hdmi_imx_ops);
248 -static struct platform_driver cdns_hdmi_imx_platform_driver = {
249 - .probe = cdns_hdmi_imx_probe,
250 - .remove = cdns_hdmi_imx_remove,
252 - .name = "cdn-hdp-imx8mq",
253 - .of_match_table = cdns_hdmi_imx_dt_ids,
257 -module_platform_driver(cdns_hdmi_imx_platform_driver);
259 -MODULE_AUTHOR("Sandor YU <sandor.yu@nxp.com>");
260 -MODULE_LICENSE("GPL");
261 -MODULE_ALIAS("platform:cdnhdmi-imx");
262 --- a/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
263 +++ b/drivers/gpu/drm/imx/cdn-mhdp-imx8qm.c
266 - * Copyright (C) 2019 NXP Semiconductor, Inc.
267 + * copyright (c) 2019 nxp semiconductor, inc.
269 - * This program is free software; you can redistribute it and/or modify
270 - * it under the terms of the GNU General Public License version 2 as
271 - * published by the Free Software Foundation.
272 + * this program is free software; you can redistribute it and/or modify
273 + * it under the terms of the gnu general public license version 2 as
274 + * published by the free software foundation.
276 #include <dt-bindings/firmware/imx/rsrc.h>
277 -#include <linux/clk.h>
278 -#include <linux/module.h>
279 -#include <linux/platform_device.h>
280 -#include <linux/component.h>
281 -#include <drm/drm_of.h>
282 -#include <drm/drmP.h>
283 -#include <drm/drm_crtc_helper.h>
284 -#include <drm/drm_encoder_slave.h>
285 #include <linux/firmware/imx/sci.h>
286 -#include <linux/regmap.h>
287 #include <linux/pm_domain.h>
288 +#include <linux/clk.h>
289 +#include <drm/drmP.h>
291 -#include <drm/bridge/cdns-mhdp-imx.h>
292 -#include "cdn-mhdp-phy.h"
293 -#include "imx-drm.h"
294 +#include "cdns-mhdp-imx.h"
296 #define CSR_PIXEL_LINK_MUX_CTL 0x00
297 -#define PL_MUX_CTL_VCP_OFFSET 5
298 -#define PL_MUX_CTL_HCP_OFFSET 4
299 +#define CSR_PIXEL_LINK_MUX_VCP_OFFSET 5
300 +#define CSR_PIXEL_LINK_MUX_HCP_OFFSET 4
302 #define PLL_800MHZ (800000000)
305 - struct device *dev;
306 - struct drm_encoder encoder;
309 -static void imx8qm_pixel_link_mux(struct imx_mhdp_device *hdp)
310 +static void imx8qm_pixel_link_mux(struct imx_mhdp_device *imx_mhdp)
312 - struct drm_display_mode *mode = &hdp->mhdp.mode;
313 + struct drm_display_mode *mode = &imx_mhdp->mhdp.mode;
317 - if (hdp->dual_mode)
318 + if (imx_mhdp->dual_mode)
319 val |= 0x2; /* pixel link 0 and 1 are active */
320 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
321 - val |= 1 << PL_MUX_CTL_VCP_OFFSET;
322 + val |= 1 << CSR_PIXEL_LINK_MUX_VCP_OFFSET;
323 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
324 - val |= 1 << PL_MUX_CTL_HCP_OFFSET;
325 + val |= 1 << CSR_PIXEL_LINK_MUX_HCP_OFFSET;
326 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
329 - regmap_write(hdp->regmap_csr, hdp->csr_pxl_mux_reg, val);
330 + writel(val, imx_mhdp->mhdp.regs_sec);
333 static void imx8qm_pixel_link_valid(u32 dual_mode)
334 @@ -120,10 +106,10 @@ static void imx8qm_clk_mux(u8 is_dp)
335 imx_sc_misc_set_control(handle, IMX_SC_R_HDMI, IMX_SC_C_MODE, 0);
338 -int imx8qm_clocks_init(struct imx_mhdp_device *hdp)
339 +int imx8qm_clocks_init(struct imx_mhdp_device *imx_mhdp)
341 - struct device *dev = hdp->mhdp.dev;
342 - struct imx_hdp_clks *clks = &hdp->clks;
343 + struct device *dev = imx_mhdp->mhdp.dev;
344 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
346 clks->dig_pll = devm_clk_get(dev, "dig_pll");
347 if (IS_ERR(clks->dig_pll)) {
348 @@ -229,10 +215,10 @@ int imx8qm_clocks_init(struct imx_mhdp_d
352 -static int imx8qm_pixel_clk_enable(struct imx_mhdp_device *hdp)
353 +static int imx8qm_pixel_clk_enable(struct imx_mhdp_device *imx_mhdp)
355 - struct imx_hdp_clks *clks = &hdp->clks;
356 - struct device *dev = hdp->mhdp.dev;
357 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
358 + struct device *dev = imx_mhdp->mhdp.dev;
361 ret = clk_prepare_enable(clks->av_pll);
362 @@ -273,12 +259,11 @@ static int imx8qm_pixel_clk_enable(struc
369 -static void imx8qm_pixel_clk_disable(struct imx_mhdp_device *hdp)
370 +static void imx8qm_pixel_clk_disable(struct imx_mhdp_device *imx_mhdp)
372 - struct imx_hdp_clks *clks = &hdp->clks;
373 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
375 clk_disable_unprepare(clks->lpcg_pxl);
376 clk_disable_unprepare(clks->lpcg_hdp);
377 @@ -289,14 +274,14 @@ static void imx8qm_pixel_clk_disable(str
378 clk_disable_unprepare(clks->av_pll);
381 -static void imx8qm_pixel_clk_set_rate(struct imx_mhdp_device *hdp, u32 pclock)
382 +static void imx8qm_pixel_clk_set_rate(struct imx_mhdp_device *imx_mhdp, u32 pclock)
384 - struct imx_hdp_clks *clks = &hdp->clks;
385 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
387 /* pixel clock for HDMI */
388 clk_set_rate(clks->av_pll, pclock);
390 - if (hdp->dual_mode == true) {
391 + if (imx_mhdp->dual_mode == true) {
392 clk_set_rate(clks->clk_pxl, pclock/2);
393 clk_set_rate(clks->clk_pxl_link, pclock/2);
395 @@ -306,24 +291,11 @@ static void imx8qm_pixel_clk_set_rate(st
396 clk_set_rate(clks->clk_pxl_mux, pclock);
399 -static void imx8qm_pixel_clk_rate_change(struct imx_mhdp_device *hdp)
401 - /* set pixel clock before video mode setup */
402 - imx8qm_pixel_clk_disable(hdp);
404 - imx8qm_pixel_clk_set_rate(hdp, hdp->mhdp.mode.clock * 1000);
406 - imx8qm_pixel_clk_enable(hdp);
408 - /* Config pixel link mux */
409 - imx8qm_pixel_link_mux(hdp);
412 -static int imx8qm_ipg_clk_enable(struct imx_mhdp_device *hdp)
413 +static int imx8qm_ipg_clk_enable(struct imx_mhdp_device *imx_mhdp)
416 - struct imx_hdp_clks *clks = &hdp->clks;
417 - struct device *dev = hdp->mhdp.dev;
418 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
419 + struct device *dev = imx_mhdp->mhdp.dev;
421 ret = clk_prepare_enable(clks->dig_pll);
423 @@ -381,25 +353,9 @@ static int imx8qm_ipg_clk_enable(struct
427 -static void imx8qm_ipg_clk_disable(struct imx_mhdp_device *hdp)
429 - struct imx_hdp_clks *clks = &hdp->clks;
431 - clk_disable_unprepare(clks->clk_i2s_bypass);
432 - clk_disable_unprepare(clks->lpcg_i2s);
433 - clk_disable_unprepare(clks->lpcg_apb_ctrl);
434 - clk_disable_unprepare(clks->lpcg_apb_csr);
435 - clk_disable_unprepare(clks->lpcg_msi);
436 - clk_disable_unprepare(clks->lpcg_lis);
437 - clk_disable_unprepare(clks->lpcg_apb);
438 - clk_disable_unprepare(clks->clk_core);
439 - clk_disable_unprepare(clks->clk_ipg);
440 - clk_disable_unprepare(clks->dig_pll);
443 -static void imx8qm_ipg_clk_set_rate(struct imx_mhdp_device *hdp)
444 +static void imx8qm_ipg_clk_set_rate(struct imx_mhdp_device *imx_mhdp)
446 - struct imx_hdp_clks *clks = &hdp->clks;
447 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
450 clk_set_rate(clks->dig_pll, PLL_800MHZ);
451 @@ -407,308 +363,171 @@ static void imx8qm_ipg_clk_set_rate(stru
452 clk_set_rate(clks->clk_ipg, PLL_800MHZ/8);
455 -static void imx8qm_detach_pm_domains(struct imx_mhdp_device *hdp)
456 +static void imx8qm_detach_pm_domains(struct imx_mhdp_device *imx_mhdp)
458 - if (hdp->pd_pll1_link && !IS_ERR(hdp->pd_pll1_link))
459 - device_link_del(hdp->pd_pll1_link);
460 - if (hdp->pd_pll1_dev && !IS_ERR(hdp->pd_pll1_dev))
461 - dev_pm_domain_detach(hdp->pd_pll1_dev, true);
463 - if (hdp->pd_pll0_link && !IS_ERR(hdp->pd_pll0_link))
464 - device_link_del(hdp->pd_pll0_link);
465 - if (hdp->pd_pll0_dev && !IS_ERR(hdp->pd_pll0_dev))
466 - dev_pm_domain_detach(hdp->pd_pll0_dev, true);
468 - if (hdp->pd_mhdp_link && !IS_ERR(hdp->pd_mhdp_link))
469 - device_link_del(hdp->pd_mhdp_link);
470 - if (hdp->pd_mhdp_dev && !IS_ERR(hdp->pd_mhdp_dev))
471 - dev_pm_domain_detach(hdp->pd_mhdp_dev, true);
473 - hdp->pd_mhdp_dev = NULL;
474 - hdp->pd_mhdp_link = NULL;
475 - hdp->pd_pll0_dev = NULL;
476 - hdp->pd_pll0_link = NULL;
477 - hdp->pd_pll1_dev = NULL;
478 - hdp->pd_pll1_link = NULL;
479 + if (imx_mhdp->pd_pll1_link && !IS_ERR(imx_mhdp->pd_pll1_link))
480 + device_link_del(imx_mhdp->pd_pll1_link);
481 + if (imx_mhdp->pd_pll1_dev && !IS_ERR(imx_mhdp->pd_pll1_dev))
482 + dev_pm_domain_detach(imx_mhdp->pd_pll1_dev, true);
484 + if (imx_mhdp->pd_pll0_link && !IS_ERR(imx_mhdp->pd_pll0_link))
485 + device_link_del(imx_mhdp->pd_pll0_link);
486 + if (imx_mhdp->pd_pll0_dev && !IS_ERR(imx_mhdp->pd_pll0_dev))
487 + dev_pm_domain_detach(imx_mhdp->pd_pll0_dev, true);
489 + if (imx_mhdp->pd_mhdp_link && !IS_ERR(imx_mhdp->pd_mhdp_link))
490 + device_link_del(imx_mhdp->pd_mhdp_link);
491 + if (imx_mhdp->pd_mhdp_dev && !IS_ERR(imx_mhdp->pd_mhdp_dev))
492 + dev_pm_domain_detach(imx_mhdp->pd_mhdp_dev, true);
494 + imx_mhdp->pd_mhdp_dev = NULL;
495 + imx_mhdp->pd_mhdp_link = NULL;
496 + imx_mhdp->pd_pll0_dev = NULL;
497 + imx_mhdp->pd_pll0_link = NULL;
498 + imx_mhdp->pd_pll1_dev = NULL;
499 + imx_mhdp->pd_pll1_link = NULL;
502 -static int imx8qm_attach_pm_domains(struct imx_mhdp_device *hdp)
503 +static int imx8qm_attach_pm_domains(struct imx_mhdp_device *imx_mhdp)
505 - struct device *dev = hdp->mhdp.dev;
506 + struct device *dev = imx_mhdp->mhdp.dev;
507 u32 flags = DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE;
510 - hdp->pd_mhdp_dev = dev_pm_domain_attach_by_name(dev, "hdmi");
511 - if (IS_ERR(hdp->pd_mhdp_dev)) {
512 - ret = PTR_ERR(hdp->pd_mhdp_dev);
513 + imx_mhdp->pd_mhdp_dev = dev_pm_domain_attach_by_name(dev, "hdmi");
514 + if (IS_ERR(imx_mhdp->pd_mhdp_dev)) {
515 + ret = PTR_ERR(imx_mhdp->pd_mhdp_dev);
516 dev_err(dev, "Failed to attach dc pd dev: %d\n", ret);
519 - hdp->pd_mhdp_link = device_link_add(dev, hdp->pd_mhdp_dev, flags);
520 - if (IS_ERR(hdp->pd_mhdp_link)) {
521 - ret = PTR_ERR(hdp->pd_mhdp_link);
522 + imx_mhdp->pd_mhdp_link = device_link_add(dev, imx_mhdp->pd_mhdp_dev, flags);
523 + if (IS_ERR(imx_mhdp->pd_mhdp_link)) {
524 + ret = PTR_ERR(imx_mhdp->pd_mhdp_link);
525 dev_err(dev, "Failed to add device link to dc pd dev: %d\n",
530 - hdp->pd_pll0_dev = dev_pm_domain_attach_by_name(dev, "pll0");
531 - if (IS_ERR(hdp->pd_pll0_dev)) {
532 - ret = PTR_ERR(hdp->pd_pll0_dev);
533 + imx_mhdp->pd_pll0_dev = dev_pm_domain_attach_by_name(dev, "pll0");
534 + if (IS_ERR(imx_mhdp->pd_pll0_dev)) {
535 + ret = PTR_ERR(imx_mhdp->pd_pll0_dev);
536 dev_err(dev, "Failed to attach pll0 pd dev: %d\n", ret);
539 - hdp->pd_pll0_link = device_link_add(dev, hdp->pd_pll0_dev, flags);
540 - if (IS_ERR(hdp->pd_pll0_link)) {
541 - ret = PTR_ERR(hdp->pd_pll0_link);
542 + imx_mhdp->pd_pll0_link = device_link_add(dev, imx_mhdp->pd_pll0_dev, flags);
543 + if (IS_ERR(imx_mhdp->pd_pll0_link)) {
544 + ret = PTR_ERR(imx_mhdp->pd_pll0_link);
545 dev_err(dev, "Failed to add device link to pll0 pd dev: %d\n",
550 - hdp->pd_pll1_dev = dev_pm_domain_attach_by_name(dev, "pll1");
551 - if (IS_ERR(hdp->pd_pll1_dev)) {
552 - ret = PTR_ERR(hdp->pd_pll1_dev);
553 + imx_mhdp->pd_pll1_dev = dev_pm_domain_attach_by_name(dev, "pll1");
554 + if (IS_ERR(imx_mhdp->pd_pll1_dev)) {
555 + ret = PTR_ERR(imx_mhdp->pd_pll1_dev);
556 dev_err(dev, "Failed to attach pll0 pd dev: %d\n", ret);
559 - hdp->pd_pll1_link = device_link_add(dev, hdp->pd_pll1_dev, flags);
560 - if (IS_ERR(hdp->pd_pll1_link)) {
561 - ret = PTR_ERR(hdp->pd_pll1_link);
562 + imx_mhdp->pd_pll1_link = device_link_add(dev, imx_mhdp->pd_pll1_dev, flags);
563 + if (IS_ERR(imx_mhdp->pd_pll1_link)) {
564 + ret = PTR_ERR(imx_mhdp->pd_pll1_link);
565 dev_err(dev, "Failed to add device link to pll1 pd dev: %d\n",
570 - imx8qm_detach_pm_domains(hdp);
571 + imx8qm_detach_pm_domains(imx_mhdp);
575 -static int imx8qm_firmware_init(struct imx_mhdp_device *hdp)
576 +static void imx8qm_mhdp_power_on(struct cdns_mhdp_device *mhdp)
581 + struct imx_mhdp_device *imx_mhdp =
582 + container_of(mhdp, struct imx_mhdp_device, mhdp);
583 /* Power on PM Domains */
584 - imx8qm_attach_pm_domains(hdp);
586 + imx8qm_attach_pm_domains(imx_mhdp);
588 /* clock init and rate set */
589 - imx8qm_clocks_init(hdp);
590 + imx8qm_clocks_init(imx_mhdp);
592 - imx8qm_ipg_clk_set_rate(hdp);
593 + imx8qm_ipg_clk_set_rate(imx_mhdp);
595 /* Init pixel clock with 148.5MHz before FW init */
596 - imx8qm_pixel_clk_set_rate(hdp, 148500000);
597 + imx8qm_pixel_clk_set_rate(imx_mhdp, 148500000);
599 - imx8qm_ipg_clk_enable(hdp);
600 + imx8qm_ipg_clk_enable(imx_mhdp);
602 - imx8qm_clk_mux(hdp->plat_data->is_dp);
603 + imx8qm_clk_mux(imx_mhdp->mhdp.plat_data->is_dp);
605 - imx8qm_pixel_clk_enable(hdp);
606 + imx8qm_pixel_clk_enable(imx_mhdp);
610 - hdp->csr_pxl_mux_reg = 0;
611 - hdp->csr_ctrl0_reg = 0x8;
612 - hdp->csr_ctrl0_sec = 0xc;
613 - /* iMX8QM HDP register, Remap HPD memory address to low 4K */
614 - regmap_write(hdp->regmap_csr, hdp->csr_ctrl0_reg, 0);
616 - /* configure HDMI/DP core clock */
617 - rate = clk_get_rate(hdp->clks.clk_core);
618 - cdns_mhdp_set_fw_clk(&hdp->mhdp, rate);
620 - /* un-reset ucpu */
621 - writel(0, (APB_CTRL << 2) + hdp->mhdp.regs);
622 - DRM_INFO("Started firmware!\n");
624 - ret = cdns_mhdp_check_alive(&hdp->mhdp);
625 - if (ret == false) {
626 - DRM_ERROR("NO HDMI FW running\n");
630 - /* turn on IP activity */
631 - cdns_mhdp_set_firmware_active(&hdp->mhdp, 1);
633 - DRM_INFO("HDP FW Version - ver %d verlib %d\n",
634 - __raw_readb(VER_L + hdp->mhdp.regs) + (__raw_readb(VER_H + hdp->mhdp.regs) << 8),
635 - __raw_readb(VER_LIB_L_ADDR + hdp->mhdp.regs) + (__raw_readb(VER_LIB_H_ADDR + hdp->mhdp.regs) << 8));
640 -static void cdns_hdmi_imx_encoder_disable(struct drm_encoder *encoder)
641 +void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp)
643 - struct imx_mhdp_device *hdp = encoder->bridge->driver_private;
644 + struct imx_mhdp_device *imx_mhdp =
645 + container_of(mhdp, struct imx_mhdp_device, mhdp);
647 - imx8qm_pixel_link_sync_disable(hdp->dual_mode);
648 - imx8qm_pixel_link_invalid(hdp->dual_mode);
649 + imx8qm_pixel_link_sync_disable(imx_mhdp->dual_mode);
650 + imx8qm_pixel_link_invalid(imx_mhdp->dual_mode);
653 -static void cdns_hdmi_imx_encoder_enable(struct drm_encoder *encoder)
654 +void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp)
656 - struct imx_mhdp_device *hdp = encoder->bridge->driver_private;
657 + struct imx_mhdp_device *imx_mhdp =
658 + container_of(mhdp, struct imx_mhdp_device, mhdp);
660 - imx8qm_pixel_link_valid(hdp->dual_mode);
661 - imx8qm_pixel_link_sync_enable(hdp->dual_mode);
662 + imx8qm_pixel_link_valid(imx_mhdp->dual_mode);
663 + imx8qm_pixel_link_sync_enable(imx_mhdp->dual_mode);
666 -static int cdns_hdmi_imx_encoder_atomic_check(struct drm_encoder *encoder,
667 - struct drm_crtc_state *crtc_state,
668 - struct drm_connector_state *conn_state)
669 +void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp)
671 - struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
673 - imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB101010_1X30;
676 + struct imx_mhdp_device *imx_mhdp =
677 + container_of(mhdp, struct imx_mhdp_device, mhdp);
679 -static const struct drm_encoder_helper_funcs cdns_hdmi_imx_encoder_helper_funcs = {
680 - .enable = cdns_hdmi_imx_encoder_enable,
681 - .disable = cdns_hdmi_imx_encoder_disable,
682 - .atomic_check = cdns_hdmi_imx_encoder_atomic_check,
685 -static const struct drm_encoder_funcs cdns_hdmi_imx_encoder_funcs = {
686 - .destroy = drm_encoder_cleanup,
690 -static struct cdn_plat_data imx8mq_hdmi_drv_data = {
691 - .bind = cdns_hdmi_bind,
692 - .unbind = cdns_hdmi_unbind,
693 - .phy_init = cdns_hdmi_phy_set_imx8mq,
696 -static struct cdn_plat_data imx8mq_dp_drv_data = {
697 - .bind = cdns_dp_bind,
698 - .unbind = cdns_dp_unbind,
699 - .phy_init = cdns_dp_phy_init_imx8mq,
703 -static struct cdn_plat_data imx8qm_hdmi_drv_data = {
704 - .bind = cdns_hdmi_bind,
705 - .unbind = cdns_hdmi_unbind,
706 - .phy_init = cdns_hdmi_phy_set_imx8qm,
707 - .fw_init = imx8qm_firmware_init,
708 - .pclock_change = imx8qm_pixel_clk_rate_change,
711 -static struct cdn_plat_data imx8qm_dp_drv_data = {
712 - .bind = cdns_dp_bind,
713 - .unbind = cdns_dp_unbind,
714 - .phy_init = cdns_dp_phy_init_imx8qm,
715 - .fw_init = imx8qm_firmware_init,
716 - .pclock_change = imx8qm_pixel_clk_rate_change,
720 -static const struct of_device_id cdns_hdmi_imx_dt_ids[] = {
722 - { .compatible = "cdn,imx8mq-hdmi",
723 - .data = &imx8mq_hdmi_drv_data
725 - { .compatible = "cdn,imx8mq-dp",
726 - .data = &imx8mq_dp_drv_data
729 - { .compatible = "cdn,imx8qm-hdmi",
730 - .data = &imx8qm_hdmi_drv_data
732 - { .compatible = "cdn,imx8qm-dp",
733 - .data = &imx8qm_dp_drv_data
737 -MODULE_DEVICE_TABLE(of, cdns_hdmi_imx_dt_ids);
739 -static int cdns_hdmi_imx_bind(struct device *dev, struct device *master,
742 - struct platform_device *pdev = to_platform_device(dev);
743 - const struct cdn_plat_data *plat_data;
744 - const struct of_device_id *match;
745 - struct drm_device *drm = data;
746 - struct drm_encoder *encoder;
747 - struct imx_hdmi *hdmi;
749 + /* set pixel clock before video mode setup */
750 + imx8qm_pixel_clk_disable(imx_mhdp);
752 - if (!pdev->dev.of_node)
754 + imx8qm_pixel_clk_set_rate(imx_mhdp, imx_mhdp->mhdp.mode.clock * 1000);
756 - hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
760 - match = of_match_node(cdns_hdmi_imx_dt_ids, pdev->dev.of_node);
761 - plat_data = match->data;
762 - hdmi->dev = &pdev->dev;
763 - encoder = &hdmi->encoder;
765 - encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
767 - * If we failed to find the CRTC(s) which this encoder is
768 - * supposed to be connected to, it's because the CRTC has
769 - * not been registered yet. Defer probing, and hope that
770 - * the required CRTC is added later.
772 - if (encoder->possible_crtcs == 0)
773 - return -EPROBE_DEFER;
775 - drm_encoder_helper_add(encoder, &cdns_hdmi_imx_encoder_helper_funcs);
776 - drm_encoder_init(drm, encoder, &cdns_hdmi_imx_encoder_funcs,
777 - DRM_MODE_ENCODER_TMDS, NULL);
779 - ret = plat_data->bind(pdev, encoder, plat_data);
782 - * If cdns_hdmi_bind() fails we'll never call cdns_hdmi_unbind(),
783 - * which would have called the encoder cleanup. Do it manually.
786 - drm_encoder_cleanup(encoder);
787 + imx8qm_pixel_clk_enable(imx_mhdp);
790 + /* Config pixel link mux */
791 + imx8qm_pixel_link_mux(imx_mhdp);
794 -static void cdns_hdmi_imx_unbind(struct device *dev, struct device *master,
796 +int cdns_mhdp_firmware_init_imx8qm(struct cdns_mhdp_device *mhdp)
798 - struct imx_mhdp_device *hdp = dev_get_drvdata(dev);
799 + struct imx_mhdp_device *imx_mhdp =
800 + container_of(mhdp, struct imx_mhdp_device, mhdp);
804 - hdp->plat_data->unbind(dev);
806 + imx8qm_mhdp_power_on(mhdp);
808 -static const struct component_ops cdns_hdmi_imx8qm_ops = {
809 - .bind = cdns_hdmi_imx_bind,
810 - .unbind = cdns_hdmi_imx_unbind,
812 + /* configure HDMI/DP core clock */
813 + rate = clk_get_rate(imx_mhdp->clks.clk_core);
814 + cdns_mhdp_set_fw_clk(&imx_mhdp->mhdp, rate);
816 -static int cdns_hdmi_imx_probe(struct platform_device *pdev)
818 - return component_add(&pdev->dev, &cdns_hdmi_imx8qm_ops);
820 + /* un-reset ucpu */
821 + cdns_mhdp_bus_write(0, &imx_mhdp->mhdp, APB_CTRL);
822 + DRM_INFO("Started firmware!\n");
824 -static int cdns_hdmi_imx_remove(struct platform_device *pdev)
826 - component_del(&pdev->dev, &cdns_hdmi_imx8qm_ops);
827 + ret = cdns_mhdp_check_alive(&imx_mhdp->mhdp);
828 + if (ret == false) {
829 + DRM_ERROR("NO HDMI FW running\n");
833 + /* turn on IP activity */
834 + cdns_mhdp_set_firmware_active(&imx_mhdp->mhdp, 1);
836 + DRM_INFO("HDP FW Version - ver %d verlib %d\n",
837 + cdns_mhdp_bus_read(mhdp, VER_L) + (cdns_mhdp_bus_read(mhdp, VER_H) << 8),
838 + cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) + (cdns_mhdp_bus_read(mhdp, VER_LIB_H_ADDR) << 8));
843 -static struct platform_driver cdns_hdmi_imx_platform_driver = {
844 - .probe = cdns_hdmi_imx_probe,
845 - .remove = cdns_hdmi_imx_remove,
847 - .name = "cdn-hdp-imx8qm",
848 - .of_match_table = cdns_hdmi_imx_dt_ids,
852 -module_platform_driver(cdns_hdmi_imx_platform_driver);
854 -MODULE_AUTHOR("Sandor YU <sandor.yu@nxp.com>");
855 -MODULE_LICENSE("GPL");
856 -MODULE_ALIAS("platform:cdnhdmi-imx");
858 +++ b/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
861 + * copyright (c) 2019 nxp semiconductor, inc.
863 + * this program is free software; you can redistribute it and/or modify
864 + * it under the terms of the gnu general public license version 2 as
865 + * published by the free software foundation.
867 +#include <linux/module.h>
868 +#include <linux/platform_device.h>
869 +#include <linux/component.h>
870 +#include <drm/drm_of.h>
871 +#include <drm/drmP.h>
872 +#include <drm/drm_crtc_helper.h>
873 +#include <drm/drm_encoder_slave.h>
875 +#include "cdns-mhdp-imx.h"
876 +#include "cdn-mhdp-phy.h"
877 +#include "imx-drm.h"
879 +static void cdns_mhdp_imx_encoder_disable(struct drm_encoder *encoder)
881 + struct cdns_mhdp_device *mhdp = encoder->bridge->driver_private;
883 + cdns_mhdp_plat_call(mhdp, plat_init);
886 +static void cdns_mhdp_imx_encoder_enable(struct drm_encoder *encoder)
888 + struct cdns_mhdp_device *mhdp = encoder->bridge->driver_private;
890 + cdns_mhdp_plat_call(mhdp, plat_deinit);
893 +static int cdns_mhdp_imx_encoder_atomic_check(struct drm_encoder *encoder,
894 + struct drm_crtc_state *crtc_state,
895 + struct drm_connector_state *conn_state)
897 + struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
898 + struct cdns_mhdp_device *mhdp = encoder->bridge->driver_private;
900 + if (mhdp->plat_data->video_format != 0)
901 + imx_crtc_state->bus_format = mhdp->plat_data->video_format;
905 +static const struct drm_encoder_helper_funcs cdns_mhdp_imx_encoder_helper_funcs = {
906 + .enable = cdns_mhdp_imx_encoder_enable,
907 + .disable = cdns_mhdp_imx_encoder_disable,
908 + .atomic_check = cdns_mhdp_imx_encoder_atomic_check,
911 +static const struct drm_encoder_funcs cdns_mhdp_imx_encoder_funcs = {
912 + .destroy = drm_encoder_cleanup,
915 +static struct cdns_plat_data imx8mq_hdmi_drv_data = {
916 + .bind = cdns_hdmi_bind,
917 + .unbind = cdns_hdmi_unbind,
918 + .phy_set = cdns_hdmi_phy_set_imx8mq,
919 + .bus_type = BUS_TYPE_NORMAL_APB,
922 +static struct cdns_plat_data imx8mq_dp_drv_data = {
923 + .bind = cdns_dp_bind,
924 + .unbind = cdns_dp_unbind,
925 + .phy_set = cdns_dp_phy_set_imx8mq,
926 + .bus_type = BUS_TYPE_NORMAL_APB,
929 +static struct cdns_plat_data imx8qm_hdmi_drv_data = {
930 + .bind = cdns_hdmi_bind,
931 + .unbind = cdns_hdmi_unbind,
932 + .phy_set = cdns_hdmi_phy_set_imx8qm,
933 + .firmware_init = cdns_mhdp_firmware_init_imx8qm,
934 + .pclk_rate = cdns_mhdp_pclk_rate_imx8qm,
935 + .plat_init = cdns_mhdp_plat_init_imx8qm,
936 + .plat_deinit = cdns_mhdp_plat_deinit_imx8qm,
937 + .bus_type = BUS_TYPE_LOW4K_APB,
938 + .video_format = MEDIA_BUS_FMT_RGB101010_1X30,
941 +static struct cdns_plat_data imx8qm_dp_drv_data = {
942 + .bind = cdns_dp_bind,
943 + .unbind = cdns_dp_unbind,
944 + .phy_set = cdns_dp_phy_set_imx8qm,
945 + .firmware_init = cdns_mhdp_firmware_init_imx8qm,
946 + .pclk_rate = cdns_mhdp_pclk_rate_imx8qm,
947 + .plat_init = cdns_mhdp_plat_init_imx8qm,
948 + .plat_deinit = cdns_mhdp_plat_deinit_imx8qm,
949 + .bus_type = BUS_TYPE_LOW4K_APB,
950 + .video_format = MEDIA_BUS_FMT_RGB101010_1X30,
954 +static const struct of_device_id cdns_mhdp_imx_dt_ids[] = {
955 + { .compatible = "cdn,imx8mq-hdmi",
956 + .data = &imx8mq_hdmi_drv_data
958 + { .compatible = "cdn,imx8mq-dp",
959 + .data = &imx8mq_dp_drv_data
961 + { .compatible = "cdn,imx8qm-hdmi",
962 + .data = &imx8qm_hdmi_drv_data
964 + { .compatible = "cdn,imx8qm-dp",
965 + .data = &imx8qm_dp_drv_data
969 +MODULE_DEVICE_TABLE(of, cdns_mhdp_imx_dt_ids);
971 +static int cdns_mhdp_imx_bind(struct device *dev, struct device *master,
974 + struct platform_device *pdev = to_platform_device(dev);
975 + const struct cdns_plat_data *plat_data;
976 + const struct of_device_id *match;
977 + struct drm_device *drm = data;
978 + struct drm_encoder *encoder;
979 + struct imx_mhdp_device *imx_mhdp;
982 + if (!pdev->dev.of_node)
985 + imx_mhdp = devm_kzalloc(&pdev->dev, sizeof(*imx_mhdp), GFP_KERNEL);
989 + match = of_match_node(cdns_mhdp_imx_dt_ids, pdev->dev.of_node);
990 + plat_data = match->data;
991 + encoder = &imx_mhdp->encoder;
993 + encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
995 + * If we failed to find the CRTC(s) which this encoder is
996 + * supposed to be connected to, it's because the CRTC has
997 + * not been registered yet. Defer probing, and hope that
998 + * the required CRTC is added later.
1000 + if (encoder->possible_crtcs == 0)
1001 + return -EPROBE_DEFER;
1003 + drm_encoder_helper_add(encoder, &cdns_mhdp_imx_encoder_helper_funcs);
1004 + drm_encoder_init(drm, encoder, &cdns_mhdp_imx_encoder_funcs,
1005 + DRM_MODE_ENCODER_TMDS, NULL);
1008 + imx_mhdp->mhdp.plat_data = plat_data;
1009 + imx_mhdp->mhdp.dev = dev;
1010 + imx_mhdp->mhdp.bus_type = plat_data->bus_type;
1011 + ret = plat_data->bind(pdev, encoder, &imx_mhdp->mhdp);
1013 + * If cdns_mhdp_bind() fails we'll never call cdns_mhdp_unbind(),
1014 + * which would have called the encoder cleanup. Do it manually.
1017 + drm_encoder_cleanup(encoder);
1019 + imx_mhdp->dual_mode = false;
1023 +static void cdns_mhdp_imx_unbind(struct device *dev, struct device *master,
1026 + struct imx_mhdp_device *imx_mhdp = dev_get_drvdata(dev);
1028 + imx_mhdp->mhdp.plat_data->unbind(dev);
1031 +static const struct component_ops cdns_mhdp_imx_ops = {
1032 + .bind = cdns_mhdp_imx_bind,
1033 + .unbind = cdns_mhdp_imx_unbind,
1036 +static int cdns_mhdp_imx_probe(struct platform_device *pdev)
1038 + return component_add(&pdev->dev, &cdns_mhdp_imx_ops);
1041 +static int cdns_mhdp_imx_remove(struct platform_device *pdev)
1043 + component_del(&pdev->dev, &cdns_mhdp_imx_ops);
1048 +static struct platform_driver cdns_mhdp_imx_platform_driver = {
1049 + .probe = cdns_mhdp_imx_probe,
1050 + .remove = cdns_mhdp_imx_remove,
1052 + .name = "cdn-hdp-imx8qm",
1053 + .of_match_table = cdns_mhdp_imx_dt_ids,
1057 +module_platform_driver(cdns_mhdp_imx_platform_driver);
1059 +MODULE_AUTHOR("Sandor YU <sandor.yu@nxp.com>");
1060 +MODULE_LICENSE("GPL");
1061 +MODULE_ALIAS("platform:cdnhdmi-imx");
1062 --- a/drivers/gpu/drm/imx/cdn-mhdp-phy.h
1063 +++ b/drivers/gpu/drm/imx/cdn-mhdp-phy.h
1065 #ifndef _CDN_DP_PHY_H
1066 #define _CDN_DP_PHY_H
1068 -#include <drm/bridge/cdns-mhdp-imx.h>
1069 +#include <drm/bridge/cdns-mhdp-common.h>
1071 #define CMN_SSM_BIAS_TMR 0x0022
1072 #define CMN_PLLSM0_PLLEN_TMR 0x0029
1074 #define PHY_PMA_ISO_RX_DATA_LO 0xCC16
1075 #define PHY_PMA_ISO_RX_DATA_HI 0xCC17
1077 -int cdns_dp_phy_init_imx8mq(struct imx_mhdp_device *hdp);
1078 -int cdns_dp_phy_init_imx8qm(struct imx_mhdp_device *hdp);
1079 -int cdns_hdmi_phy_set_imx8mq(struct imx_mhdp_device *hdp);
1080 -int cdns_hdmi_phy_set_imx8qm(struct imx_mhdp_device *hdp);
1081 -#endif /* _CDN_DP_PHY_H */
1082 +int cdns_dp_phy_set_imx8mq(struct cdns_mhdp_device *hdp);
1083 +int cdns_dp_phy_set_imx8qm(struct cdns_mhdp_device *hdp);
1084 +int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *hdp);
1085 +int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *hdp);
1086 +#endif /* _CDNS_MHDP_PHY_H */
1088 +++ b/drivers/gpu/drm/imx/cdns-mhdp-imx.h
1091 + * Cadence High-Definition Multimedia Interface (HDMI) driver
1093 + * Copyright (C) 2019 NXP Semiconductor, Inc.
1095 + * This program is free software; you can redistribute it and/or modify
1096 + * it under the terms of the GNU General Public License as published by
1097 + * the Free Software Foundation; either version 2 of the License, or
1098 + * (at your option) any later version.
1101 +#ifndef CDNS_MHDP_IMX_H_
1102 +#define CDNS_MHDP_IMX_H_
1104 +#include <drm/bridge/cdns-mhdp-common.h>
1105 +#include <drm/drm_encoder_slave.h>
1108 +#define HDP_DUAL_MODE_MIN_PCLK_RATE 300000 /* KHz */
1109 +#define HDP_SINGLE_MODE_MAX_WIDTH 1920
1111 +static inline bool video_is_dual_mode(const struct drm_display_mode *mode)
1113 + return (mode->clock > HDP_DUAL_MODE_MIN_PCLK_RATE ||
1114 + mode->hdisplay > HDP_SINGLE_MODE_MAX_WIDTH) ? true : false;
1117 +struct imx_mhdp_device;
1119 +struct imx_hdp_clks {
1120 + struct clk *av_pll;
1121 + struct clk *dig_pll;
1122 + struct clk *clk_ipg;
1123 + struct clk *clk_core;
1124 + struct clk *clk_pxl;
1125 + struct clk *clk_pxl_mux;
1126 + struct clk *clk_pxl_link;
1128 + struct clk *lpcg_hdp;
1129 + struct clk *lpcg_msi;
1130 + struct clk *lpcg_pxl;
1131 + struct clk *lpcg_vif;
1132 + struct clk *lpcg_lis;
1133 + struct clk *lpcg_apb;
1134 + struct clk *lpcg_apb_csr;
1135 + struct clk *lpcg_apb_ctrl;
1137 + struct clk *lpcg_i2s;
1138 + struct clk *clk_i2s_bypass;
1141 +struct imx_mhdp_device {
1142 + struct cdns_mhdp_device mhdp;
1143 + struct drm_encoder encoder;
1145 + struct mutex audio_mutex;
1146 + spinlock_t audio_lock;
1150 + struct imx_hdp_clks clks;
1156 + struct device *pd_mhdp_dev;
1157 + struct device *pd_pll0_dev;
1158 + struct device *pd_pll1_dev;
1159 + struct device_link *pd_mhdp_link;
1160 + struct device_link *pd_pll0_link;
1161 + struct device_link *pd_pll1_link;
1165 +void cdns_mhdp_plat_init_imx8qm(struct cdns_mhdp_device *mhdp);
1166 +void cdns_mhdp_plat_deinit_imx8qm(struct cdns_mhdp_device *mhdp);
1167 +void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp);
1168 +int cdns_mhdp_firmware_init_imx8qm(struct cdns_mhdp_device *mhdp);
1169 +#endif /* CDNS_MHDP_IMX_H_ */